This U.S. non-provisional patent application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2007-0090613, filed Sep. 6, 2007, the entire contents of which are hereby incorporated herein by reference.
The present invention relates to integrated circuit devices and, more particularly, to integrated circuit amplifiers and methods of operating same.
In comparison with bipolar or GaAs semiconductor circuits, radio frequency (RF) CMOS circuits may have high 1/f noise (i.e., a low-frequency noise), which is dominant in the frequency domain unlike thermal noise. Also, the down-scaling of CMOS circuits may further degrade the 1/f noise characteristics of CMOS circuits. The down-scaling of CMOS circuits reduces a supply voltage and is advantageous in terms of power amplification. However, the degradation of the 1/f noise characteristics of CMOS circuits further worsens a signal-to-noise ratio (SNR) of CMOS communication semiconductor circuits. Therefore, a communication semiconductor device using a CMOS circuit may have reduce sensitivity, thus degrading the receive (RX) sensitivity of the communication semiconductor device. If a CMOS direct conversion receiver is implemented in a narrowband communication system, such as the Global System for Mobile Communications (GSM), the 1/f noise may become the main noise source of up to several hundreds of kH through several tens of MHz.
Integrated circuit devices according to some embodiments of the present invention include a pair of field effect transistors having shared source terminals, shared drain terminals and shared gate terminals, which may be treated herein as being electrically coupled in parallel. A switch circuit is also provided. The switch circuit is configured to drive a body terminal of a first one of the pair of field effect transistors with an alternating sequence of first and second unequal body voltages. This alternating sequence is synchronized with a first clock signal. The switch circuit is also configured to drive a body terminal of a second one of the pair of field effect transistors with an alternating sequence of third and fourth unequal body voltages, which is synchronized with a second clock signal. The first and third body voltages may have equivalent magnitudes and the second and fourth body voltages may have equivalent magnitudes. In addition, the first and second clock signals may be synchronized with each other. The first and second clock signals may have 50% duty cycles and may be 180 degrees out-of-phase relative to each other.
Additional embodiments of the present invention include a differential amplifier having first and second pairs of field effect transistors and first and second switch circuits. The first pair of field effect transistors have shared first source terminals, shared first drain terminals and shared first gate terminals. The shared first gate terminals are electrically connected to a first input of the differential amplifier. The shared second pair of field effect transistors have shared second source terminals, shared second drain terminals and shared second gate terminals. The shared second gate terminals are electrically connected to a second input of the differential amplifier. The first switch circuit is configured to drive a body terminal of a first one of the first pair of field effect transistors with an alternating sequence of first and second unequal body voltages that is synchronized with a first clock signal. This first switch circuit may also be configured to drive a body terminal of a second one of the first pair of field effect transistors with an alternating sequence of third and fourth unequal body voltages that is synchronized with a second clock signal. Similarly, the second switch circuit is configured to drive a body terminal of a first one of the second pair of field effect transistors with the alternating sequence of the first and second unequal body voltages, and may be further configured to drive a body terminal of a second one of the second pair of field effect transistors with the alternating sequence of third and fourth unequal body voltages.
The differential amplifier according to embodiments of the invention may also include an output circuit, which is electrically coupled to the shared first drain terminals and the shared second drain terminals, and a current mirror circuit, which is electrically coupled to the shared first source terminals and the shared second source terminals.
The accompanying figures are included to provide a further understanding of the present invention, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present invention and, together with the description, serve to explain principles of the present invention. In the figures:
Preferred embodiments of the present invention will be described below in more detail with reference to the accompanying drawings. The present invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art.
A complementary metal oxide semiconductor (CMOS) amplifier according to the present invention can reduce 1/f noise (i.e., a low-frequency noise) by using two field-effect transistors (FETs) connected in parallel. The CMOS amplifier according to the present invention includes: a first transistor including a first source, a first gate, a first drain, and a first body; a second transistor including a second source, a second gate, a second drain, and a second body; a source terminal connecting the first source and the second source in common; a drain terminal connecting the first drain and the second drain in common; a gate terminal connecting the first gate and the second gate in common; a first switch connecting one of a first body voltage and a second body voltage to the first body according to a first clock; and a second switch connecting one of the first body voltage and the second body voltage to the second body according to a second clock.
The CMOS amplifier according to an embodiment of the present invention drives a first transistor and a second transistor alternately in synchronization with a first clock and a second clock, thereby reducing power consumption and 1/f noise. Also, the CMOS amplifier according to the present invention is applied to continuous signal processing.
The first switch SW1 connects one of a first body voltage B1 and a second body voltage B2 to the first body according to the voltage level of a first clock Q1, and the second switch SW2 connects one of the first body voltage B1 and the second body voltage B2 to the second body according to the voltage level a second clock Q2. The first transistor TR1 and the second transistor TR2 are physically identical. The first transistor TR1 and the second transistor TR2 may be implemented using FETs. Also, the first switch SW1 and the second switch SW2 may be implemented using small-sized MOS switches.
Referring to
ΔVth=γ(√{square root over (2|φF|−VSB)}−√{square root over (2|φF|)}) (1)
where ΔVth denotes a variation in a threshold voltage, γ denotes a constant value according to a doping concentration and the SiO2 thickness of a gate terminal, φF denotes the Fermi level, and VSB denotes the bias voltage of a substrate of a transistor. This equation (1) is disclosed in a textbook by Y. J. Park, entitled “VLSI Device Theory,” Kyohak Publishing Co., Ltd., p. 300 (1995) and a textbook by B. Streetman, entitled “Solid State Electronic Design 3rd Edition”, Prentice-Hall, p. 321.
Referring to
Referring to
During the period T2, the first clock Q1 has a low state and the second clock Q2 has a high state. Thus, when the first clock Q1 is in the low state, the first switch SW1 connects the second body voltage B2 to the body of the first transistor TR1 and the second switch SW2 connects the first body voltage B1 to the body of the second transistor TR2. When the first clock Q1 is in the low state, the second body voltage B2 is applied to the body of the first transistor TR1 and the first body voltage B1 is applied to the body of the second transistor TR2. In this case, the threshold voltage of the first transistor TR1 is 0.345 V and the threshold voltage of the second transistor TR2 is 0.57 V. At this point, an input signal is applied from the gate terminal G. The voltage level of the input signal is set to about 0.345 ˜0.57 V, which means the first transistor TR1 is turned on and the second transistor TR2 is turned off. Thus, a signal input from the gate terminal G is output through the first transistor TR1 to the drain terminal D.
If the period T1 plus the period T2 is a cycle T, a current flowing through the drain terminal D during the cycle T is ID. If a current flowing through an FET during the cycle T is ID, the power of the FET is proportional to ID2. On the other hand, in the case of the CMOS amplifier according to embodiments of the present invention, a current flowing during the half cycle (T1 or T2) is 0.5ID and thus a current flowing during the cycle T is ID (i.e., 0.5ID×2). Also, the power of the CMOS amplifier according to the present invention is proportional to 0.5ID2(i.e., 0.25ID2+0.25ID2), which is the sum of the square of a current flowing during the first half cycle T1 and the square of a current flowing during the second half cycle T2.
Because the 1/f noise (i.e., a low-frequency noise) increases in proportion to the power used, a CMOS amplifier according to an embodiment of the present invention may consume about half the power in comparison with the case of using only one FET. Thus, the CMOS amplifier may reduce the 1/f noise by about ½ in comparison with the case of using only one FET. Also, the CMOS amplifier according to the illustrated embodiment enables the transistor to operate continuously. Thus, the CMOS amplifier according to the illustrated embodiments illustrated can be applied to continuous signal processing. For example, the embodiments of the invention can be used to improve the receive (RX) sensitivities of an audio system and a CMOS direct conversion receiver in the Global System for Mobile Communications (GSM).
Unlike the CMOS amplifier 100 illustrated in
The output unit 140 includes a first transistor MN1, a second transistor MN2, a third transistor MN3, a resistor R, and a capacitor C. The source of the first transistor MN1 is connected to the drain terminal of the first CMOS amplifier 110, and the source of the second transistor MN2 is connected to the drain terminal of the second CMOS amplifier 120. The gates of the first and second transistors MN1 and MN2 are connected to the drain terminal of the second CMOS amplifier 120. The gate of the third transistor MN3 is connected to the drain terminal of the first CMOS amplifier 110, and the gate of the third transistor MN3 is connected to the output terminal Vo. The drains of the first, second and third transistors MN1, MN2 and MN3 are connected to a ground voltage VSS. Also, the resistor R and the capacitor C are connected in series between the output terminal Vo and the source of the second transistor MN2.
The output unit 140 outputs an output signal to the output terminal Vo in proportion to the currents flowing from the drain terminals of the first and second CMOS amplifiers 110 and 120. The resistor R and the capacitor C in the output unit 140 attenuate a high-frequency component (e.g., a glitch) contained in the output signal. A normal input signal is applied to a first input terminal Vip, and an inverted input signal of the normal input signal is applied to a second input terminal Vin.
Thus, as described above with respect to
As illustrated by
The differential amplifier 200 may also include an output circuit 140, which is electrically coupled to the shared first drain terminals and the shared second drain terminals, and a current mirror circuit 130, which is electrically coupled to the shared first source terminals and the shared second source terminals.
In the drawings and specification, there have been disclosed typical preferred embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.
Number | Date | Country | Kind |
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2007-90613 | Jun 2007 | KR | national |