J. S. Hiltebeitel, CMOS XOR, IBM Technical Disclosure Bulletin, V. 27, #4B Sep. 1984, p. 2639. |
M. R. Ouellette, et al, Fast Carry Sum Adder, IBM Technical Disclosure Bulletin, V. 30, #5, Oct. 1987, pp. 323-324. |
K. Yano, et al., A 3.8-ns CMOS 16.times.16-b Multiplier Using Complementary Pass-Transistor Logic, IEEE, 1990. |
C. Heikes, A 4.5mm2 Multiplier Array For A 200MFlop Pipelined Coprocessor, Digest of Technical Papers, High-Performance Logic Circuit Techniques, Paper FA 18.1, Session 18, ISSCC94, pp. 290-291. |
H. Partovi, et al., A Regenerative Push-Pull Differential Logic Family, IEEE International Solid-State Circuits Conference, Digest of Technical Papers, High-Performance Logic Circuit Techniques, FA 18.3, Session 18, ISSCC94, pp. 294-295. |