Patent Grant
9135871
This application claims the benefit of priority based on Japanese Patent Application No. 2008-140179, filed on May 28, 2008, the disclosure of which is incorporated herein by reference.
1. Field of the Invention
The present invention relates to a display device, a display panel driver, a method for driving a display panel, and a method for supplying image data to the driver, and more specifically, to overdriving of the display panel.
2. Description of the Related Art
The overdriving is one approach for improving the response speed of liquid crystal material within a liquid crystal display panel. The overdriving is a technique for improving the response speed of a liquid crystal display panel by driving liquid crystal material with a drive voltage higher than a normal drive voltage for positive drive voltage or with a drive voltage lower than a normal drive voltage for negative drive voltage, when there is a large change in the grayscale level.
Such overdriving is often used in large-sized liquid crystal display devices, for example, a liquid crystal television and a liquid-crystal monitor for a computer, which are required to display high-quality video images. For example, Japanese Open Laid Patent Application No. H04-365094 discloses a liquid crystal television that adopts the overdriving.
In recent years, a demand for displaying moving images is increasing also in the portable terminals; video and TV functions are provided for portable terminals. Therefore, it is one prevalent choice to apply the overdriving to liquid crystal display devices of the portable terminals.
According to inventors' examination, however, the use of conventional overdriving may cause a problem in terms of power consumption, especially in portable devices which require low power consumption. In the conventional overdriving, overdrive processing is performed in every frame period, which involves: writing image data into the image memory 111 for storing the image data of the previous frame; reading the image data of the previous frame from the image memory 111 in order to compare it with the image data of a current frame; determining the degree of overdrive from the data stored in the ROM 112; and outputting the resultant drive data. Performing such overdrive processing in every frame period undesirably increases power consumption.
The inventors have discovered that it is not necessary to perform overdrive processing in every frame period, when driving a liquid crystal display panel with an LCD panel driver which incorporates a display memory for storing image data of a previous frame image. It is not necessary to perform overdrive processing, when image data stored in the display memory are not updated; the image is unchanged in this case. It is possible to reduce power consumption by skipping overdrive processing when the image data in the display memory are unchanged.
More specifically, in an aspect of the present invention, a display device is provided with a display panel, and a display panel driver driving the display panel in response to externally-provided image data. The display panel driver is provided with a display memory for storing the externally-provided image data, and configured to perform overdrive processing on the image data read from the display memory. The display panel driver includes an overdrive processing control circuit which detects whether or not image data are written onto the display memory, to allow or prohibit the operation of a circuitry used for the overdrive processing.
The present invention effectively reduces the power consumption necessary for performing overdrive processing.
The above and other objects, advantages and features of the present invention will be more apparent from the following description of certain preferred embodiments taken in conjunction with the accompanying drawings, in which:
The invention will be now described herein with reference to illustrative embodiments. Those skilled in the art will recognize that many alternative embodiments can be accomplished using the teachings of the present invention and that the invention is not limited to the embodiments illustrated for explanatory purposes.
The liquid crystal display panel 2 is provided with a display section 11 and a gate line driver circuit 12 formed by using a SOG (silicon on glass) technique. The display section 11 includes H data lines, V gate lines, and liquid crystal pixels arranged at the intersections of the data lines and gate lines. In this embodiment, the number of the liquid crystal pixels provided in the display section 11 is H×V. The gate line driver circuit 12 has a function of driving the V gate lines provided in the display section 11.
The LCD driver 3 drives the data lines within the display section 11 of the liquid crystal display panel 2 in response to the image data Din fed from the image processing device 4. The LCD driver 3 further generates gate line drive timing control signals 5 to control operation timings of the gate line driver circuit 12.
The image processing device 4 supplies to the LCD driver 3 the image data Din and memory control signals 6 for controlling the LCD driver 3. The memory control signals 6 include a write clock WR generated in synchronization with the transfer of the image data Din. The write clock WR is used for writing the image data Din into a display memory incorporated within the LCD driver 3, as will be described later. Timings at which the image processing device 4 supplies the image data Din and the write clock WR to the LCD driver 3 are in synchronization with a display frame timing signal Vsync supplied to the image processing device 4 from the LCD driver 3. That is, the image processing device 4 recognizes from the display frame timing signal Vsync the timings at which the image data Din and the write clock WR are to supplied, and supplies the image data Din and the write clock WR to the LCD driver 3 accordingly. A CPU (central processing unit) or a DSP (digital signal processor) may be used as the image processing device 4, for example.
The LCD driver 3 is provided with a memory control circuit 21, a display memory 22, an overdrive memory (OD memory) 23, an overdrive processing circuit 24, a latch circuit 25, a data line driver circuit 26, a grayscale voltage generator circuit 27, and a timing control circuit 28.
The memory control circuit 21 operates as follows: First, the memory control circuit 21 receives the image data Din from the image processing device 4 and transfers the received image data Din to the display memory 22. Second, the memory control circuit 21 is responsive to a timing control signal 35 received from the timing control circuit 28 for supplying display memory control signals 31 to the display memory 22 and for supplying overdrive memory control signals 32 to the overdrive memory 23. The display memory control signals 31 include the above-mentioned write clock WR and a read clock LCD_READ. The write clock WR is used for writing the image data Din into the display memory 22, and the read clock LCD_READ is used for reading the image data from the display memory 22. The frequency of the read clock LCD_READ is adjusted so that the image may be displayed on the display section 11 at a desired frame rate (typically, 60 Hz). On the other hand, the overdrive memory control signals 32 include the read clock LCD_READ. The write and read operations of the overdrive memory 23 are performed in synchronization with the read clock LCD_READ. Third, the memory control circuit 21 supplies the above-mentioned display frame timing signal Vsync to the image processing device 4. As described above, the display frame timing signal Vsync is used in order to determine the timings at which the image processing device 4 starts to supply the image data Din and the write clock WR.
The display memory 22 receives and stores the image data Din therein. Image data Dmem read from the display memory 22 are used for image display in the current frame. In this embodiment, the image data Din are k-bit data, and the display memory 22 has a capacity enough to store the image data for the H×V liquid crystal pixels, i.e., a capacity of H×V×k bits.
In this embodiment, a dual port memory is used as the display memory 22, and writing of the image data Din into the display memory 22 and reading of the image data Dmem from the display memory 22 are performed asynchronously. In detail, the writing of the image data Din into the display memory 22 is performed in synchronization with the write clock WR. The write clock WR is supplied to the LCD driver 3 only during a period in which the image data Din are written into the display memory 22. On the other hand, the reading of the image data Dmem from the display memory 22 is performed in synchronization with the read clock LCD_READ. Such a function is effective in improving flexibility of transfer of the image data Din to the display memory 22. For example, the configuration in which the writing and the reading are asynchronously performed allows omitting the transfer of the image data Din to the display memory 22, when there is no change in the image to be displayed. Moreover, in the case where only a part of the image is changed, such configuration allows selectively transferring only the part of the image data Din corresponding to the changed part to the display memory 22 with the write address of the display memory 22 specified.
Referring back to
The overdrive processing circuit 24 has a function of performing overdrive processing in response to the previous frame image data Dn−1 (namely, the correction processing of the image data Dmem for achieving the overdriving) on the image data Dmem read from the display memory 22 to generate resultant image data Dout. The resultant image data Dout are transferred to the latch circuit 25. In addition, the overdrive processing circuit 24 transfers upper z bits of the image data Dmem (the image data used for the image display on the display section 11) received from the display memory 22 to the overdrive memory 23, and stores the upper z bits of the image data Dmem into the overdrive memory 23.
The latch circuit 25 is responsive to a latch signal 34 received from the timing control circuit 28 for latching the resultant image data Dout from the overdrive processing circuit 24 to transfer the resultant image data Dout to the data line driver circuit 26. The latch circuit 25 has a capacity for storing the resultant image data Dout associated with H pixels of one horizontal line, i.e., a capacity of H×k bits.
The data line driver circuit 26 drives data lines of the display section 11 of the liquid crystal display panel 2 in response to the resultant image data Dout of the selected horizontal line received from the latch circuit 25. More specifically, the data line driver circuit 26 selects a grayscale voltage from a plurality of grayscale voltages V1 to VN fed from the grayscale voltage generator circuit 27 for each data line in response to the resultant image data Dout, and drives each data line of the display section 11 to the selected grayscale voltage. In this embodiment, the number of grayscale voltages supplied from the grayscale voltage generator circuit 27 is 2k.
The timing control circuit 28 provides a timing control for the whole of the LCD driver 3. In detail, the timing control circuit 28 generates the latch signal 34, the timing control signal 35, and the gate line driving timing control signal 5, and supplies these signals to the latch circuit 25, the memory control circuit 21, and the gate line driver circuit 12, respectively.
One feature of the liquid crystal display device 1 of this embodiment is that the liquid crystal display device 1 is configured to automatically perform execution and halt of the overdrive processing depending on whether or not the image data Din are transferred from the image processing device 4 to the LCD driver 3. This effectively reduces power consumption. In the case where the image data Din are not transferred from the image processing device 4 to the LCD driver 3, the image being displayed does not experience a change, and the overdrive processing is not essentially necessary. In such a case, the liquid crystal display device 1 of this embodiment halts the write and read operations into and from the overdrive memory 23 and thereby reduces power consumption, effectively.
More specifically, the LCD driver 3 of this embodiment is provided with an overdrive processing control circuit 29 that generates an overdrive processing select signal 33 to control the execution and halt of the overdrive processing. In this embodiment, the write clock WR is additionally supplied to the overdrive processing control circuit 29, and the overdrive processing control circuit 29 discriminates the existence or absence of the transfer of the image data Din from the write clock WR. According to the result of the discrimination, the overdrive processing control circuit 29 asserts the overdrive processing select signal 33 to permit the execution of the overdrive processing if necessary. The overdrive processing select signal 33 is fed to the overdrive memory 23 and the overdrive processing circuit 24.
When the overdrive processing select signal 33 is asserted, the overdrive processing is performed. That is, the image data Dn received from the display memory 22 are written into the overdrive memory 23 while the previous frame image data Dn−1 are read from the overdrive memory 23, and the overdrive processing circuit 24 performs the overdrive processing using the previous frame image data Dn−1.
When the overdrive processing select signal 33 is negated, on the other hand, the overdrive processing is halted. That is, the write and read operations into and from the overdrive memory 23 are halted: the overdrive processing circuit 24 outputs the image data Dmem received from the display memory 22 as they are, as the resultant image data Dout without performing the overdrive processing. The halt of the write and read operations into and from the overdrive memory 23 may be achieved by, for example, halting supply of the read clock LCD_READ to the overdrive memory 23. In order to prevent malfunction, it is preferable to halt the supply of the address signals and to negate the write enable signal and the read enable signal, in addition to the halt of the supply of the read clock LCD_READ.
When the overdrive processing select signal 33 is asserted, the switches 42 and 43 are turned on, and the selection circuit 44 selects the output image data Dout′ as the resultant image data Dout. This allows performing the overdrive processing, and writing upper z bits of the image data Dmem of the current frame image into the overdrive memory 23 as the image data Dn. When the overdrive processing select signal 33 is negated, on the other hand, the switches 42 and 43 are turned off and the selection circuit 44 selects the image data Dmem as the resultant image data Dout. This allows halting the overdrive processing.
One issue in controlling the execution and halt of the overdrive processing is the selection of the frame period in which the overdrive processing is to be performed when the image data Din are transferred to the LCD driver 3. In the case where the image data Din are transferred in a certain frame period and the transferred image data Din are used for the image display in the same frame period, the overdrive processing is to be performed in the frame period in which the relevant image data Din are transferred; if not so, the response speed of liquid crystal material is not improved according to the change of the grayscale level. On the other hand, in the case where the image data Din are transferred in a certain frame period and the transferred image data Din are used for the image display in the frame period following the certain frame period, the overdrive processing is to be performed in the next frame period; if not so, the overdrive processing is performed on the image data which is being updated, and an improper image may be displayed.
In this embodiment, the overdrive processing control circuit 29 is configured to properly determine the frame period in which the overdrive processing should be performed, from the relation between the timing at which the transfer of the image data Din is started and the timing at which reading of the image data Dmem from the display memory 22 is started. The overdrive processing control circuit 29 recognizes the timing at which the transfer of the image data Din is started by the timing at which the supply of the write clock WR is started, and recognizes the timing at which the reading of the image data Dmem from the display memory 22 is started by the timing at which the supply of the read clock LCD_READ is started. When the timing at which the transfer of the image data Din is started is ahead of the timing at which the reading of the image data Dmem from the display memory 22 is started in a specific frame period, the image data Din transferred in the frame period is used for the image display in the specific frame period. In this case, the overdrive processing control circuit 29 permits the overdrive processing in the specific frame period. On the other hand, when the timing at which the transfer of the image data Din is started is behind the timing at which the reading of the image data Dmem from the display memory 22 is started in a certain frame period, the transferred image data Din are used for the image display in the frame period following the specific frame period. In this case, the overdrive processing control circuit 29 permits the overdrive processing in the following frame period.
More specifically, the overdrive processing control circuit 29 performs the following processes, using a CPU write flag as an internal variable in this embodiment:
The above-described procedure allows appropriately determining the frame period in which the overdrive processing is to be performed. In the following, a detailed description is given of an exemplary procedure for determining the frame period in which the overdrive processing is to be performed.
The image processing device 4 monitors the display frame timing signal Vsync, and transfers the image data Din so that the read address of the image data Dmem in the display memory 22 does not overtake the write address of the image data Din. In detail, in the i-th frame period, the image processing device 4 starts the transfer of the image data Din and the supply of the write clock WR in synchronization with the transfer, at a timing before the supply of the read clock LCD_READ is started. The frequency of the write clock WR is adjusted higher than the frequency of the read clock LCD_READ and this prevents the read address of the image data Dmem from overtaking the write address of the image data Din. It should be noted, however, the frequency of the write clock WR is not necessarily required to be higher than the frequency of the read clock LCD_READ, in the case where the image data Din corresponding to only a part of the image are transferred.
When the supply of the write clock WR is started, the CPU write flag is asserted. Subsequently, the supply of the read clock LCD_READ is started and the reading of the image data Dmem from the display memory 22 is started. When the supply of the read clock LCD_READ is started in the state where the CPU write flag is asserted, the overdrive processing select signal 33 is asserted and the execution of the overdrive processing is permitted. When the predetermined period elapses after the overdrive processing select signal 33 is asserted, the CPU write flag is negated. Subsequently, the overdrive processing select signal 33 is negated when the supply of the read clock LCD_READ is halted. In such an operation, the overdrive processing is performed in the i-th frame period, when the transfer of the image data Din is performed in the i-th frame period.
On the other hand, the overdrive processing is not performed in the frame period in which the transfer of the image data Din to the display memory 22 is not performed. That is, neither the write operation nor the read operation to the overdrive memory 23 is performed. This effectively reduces the power consumption.
In each frame period, the supply of the read clock LCD_READ is started at the predetermined timing after the display frame timing signal Vsync is asserted, and the reading of the image data Dmem from the display memory 22 is started. At this time, the overdrive processing select signal 33 remains negated, since the CPU write flag is not asserted at the timing of the start of the supply of the read clock LCD_READ of the i-th frame period. That is, the overdrive processing is not performed in the i-th frame period.
The image processing device 4 monitors the display frame timing signal Vsync, and transfers the image data Din so that the write address of the image data Din does not overtake the read address of the image data Dmem in the display memory 22. It should be noted that the relation of the write address and the read address in the operation of
In detail, the image processing device 4 starts the transfer of the image data Din and the supply of the write clock WR in synchronization with the transfer of the image data Din in the i-th frame period, at a timing after the supply of the read clock LCD_READ is started. The frequency of the write clock WR is set lower than the frequency of the read clock LCD_READ and this prevents the write address of the image data Din from overtaking the read address of the image data Dmem. It should be noted, however, the frequency of the read clock LCD_READ is not necessarily required to be lower than the frequency of the write clock WR in the case where the image data Din associated with only a part of the image is transferred. When the supply of the write clock WR is started, the CPU write flag is asserted.
In the following (i+1)-th frame period, when the supply of the read clock LCD_READ is started, the overdrive processing select signal 33 is asserted to permit the execution of the overdrive processing in response to the CPU write flag being asserted. When the predetermined period elapses after the overdrive processing select signal 33 is asserted, the CPU write flag is negated. Subsequently, the overdrive processing select signal 33 is negated, when the supply of the read clock LCD_READ is halted. In such the operation, the overdrive processing is performed in the (i+1)th frame period, when the transfer of the image data Din is started in the i-th frame period. Therefore, the overdrive processing is performed after a complete set of the image data is prepared on the display memory 22, and this effectively avoids an improper image being displayed.
In the frame period in which the transfer of the image data Din to the display memory 22 is not performed, the overdrive processing is not performed. That is, neither the write operation nor the read operation to the overdrive memory 23 is performed, and this effectively reduces power consumption.
As thus described, the operation of the overdrive processing control circuit 29 of this embodiment allows automatically identifying the transfer of the image data Din shown in
Such operation is preferable, especially when the timing relation is adjustable between the timing at which the transfer of the image data Din to the display memory 22 is started (namely, the timing at which the supply of the write clock WR is started) and the timing at which the reading of the image data Dmem from the display memory 22 is started (namely, the timing at which the supply of the read clock LCD_READ is started). In one embodiment, the timing relation may be adjusted in response to the amount of the image data Din to be transferred. For example, when the quantity of the image data Din to be transferred is smaller than a predetermined value, the image processing device 4 adjusts the timing at which the transfer of the image data Din to the display memory 22 is started to precede the timing at which the reading of the image data Dmem from the display memory 22 is started. In this case, the image display in accordance with the transferred image data Din is performed in the same frame period as the frame period in which the transfer of the image data Din is started, while the overdrive processing is performed in the same frame period. When the quantity of the image data Din that should be transferred is larger than a specified value, on the other hand, the image processing device 4 adjusts the timing at which the transfer of the image data Din to the display memory 22 is started to come after the timing at which the reading of the image data Dmem from the display memory 22 is started. The image display in accordance with the image data Din transferred is performed in the frame period following the frame period in which the transfer of the image data Din is started, while the overdrive processing is performed in the following frame period.
Although various embodiments of the present invention are described above, the present invention should not be interpreted as being limited to the embodiments described above. The present invention may be modified and implemented in various forms. Especially, although embodiments in which the present invention is applied to a liquid crystal display device are presented above, it would be obvious to those skilled in the art that the present invention is applicable to other display devices that perform the overdrive processing, for example, electronic paper (especially, electronic paper using electro-liquid powder).
| Number | Date | Country | Kind |
|---|---|---|---|
| 2008-140179 | May 2008 | JP | national |
This application is a Continuation Application of U.S. patent application Ser. No. 12/453,930, filed May 27, 2009, now U.S. Pat. No. 8,279,230.
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| Number | Date | Country | |
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| Number | Date | Country | |
|---|---|---|---|
| Parent | 12453930 | May 2009 | US |
| Child | 13566518 | US |
