Patent Application
20240403535
This application is related to integrated circuits and more particularly to electronic design automation for integrated circuits.
A typical integrated circuit includes one or more intellectual property (IP) designs created by one or more vendors. For example, a fabless semiconductor company designs an integrated circuit product using a circuit designed in-house and at least one circuit designed by an IP vendor that satisfies specifications provided by or approved by the fabless semiconductor company. The IP vendor completes verification for manufacturability of the design before providing a corresponding circuit layout database to a semiconductor foundry for manufacturing. However, to protect their intellectual property from theft, the IP vendor may not provide the corresponding circuit layout database to the fabless semiconductor company. Instead, the IP vendor provides only one or more models of the IP design to the fabless semiconductor company. While those models are useful for simulation of functionality and timing, a physical view is omitted. As a result, the fabless semiconductor company has an incomplete view of the integrated circuit product at the borders of the IP design in a physical layout view of the integrated circuit product used for verification for manufacturability. Density gradient violations are likely to take place between the borders of the IP design and other circuits adjacent to the IP design. Density gradient violations may be detected by the semiconductor foundry after tapeout when the semiconductor foundry merges and verifies a merged design including the circuit layout received from the IP vendor and the layout for the circuits designed by the fabless semiconductor company. Addressing any density gradient violations typically delays a project timeline. Accordingly, improved techniques for generating an integrated circuit design are desired.
In at least one embodiment, a method for manufacturing an integrated circuit includes generating a design density view database representing a first integrated circuit layout design by using layer density information associated with the first integrated circuit layout design as a proxy for actual layout design information. The generating may include, for each layer and each density window of a design density database including the layer density information associated with the first integrated circuit layout design: extracting a density value for the layer in the density window, calculating layer material area in the density window based on the density value, and placing a number of geometric shapes of predetermined unit size with predetermined spacing in the density window corresponding to the layer material area and density value.
In at least one embodiment, a computer-aided design system includes a design density database including a plurality of density windows for each layer of a plurality of layers associated with a first integrated circuit layout design. The computer-aided design system includes a processor configured to generate a design density view database for the first integrated circuit layout design based on the design density database. The design density view database uses layer density information as a proxy for actual layout design information for the first integrated circuit layout design. For each layer and for each density window of the plurality of density windows, the processor may be configured to extract a density value for the layer in the density window, calculate layer material area in the density window, and place a number of geometric shapes of predetermined unit size with predetermined spacing in the density window corresponding to the layer material area and density value.
In at least one embodiment, a method for manufacturing an integrated circuit includes providing a design density database associated with a first integrated circuit layout design. The method includes providing a full design view database associated with the first integrated circuit layout design. In an embodiment, the method includes generating a layout design database based on a design density view database associated with the first integrated circuit layout design and a second integrated circuit layout design. The layout design database may include a phantom design corresponding to the first integrated circuit layout design. The design density view database may represent the first integrated circuit layout design using layer density information associated with the first integrated circuit layout design as a proxy for actual layout design information. The method may include generating the integrated circuit using the full design view database and the layout design database.
The present invention may be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings.
The use of the same reference symbols in different drawings indicates similar or identical items.
Referring to
Although the layout design database for integrated circuit design 102 including the phantom design passes one or more design rule checks executed by the second party using Electronic Design Automation (EDA) tools, when the semiconductor foundry replaces the phantom design with the layout design database for integrated circuit portion 106, the layout design database for integrated circuit design 102 may no longer pass the one or more design rule checks. Accordingly, the semiconductor foundry delays the manufacture of integrated circuit design 102 until the semiconductor foundry, second party, or IP vendor addresses the failure (e.g., by redesigning integrated circuit portion 104, integrated circuit portion 106, or other portion of integrated circuit design 102). Any delay in manufacture can delay the time to market of a product, increase costs or result in lost revenue for the second party.
Referring to
CAD and PG 290 runs a density deck on a full IP layout design represented by IP design database 204 (206). That is, the IP vendor runs a script or other software that uses IP design database 204 and density deck 202. In at least one embodiment of CAD and PG 290, the IP vendor receives density deck 202 from the fabless semiconductor manufacturer. However, in other embodiments, the IP vendor receives density deck 202 from an EDA vendor, a semiconductor foundry, or other party. In at least one embodiment, density deck 202 includes instructions for calculating the density of portions of the full IP layout design. In at least one embodiment, the script partitions each layer of IP design database 204 into a grid of density windows and determines the density of material in each window of the layer. For example, the script generates IP density results database 208 by determining, for each layer of the IP layout design, the area of the layer material in each tile of a grid and divides by the area of the tile. The IP vendor provides IP density results database 210, which is a copy of IP density results database 208, to the fabless semiconductor manufacturer for use during CAD 292. In at least one embodiment, IP density results database 208 and IP density results database 210 include text descriptions of tiles used to calculate the density along with corresponding density values.
During CAD 292, the fabless semiconductor manufacturer uses IP density results database 210 to generate IP density view database 220. As referred to herein, a density view includes an imitation of design, i.e., includes density information without other physical layout information. The density view provides density information as a proxy for actual layout design information (i.e., conventional physical view information). In at least one embodiment, a script executing on a processor partitions each layer of an integrated circuit layout into a grid of density windows in the layer and performs loop 212 for each density window of each layer to generate IP density view database 220. In performing loop 212, the processor extracts a density value for the density window (214), calculates an area of layer material for the density window (216), and places within the density window a number of spaced unit rectangles (or other predetermined shape) representing layer material corresponding to the area of layer material (218). In at least one embodiment, shapes placed in IP density view database 220 obey manufacturing design rules to avoid design verification violations later.
In at least one embodiment, the fabless semiconductor manufacturer executes quality assurance analysis 224 (e.g., via a script or other software executing on one or more processors). In an embodiment, quality assurance analysis 224 runs density deck 202 on IP density view database 220 (226). In at least one embodiment, quality assurance analysis 224 partitions each layer of IP density view database 220 into a grid of density windows for the layer and measures the density of layer material represented in each density window of the layer. For example, quality assurance analysis 224 generates density view density results database 228 by determining the area of the layer material in each density window of a layer and divides by the area of the density window. Quality assurance analysis 224 compares (230) the density view density results database 228 to IP density results database 210 and provides an indication of the comparison. In at least one embodiment, quality assurance analysis 224 generates analytics based on the comparison. For example, representation scores 232 indicate any error in density between IP density results database 210 and density view density results database 228. In at least one embodiment, the final representation score is 99%, i.e., 99% of layer material in IP density results database 210 is represented in IP density view database 220.
Referring to
Referring back to
In at least one embodiment, CAD 292 and PG 294 are implemented using corresponding CAD and PG scripts or other software stored in memory and executing on one or more processors that call APIs of CAD software and PG software, respectively, to generate IP density view database 220 and final database 248, respectively. The semiconductor foundry will verify manufacturability of the design represented by final database 248 and may make modifications to final database 248 before generating photolithography masks. Those modifications may include inserting custom structures to further improve manufacturability of the layout, generating a reticle layout with test patterns and alignment marks, layout-to-mask preparation, or other modifications in preparation for manufacturing.
In at least one embodiment, the density window size (e.g., 40 μm×40 μm) used by loop 212 is the same size as a window size used in uniformity checks or other DRC of PG 294. In at least one embodiment, IP density view database 220 is generated using shapes of another predetermined size (e.g., 500 nm×500 nm) and densities are compared by quality assurance analysis 224 using windows of yet another predetermined size (e.g., 200 μm×200 μm). However, other embodiments use different relationships between window sizes and shape sizes or different window sizes or different shape sizes. In at least one embodiment, the error in density between IP density results database 210 and IP density view database 220 is less than 1%.
Thus, techniques for providing a realistic representation of density of layer material in an IP design without revealing actual layout design data to protect an IP vendor's proprietary data are described. The realistic representation of the densities of layer material reduces or eliminates density violations on the borders of the IP design. By exchanging standardized data in an IP density view database, the techniques described herein can be independent of the IP vendor. The techniques reduce redesign, thus reducing development time and cost of manufacturing an integrated circuit including an IP block. The technique allows an IP vendor to protect their IP and maintain control of the layout design by disclosing the actual layout design directly to a semiconductor foundry without disclosing the actual layout design to a fabless semiconductor manufacturer.
The description of the invention set forth herein is illustrative and is not intended to limit the scope of the invention as set forth in the following claims. The terms “first,” “second,” “third,” and so forth, as used in the claims, unless otherwise clear by context, is to distinguish between different items in the claims and does not otherwise indicate or imply any order in time, location, or quality. For example, “a first received database,” “a second received database,” does not indicate or imply that the first received database occurs in time before the second received database. Software, as described herein, may be encoded in at least one tangible (i.e., non-transitory) computer readable medium. As referred to herein, a tangible computer-readable medium includes at least a disk, tape, or other magnetic, optical, or electronic storage medium. Persons of ordinary skill in the art will recognize a variety of design tools and languages appropriate for implementing the teachings described herein. Variations and modifications of the embodiments disclosed herein may be made based on the description set forth herein, without departing from the scope of the invention as set forth in the following claims.
