INTEGRATED CIRCUIT DEVICE AND CHIP DEVICE

Abstract

An integrated circuit device includes a reference voltage channel, a first cell and a second cell. The reference voltage channel is configured to provide a first reference voltage and a second reference voltage. The first cell is coupled to the reference voltage channel, and is configured to receive the first reference voltage and the second reference voltage. The second cell is coupled to the reference voltage channel, and is configured to receive the first reference voltage and the second reference voltage.

Description

BACKGROUND

Technology Field

The disclosure relates to an integrated circuit, and, in particular, to an integrated circuit device and a chip device for decreasing area and power consumption.

Description of the Related Art

Generally, an integrated circuit may include a plurality of components. However, each of the components may use an independent power source, or the selecting signal of an independent selecting module, increasing the area and power consumption of the integrated circuit. Therefore, how to decrease the area and power consumption of the integrated circuit has become an important issue.

SUMMARY

The disclosure provides an integrated circuit device and a chip device, thereby decreasing the area and power consumption of the integrated circuit device.

An embodiment of the disclosure provides an integrated circuit device, which includes a reference voltage channel, a first cell and a second cell. The reference voltage channel is configured to provide a first reference voltage and a second reference voltage. The first cell is coupled to the reference voltage channel, and is configured to receive the first reference voltage and the second reference voltage. The second cell is coupled to the reference voltage channel, and is configured to receive the first reference voltage and the second reference voltage.

An embodiment of the disclosure provides a chip device, which includes at least one above integrated circuit device.

An embodiment of the disclosure provides an integrated circuit device, which includes a plurality of selecting modules and a selecting signal providing module. Each of the selecting modules is configured to receive a first input signal, a second input signal, a first selecting signal and a second selecting signal, and select the first input signal or the second input signal to generate an output signal according to a first selecting signal and a second selecting signal. The selecting signal providing module is configured to provide the first selecting signal and the second selecting signal.

According to the integrated circuit device and the chip device disclosed by the present disclosure, the first cell and the second cell share the same reference voltage channel or the selecting module share the same selecting signal providing module. Therefore, the area and power consumption of the integrated circuit device may be effectively decreased.

BRIEF DESCRIPTION OF THE DRAWINGS

The disclosure can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:

FIG. 1 is a schematic view of an integrated circuit device according to an embodiment of the disclosure;

FIG. 2 is a schematic view of an integrated circuit device according to another embodiment of the disclosure;

FIG. 3 is a schematic view of an integrated circuit device according to another embodiment of the disclosure;

FIG. 4 is a schematic view of a layout of a chip device according to an embodiment of the disclosure;

FIG. 5 is a schematic view of an integrated circuit device according to an embodiment of the disclosure;

FIG. 6 is a circuit diagram of a selecting module in FIG. 5; and

FIG. 7 is a circuit diagram of a selecting module in FIG. 5.

DETAILED DESCRIPTION OF THE DISCLOSURE

Technical terms of the present disclosure are based on general definition in the technical field of the present disclosure. If the present disclosure describes or explains one or some terms, definition of the terms is based on the description or explanation of the present disclosure. Each of the disclosed embodiments has one or more technical features. In possible implementation, a person skilled in the art would selectively implement all or some technical features of any embodiment of the present disclosure or selectively combine all or some technical features of the embodiments of the present disclosure.

In each of the following embodiments, the same reference number represents the same or a similar element or component.

FIG. 1 is a schematic view of an integrated circuit device according to an embodiment of the disclosure. Please refer to FIG. 1. The integrated circuit device 100 includes a reference voltage channel 110, a first cell 120 and a second cell 130.

The reference voltage channel 110 is configured to provide a first reference voltage VDD and a second reference voltage VSS. In the embodiment, the first reference voltage VDD is, for example, a system voltage, and the second reference voltage VSS is, for example, a ground voltage, but the disclosure is not limited thereto.

The first cell 120 is coupled to the reference voltage channel 110, and is configured to receive the first reference voltage VDD and the second reference voltage VSS. In addition, the first cell 120 is disposed on a first side 111 of the reference voltage channel 110.

The second cell 130 is coupled to the reference voltage channel 110, and is configured to receive the first reference voltage VDD and the second reference voltage VSS. In addition, the second cell 130 is disposed on a second side 112 of the reference voltage channel 110. The second side 112 is opposite to the first side 111. That is, the first cell 120 and the second cell 130 are disposed at two opposite sides of the reference voltage channel 110. Therefore, the first cell 120 and the second cell 130 may share the same reference voltage channel 110, the first cell 120 and the second cell 130 may share the same first reference voltage VDD and the same second reference voltage VSS, so as to effectively decrease the area and power consumption of the integrated circuit device 100.

In some embodiments, each of the first cell 120 and the second cell 130 may include a plurality of transistors. In addition, the transistors may at least include an N-type transistor TN and a P-type transistor TP, but the disclosure is not limited thereto. In other embodiments, the transistors may also a plurality of N-type transistors TN and a plurality of P-type transistors TP.

In the embodiment, the number of transistors of the first cell 120 is, for example, equal to the number of transistors of the second cell 130. That is, the area of the first cell 120 is equal to the area the second cell 130.

In some embodiments, the number of transistors of the first cell 120 is, for example, less than the number of transistors of the second cell 130, as shown in FIG. 2. That is, the area of the first cell 120 is less than the area of the second cell 130.

In some embodiments, the number of transistors of the first cell 120 is, for example, greater than the number of transistors of the second cell 130, as shown in FIG. 3. That is, the area of the first cell 120 is greater than the area of the second cell 130.

In some embodiments, the first cell 120 may at least include an input terminal 121 and an output terminal 122. The input terminal 121 is configured to receive an input signal. The output terminal 122 is configured to output an output signal. In other embodiments, the first cell 120 may include a plurality of input terminals 121 and a plurality of output terminals 122. In addition, the number of input terminals 121 and the number of output terminals 122 may be the same or different.

In addition, the second cell 130 may at least include an input terminal 131 and an output terminal 132. The input terminal 131 is configured to receive an input signal. The output terminal 132 is configured to output an output signal. In other embodiments, the second cell 130 may include a plurality of input terminals 131 and a plurality of output terminals 132. In addition, the number of input terminals 131 and the number of output terminals 132 may be the same or different.

FIG. 4 is a schematic view of a layout of a chip device according to an embodiment of the disclosure. Please refer to FIG. 4. The chip device 400 may include at least one integrated circuit device 100 in FIG. 1, FIG. 2 and/or FIG. 3. Therefore, the chip device 400 may also achieve the same effect for decreasing area and power consumption. In FIG. 4, the chip device 400 includes three integrated circuits 100, but the disclosure is not limited thereto. In some embodiment, the chip device 400 may also include two or more than three integrated circuits 100. In addition, the disposing position of the integrated circuits 100 in FIG. 4 is one exemplary embodiment of the disclosure, but the disclosure is not limited thereto. The user may adjust the disposing position of the integrated circuits 100 according to the requirements thereof. Therefore, the same effect may also be achieved.

FIG. 5 is a schematic view of an integrated circuit device according to an embodiment of the disclosure. Please refer to FIG. 5. The integrated circuit device 500 includes a plurality of selecting modules 510_1˜510_N and a selecting signal providing module 520, wherein N is a positive integer greater than 1.

Each of the selecting modules 510_1˜510_N is configured to receive a first input signal IN1_1˜IN1_N, a second input signal IN2_1˜IN2_N, a first selecting signal S1 and a second selecting signal S2, and select the first input signal IN1_1˜IN1_N or the second input signal IN2_1˜IN2_N to generate an output signal OUT_1˜OUT_N according to a first selecting signal S1 and a second selecting signal S2. For example, the selecting modules 510_1 receives the first input signal IN1_1, the second input signal IN2_1, the first selecting signal S1 and the second selecting signal S2, and selects the first input signal IN1_1 or the second input signal IN2_1 to generate the output signal OUT_1 according to the first selecting signal S1 and the second selecting signal S2.

The selecting modules 510_2 receives the first input signal IN1_2, the second input signal IN2_2, the first selecting signal S1 and the second selecting signal S2, and selects the first input signal IN1_2 or the second input signal IN2_2 to generate the output signal OUT_2 according to the first selecting signal S1 and the second selecting signal S2. . . . The selecting modules 510_N receives the first input signal IN1_N, the second input signal IN2_N, the first selecting signal S1 and the second selecting signal S2, and selects the first input signal IN1_N or the second input signal IN2_N to generate the output signal OUT_N according to the first selecting signal S1 and the second selecting signal S2. In the embodiments, each of the selecting modules 510_1˜510_N may include, for example, a multiplexer (MUX).

The selecting signal providing module 520 is coupled to the selecting module 510_1˜510_N. The selecting signal providing module 520 is configured to provide the first selecting signal S1 and the second selecting signal S2.

In the embodiment, the first selecting signal S1 and the second selecting signal S2 are inverted. In addition, the selecting signal providing module 520 may include an inverter 521. The inverter 521 has an input terminal and an output terminal. The input terminal of the inverter 521 receives the first selecting signal S1, and the output terminal of the inverter 521 outputs the second selecting signal S2. Therefore, the selecting modules 510_˜510_N may share the same selecting signal providing module 520, i.e., the selecting modules 510_1˜510_N may share the same first selecting signal Si and the same second selecting signal S2, so as to decrease the area and power consumption of the integrated circuit device 500.

In some embodiments, the selecting module 510_1 may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9 and a tenth transistor T10, as shown in FIG. 6. The internal components and the connection relationship thereof of selecting modules 510_2˜510_N are the same as the internal components and the connection relationship thereof of the selecting module 510_1. Accordingly, the selecting modules 510_2˜510_N may refer to the description of the embodiment in FIG. 6, and the description thereof is not repeated thereto.

The first transistor T1 has a first terminal, a second terminal and a control terminal. The first terminal of the first transistor T1 receives a first reference voltage VDD. The control terminal of the first transistor T1 receives the first input signal IN1_1. The second transistor T2 has a first terminal, a second terminal and a control terminal. The first terminal of the second transistor T2 receives a second reference voltage VSS. The second terminal of the second transistor T2 is coupled to the second terminal of the first transistor T1. The control terminal of the second transistor T2 is coupled to the control terminal of the first transistor T1. In the embodiments, the first reference voltage VDD is, for example, a system voltage, and the second reference voltage VSS is, for example, a ground voltage.

The third transistor T3 has a first terminal, a second terminal and a control terminal. The first terminal of the third transistor T3 receives the first reference voltage VDD. The control terminal of the third transistor T3 receives the second input signal IN2_1. The fourth transistor T4 has a first terminal, a second terminal and a control terminal. The first terminal of the fourth transistor T4 receives the second reference voltage VSS. The second terminal of the fourth transistor T4 is coupled to the second terminal of the third transistor T3. The control terminal of the fourth transistor T4 is coupled to the control terminal of the third transistor T3.

The fifth transistor T5 has a first terminal, a second terminal and a control terminal. The first terminal of the fifth transistor T5 is coupled to the second terminal of the first transistor T1. The control terminal of the fifth transistor T5 receives the first selecting signal S1. The sixth transistor T6 has a first terminal, a second terminal and a control terminal. The first terminal of the sixth transistor T6 is coupled to the second terminal of the fifth transistor T5. The second terminal of the sixth transistor T6 is coupled to the first terminal of the fifth transistor T5. The control terminal of the sixth transistor T6 receives the second selecting signal S2.

The seventh transistor T7 has a first terminal, a second terminal and a control terminal. The first terminal of the seventh transistor T7 is coupled to the second terminal of the third transistor T3. The control terminal of the seventh transistor T7 receives the second reference voltage S2. The eighth transistor T8 has a first terminal, a second terminal and a control terminal. The first terminal of the eighth transistor T8 is coupled to the second terminal of the seventh transistor T7. The second terminal of the eighth transistor T8 is coupled to the first terminal of the seventh transistor T7. The control terminal of the eighth transistor T8 receives the first selecting signal S1.

The ninth transistor T9 has a first terminal, a second terminal and a control terminal. The first terminal of the ninth transistor T9 receives the first reference voltage VDD. The second terminal of the ninth transistor T9 generates the first output signal OUT_1. The control terminal of the ninth transistor T9 is coupled to the second terminal of the fifth transistor T5 and the second terminal of the seventh transistor T7. The tenth transistor T10 has a first terminal, a second terminal and a control terminal. The first terminal of the tenth transistor T10 receives the second reference voltage VSS. The second terminal of the tenth transistor T10 is coupled to the second terminal of the ninth transistor T9. The control terminal of the tenth transistor T10 is coupled to the control terminal of the ninth transistor T9.

In some embodiments, each of the first transistor T1, the third transistor T3, the fifth transistor T5, the seventh transistor T7 and the ninth transistor T9 is, for example, a P-type transistor. Each of the first terminals of the first transistor T1, the third transistor T3, the fifth transistor T5, the seventh transistor T7 and the ninth transistor T9 is, for example, a source terminal of the P-type transistor. Each of the second terminals of the first transistor T1, the third transistor T3, the fifth transistor T5, the seventh transistor T7 and the ninth transistor T9 is, for example, a drain terminal of the P-type transistor. Each of the control terminals of the first transistor T1, the third transistor T3, the fifth transistor T5, the seventh transistor T7 and the ninth transistor T9 is, for example, a gate terminal of the P-type transistor.

In addition, each of the second transistor T2, the fourth transistor T4, the sixth transistor T6, the eighth transistor T8 and the tenth transistor T10 is, for example, an N-type transistor. Each of the first terminals of the second transistor T2, the fourth transistor T4, the sixth transistor T6, the eighth transistor T8 and the tenth transistor T10 is, for example, a source terminal of the N-type transistor. Each of the second terminals of the second transistor T2, the fourth transistor T4, the sixth transistor T6, the eighth transistor T8 and the tenth transistor T10 is, for example, a drain terminal of the N-type transistor. Each of the control terminals of the second transistor T2, the fourth transistor T4, the sixth transistor T6, the eighth transistor T8 and the tenth transistor T10 is, for example, a gate terminal of the P-type transistor.

In some embodiments, the selecting module 510_1 may include a first transistor T11, a second transistor T12, a third transistor T13, a fourth transistor T14, a fifth transistor T15, a sixth transistor T16, a seventh transistor T17, an eighth transistor T18, a ninth transistor T19 and a tenth transistor T20, as shown in FIG. 7. The internal components and the connection relationship thereof of selecting modules 510_2˜510_N are the same as the internal components and the connection relationship thereof of the selecting module 510_1. Accordingly, the selecting modules 510_2˜510_N may refer to the description of the embodiment in FIG. 6, and the description thereof is not repeated thereto.

The first transistor T11 has a first terminal, a second terminal and a control terminal. The first terminal of the first transistor T11 receives a first reference voltage VDD. The control terminal of the first transistor T11 receives the second selecting signal S2. The second transistor T12 has a first terminal, a second terminal and a control terminal. The first terminal of the second transistor T12 receives the first reference voltage VDD. The second terminal of the second transistor T12 is coupled to the second terminal of the first transistor T11. The control terminal of the second transistor T12 receives the first input signal IN1_1.

The third transistor T13 has a first terminal, a second terminal and a control terminal. The first terminal of the third transistor T13 is coupled to the second terminal of the first transistor T11. The control terminal of the third transistor T13 receives the first selecting signal S1. The fourth transistor T14 has a first terminal, a second terminal and a control terminal. The first terminal of the fourth transistor T14 is coupled to the first terminal of the third transistor T13. The second terminal of the fourth transistor T14 is coupled to the second terminal of the third transistor T13. The control terminal of the fourth transistor T14 receives the second input signal IN2_1.

The fifth transistor T15 has a first terminal, a second terminal and a control terminal. The second terminal of the fifth transistor T15 is coupled to the second terminal of the third transistor T13. The control terminal of the fifth transistor T15 receives the first selecting signal S1. The sixth transistor T16 has a first terminal, a second terminal and a control terminal. The second terminal of the sixth transistor T16 is coupled to the second terminal of fifth transistor T15. The control terminal of the sixth transistor T16 receives the second selecting signal S2.

The seventh transistor T17 has a first terminal, a second terminal and a control terminal. The first terminal of the seventh transistor T17 receives the second reference voltage VSS. The second terminal of the seventh transistor T17 is coupled to the first terminal of the fifth transistor T15. The control terminal of the seventh transistor T17 receives the first input signal IN1_1. The eighth transistor T18 has a first terminal, a second terminal and a control terminal. The first terminal of the eighth transistor T18 receives the second reference voltage VSS. The second terminal of the eighth transistor T18 is coupled to the first terminal of the sixth transistor T16. The control terminal of the eighth transistor T18 receives the second input signal IN2_1.

The ninth transistor T19 has a first terminal, a second terminal and a control terminal. The first terminal of the ninth transistor T19 receives the first reference voltage VDD. The second terminal of the ninth transistor T19 generates the first output signal OUT_1. The control terminal of the ninth transistor T19 is coupled to the second terminal of the third transistor T13. The tenth transistor T20 has a first terminal, a second terminal and a control terminal. The first terminal of the tenth transistor T20 receives the second reference voltage VSS. The second terminal of the tenth transistor T20 is coupled to the second terminal of the ninth transistor T19. The control terminal of the tenth transistor T20 is coupled to the control terminal of the ninth transistor T19.

In some embodiments, each of the first transistor T11, the second transistor T12, the third transistor T13, the fourth transistor T14 and the ninth transistor T19 is, for example, a P-type transistor. Each of the first terminals of the first transistor T11, the second transistor T12, the third transistor T13, the fourth transistor T14 and the ninth transistor T19 is, for example, a source terminal of the P-type transistor. Each of the second terminals of the first transistor T11, the second transistor T12, the third transistor T13, the fourth transistor T14 and the ninth transistor T19 is, for example, a drain terminal of the P-type transistor. Each of the control terminals of the first transistor T11, the second transistor T12, the third transistor T13, the fourth transistor T14 and the ninth transistor T19 is, for example, a gate terminal of the P-type transistor.

In addition, each of the fifth transistor T15, the sixth transistor T16, the seventh transistor T17, the eighth transistor T18 and the tenth transistor T20 is, for example, an N-type transistor. Each of the first terminals the fifth transistor T15, the sixth transistor T16, the seventh transistor T17, the eighth transistor T18 and the tenth transistor T20 is, for example, a source terminal of the N-type transistor. Each of the second terminals of the fifth transistor T15, the sixth transistor T16, the seventh transistor T17, the eighth transistor T18 and the tenth transistor T20 is, for example, a drain terminal of the N-type transistor. Each of the control terminals of the fifth transistor T15, the sixth transistor T16, the seventh transistor T17, the eighth transistor T18 and the tenth transistor T20 is, for example, a gate terminal of the P-type transistor.

In summary, according to the integrated circuit device and chip device disclosed by the present disclosure, the first cell and the second cell share the same reference voltage channel (i.e., the same first reference voltage and the same second reference voltage) or the selecting modules share the same selecting signal providing module (i.e., the same first selecting signal and the same second selecting signal). Therefore, the area and power consumption of the integrated circuit device may be effectively decreased.

While the disclosure has been described by way of example and in terms of the preferred embodiments, it should be understood that the disclosure is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.

Claims

1. An integrated circuit device, comprising: a reference voltage channel, configured to provide a first reference voltage and a second reference voltage;a first cell, coupled to the reference voltage channel, and configured to receive the first reference voltage and the second reference voltage; anda second cell, coupled to the reference voltage channel, and configured to receive the first reference voltage and the second reference voltage.

2. The integrated circuit device as claimed in claim 1, wherein the first reference voltage is a system voltage, and the second reference voltage is a ground voltage.

3. The integrated circuit device as claimed in claim 1, wherein each of the first cell and the second cell comprises a plurality of transistors.

4. The integrated circuit device as claimed in claim 3, wherein the plurality of transistors at least comprise an N-type transistor and a P-type transistor.

5. The integrated circuit device as claimed in claim 3, wherein a number of the plurality of transistors of the first cell is equal to a number of the plurality of transistors of the second cell.

6. The integrated circuit device as claimed in claim 3, wherein a number of the plurality of transistors of the first cell is less than a number of the plurality of transistors of the second cell.

7. The integrated circuit device as claimed in claim 3, wherein a number of the plurality of transistors of the first cell is greater than a number of the plurality of transistors of the second cell.

8. The integrated circuit device as claimed in claim 1, wherein the first cell comprises an input terminal and an output terminal.

9. The integrated circuit device as claimed in claim 1, wherein the second cell comprises an input terminal and an output terminal.

10. The integrated circuit device as claimed in claim 1, wherein the first cell is disposed on a first side of the reference voltage channel, and the second cell is disposed on a second side of the reference voltage channel.

11. The integrated circuit device as claimed in claim 10, wherein the second side is opposite to the first side.

12. A chip device, comprising at least one integrated circuit device as claimed in claim 1.

13. An integrated circuit device, comprising: a plurality of selecting modules, wherein each of the plurality of selecting modules is configured to receive a first input signal, a second input signal, a first selecting signal and a second selecting signal, and select the first input signal or the second input signal to generate an output signal according to a first selecting signal and a second selecting signal; anda selecting signal providing module, configured to provide the first selecting signal and the second selecting signal.

14. The integrated circuit device as claimed in claim 13, wherein the first selecting signal and the second selecting signal are inverted.

15. The integrated circuit device as claimed in claim 13, wherein the selecting signal providing module comprises: an inverter, having an input terminal and an output terminal, wherein the input terminal of the inverter receives the first selecting signal, and the output terminal of the inverter outputs the second selecting signal.

16. The integrated circuit device as claimed in claim 13, wherein each of the plurality of selecting modules comprises a multiplexer.

17. The integrated circuit device as claimed in claim 13, wherein each of the plurality of selecting modules comprises: a first transistor, having a first terminal, a second terminal and a control terminal, wherein the first terminal of the first transistor receives a first reference voltage, and the control terminal of the first transistor receives the first input signal;a second transistor, having a first terminal, a second terminal and a control terminal, wherein the first terminal of the second transistor receives a second reference voltage, the second terminal of the second transistor is coupled to the second terminal of the first transistor, and the control terminal of the second transistor is coupled to the control terminal of the first transistor;a third transistor, having a first terminal, a second terminal and a control terminal, wherein the first terminal of the third transistor receives the first reference voltage, and the control terminal of the third transistor receives the second input signal;a fourth transistor, having a first terminal, a second terminal and a control terminal, wherein the first terminal of the fourth transistor receives the second reference voltage, the second terminal of the fourth transistor is coupled to the second terminal of the third transistor, and the control terminal of the fourth transistor is coupled to the control terminal of the third transistor;a fifth transistor, having a first terminal, a second terminal and a control terminal, wherein the first terminal of the fifth transistor is coupled to the second terminal of the first transistor, and the control terminal of the fifth transistor receives the first selecting signal;a sixth transistor, having a first terminal, a second terminal and a control terminal, wherein the first terminal of the sixth transistor is coupled to the second terminal of the fifth transistor, the second terminal of the sixth transistor is coupled to the first terminal of the fifth transistor, and the control terminal of the sixth transistor receives the second selecting signal;a seventh transistor, having a first terminal, a second terminal and a control terminal, wherein the first terminal of the seventh transistor is coupled to the second terminal of the third transistor, and the control terminal of the seventh transistor receives the second reference voltage;an eighth transistor, having a first terminal, a second terminal and a control terminal, wherein the first terminal of the eighth transistor is coupled to the second terminal of the seventh transistor, the second terminal of the eighth transistor is coupled to the first terminal of the seventh transistor, and the control terminal of the eighth transistor receives the first selecting signal;a ninth transistor, having a first terminal, a second terminal and a control terminal, wherein the first terminal of the ninth transistor receives the first reference voltage, and the second terminal of the ninth transistor generates the first output signal, and the control terminal of the ninth transistor is coupled to the second terminal of the fifth transistor and the second terminal of the seventh transistor;a tenth transistor, having a first terminal, a second terminal and a control terminal, wherein the first terminal of the tenth transistor receives the second reference voltage, the second terminal of the tenth transistor is coupled to the second terminal of the ninth transistor, and the control terminal of the tenth transistor is coupled to the control terminal of the ninth transistor.

18. The integrated circuit device as claimed in claim 17, wherein each of the first transistor, the third transistor, the fifth transistor, the seventh transistor and the ninth transistor is a P-type transistor, and each of the second transistor, the fourth transistor, the sixth transistor, the eighth transistor and the tenth transistor is an N-type transistor.

19. The integrated circuit device as claimed in claim 13, wherein each of the plurality of selecting modules comprises: a first transistor, having a first terminal, a second terminal and a control terminal, wherein the first terminal of the first transistor receives a first reference voltage, and the control terminal of the first transistor receives the second selecting signal;a second transistor, having a first terminal, a second terminal and a control terminal, wherein the first terminal of the second transistor receives the first reference voltage, the second terminal of the second transistor is coupled to the second terminal of the first transistor, and the control terminal of the second transistor receives the first input signal;a third transistor, having a first terminal, a second terminal and a control terminal, wherein the first terminal of the third transistor is coupled to the second terminal of the first transistor, and the control terminal of the third transistor receives the first selecting signal;a fourth transistor, having a first terminal, a second terminal and a control terminal, wherein the first terminal of the fourth transistor is coupled to the first terminal of the third transistor, the second terminal of the fourth transistor is coupled to the second terminal of the third transistor, and the control terminal of the fourth transistor receives the second input signal;a fifth transistor, having a first terminal, a second terminal and a control terminal, wherein the second terminal of the fifth transistor is coupled to the second terminal of the third transistor, and the control terminal of the fifth transistor receives the first selecting signal;a sixth transistor, having a first terminal, a second terminal and a control terminal, wherein the second terminal of the sixth transistor is coupled to the second terminal of fifth transistor, and the control terminal of the sixth transistor receives the second selecting signal;a seventh transistor, having a first terminal, a second terminal and a control terminal, wherein the first terminal of the seventh transistor receives the second reference voltage, the second terminal of the seventh transistor is coupled to the first terminal of the fifth transistor, and the control terminal of the seventh transistor receives the first input signal;an eighth transistor, having a first terminal, a second terminal and a control terminal, wherein the first terminal of the eighth transistor receives the second reference voltage, the second terminal of the eighth transistor is coupled to the first terminal of the sixth transistor, and the control terminal of the eighth transistor receives the second input signal;a ninth transistor, having a first terminal, a second terminal and a control terminal, wherein the first terminal of the ninth transistor receives the first reference voltage, the second terminal of the ninth transistor generates the first output signal, and the control terminal of the ninth transistor is coupled to the second terminal of the third transistor; anda tenth transistor, having a first terminal, a second terminal and a control terminal, wherein the first terminal of the tenth transistor receives the second reference voltage, the second terminal of the tenth transistor is coupled to the second terminal of the ninth transistor, and the control terminal of the tenth transistor is coupled to the control terminal of the ninth transistor.

20. The integrated circuit device as claimed in claim 19, wherein each of the first transistor, the second transistor, the third transistor, the fourth transistor and the ninth transistor is a P-type transistor, and each of the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor and the tenth transistor is an N-type transistor.