Patent Application
20080117234
Japanese Patent Application No. 2006-315706 and Japanese Patent Application No. 2006-315705, both filed on Nov. 22, 2006, are hereby incorporated by reference in their entirety.
The present invention relates to an integrated circuit device, an electronic instrument, and the like.
In recent years, a high-speed serial transfer such as low voltage differential signaling (LVDS) has attracted attention as an interface aiming at reducing EMI noise or the like. In such a high-speed serial transfer, data is transferred by causing a transmitter circuit to transmit serialized data using differential signals and causing a receiver circuit to differentially amplify the differential signals.
An ordinary portable telephone includes a first instrument section provided with buttons for inputting a telephone number and characters, a second instrument section provided with a liquid crystal display (LCD) and a camera device, and a connection section (e.g., hinge) which connects the first and second instrument sections. Therefore, the number of interconnects passing through the connection section can be reduced by transferring data between a first circuit board provided in the first instrument section and a second circuit board provided in the second instrument section by a high-speed serial transfer using small-amplitude differential signals.
A display driver (LCD driver) is known as an integrated circuit device which drives a display panel such as a liquid crystal panel. In order to realize a high-speed serial transfer between the first and second instrument sections, a high-speed interface circuit which transfers data through a serial bus must be incorporated in the display driver (see JP-A-2001-222249).
On the other hand, since the high-speed interface circuit handles differential signals with a small voltage amplitude of 0.1 to 1.0 V, for example, the high-speed interface circuit tends to be affected by noise from other signal lines. In particular, when noise from a signal with a large amplitude (e.g., scan signal transmitted through a scan line) is transmitted to the high-speed interface circuit, a malfunction such as a transfer error may occur.
A display panel includes an array substrate in which thin film transistors (TFTs) are disposed in an array, and a common substrate on which a common electrode is formed. The display driver outputs a data signal (source signal) supplied to the source of the TFT and a scan signal (gate signal) supplied to the gate of the TFT. The display driver generates and outputs a common voltage (common electrode voltage) applied to the common electrode.
In this case, the voltage difference between the voltage of the data signal and the common voltage is applied to a liquid crystal element. Therefore, when the common voltage generated by the display driver does not reach the desired voltage due to parasitic resistance and the like, the voltage applied to the liquid crystal element does not reach the desired voltage, whereby the display quality deteriorates.
According to one aspect of the invention, there is provided an integrated circuit device comprising:
at least one scan driver block that drives a plurality of scan lines of a display panel;
a high-speed interface circuit block that transfers data through a serial bus using differential signals; and
a scan driver pad arrangement region in which a plurality of pads electrically connecting a plurality of scan output lines of the plurality of scan driver block and the scan lines are disposed;
the high-speed interface circuit block including:
a physical layer circuit that receives data using the differential signals; and
a link controller that performs a link layer process; and
the plurality of scan output lines as output lines of the scan driver block being provided from the scan driver block to the scan driver pad arrangement region to pass over the link controller while avoiding the physical layer circuit.
According to another aspect of the invention, there is provided an integrated circuit device comprising:
a common voltage generation circuit that generates a common voltage applied to a common electrode of a display panel;
a high-speed interface circuit block that includes a physical layer circuit and transfers data through a serial bus using differential signals; and
first and second common voltage pads that output the common voltage generated by the common voltage generation circuit to the outside;
when a direction from a first side as a short side of the integrated circuit device toward a third side opposite to the first side is referred to as a first direction, a direction from a second side as a long side of the integrated circuit device toward a fourth side opposite to the second side is referred to as a second direction, a direction opposite to the first direction is referred to as a third direction, and a direction opposite to the second direction is referred to as a fourth direction, the first common voltage pad being disposed in the third direction with respect to the data driver block, and the second common voltage pad being disposed in the first direction with respect to the data driver block;
first and second differential input pads to which first and second signals forming the differential signals are input from the outside being disposed in the fourth direction with respect to the physical layer circuit; and
a common voltage line connecting the first and second common voltage pads being provided from the first common voltage pad to the second common voltage pad along the first direction, the common voltage line being provided in the second direction with respect to the physical layer circuit along the first direction in an arrangement region of the physical layer circuit.
According to a further aspect of the invention, there is provided an electronic instrument comprising:
the above integrated circuit device; and
a display panel driven by the integrated circuit device.
Aspects of the invention may provide an integrated circuit device which can prevent a malfunction and the like when incorporating a high-speed interface circuit, and an electronic instrument including the same.
Further aspects of the invention may provide an integrated circuit device in which a high-speed interface circuit can be incorporated while preventing deterioration in display quality, and an electronic instrument including the same.
According to one embodiment of the invention, there is provided an integrated circuit device comprising:
at least one scan driver block that drives a plurality of scan lines of a display panel;
a high-speed interface circuit block that transfers data through a serial bus using differential signals; and
a scan driver pad arrangement region in which a plurality of pads electrically connecting a plurality of scan output lines of the plurality of scan driver block and the scan lines are disposed;
the high-speed interface circuit block including:
a physical layer circuit that receives data using the differential signals; and
a link controller that performs a link layer process; and
the plurality of scan output lines as output lines of the scan driver block being provided from the scan driver block to the scan driver pad arrangement region to pass over the link controller while avoiding the physical layer circuit.
According to this embodiment, since the high-speed interface circuit block is incorporated in the integrated circuit device, a high-speed serial transfer using the differential signals can be performed between the integrated circuit device and an external device. Since the integrated circuit device includes the scan driver block, it is necessary to provide a large number of scan output lines from the scan driver block to the scan driver pad arrangement region, and signal noise from the scan output lines may adversely affect the high-speed interface circuit block. According to this embodiment, the scan output lines of the scan driver block are provided to avoid the physical layer circuit. This effectively prevents a situation in which a change in the voltage level of the scan output lines is transmitted to the physical layer circuit as signal noise. Therefore, an integrated circuit device can be provided which can prevent a malfunction and the like when incorporating a high-speed interface circuit block.
In the integrated circuit device according to this embodiment,
the high-speed interface circuit block and the scan driver block may be disposed along a first direction; and
when a direction perpendicular to the first direction is referred to as a second direction, the scan driver pad arrangement region may be provided in the second direction with respect to the high-speed interface circuit block and the scan driver block.
When employing such an arrangement relationship, if the scan output lines are provided without taking signal noise into account, the scan output lines are provided over the physical layer circuit. According to this embodiment, since the scan output lines are provided over the link controller while avoiding the physical layer circuit, a large number of scan output lines from the scan driver block can be provided while reducing an adverse effect of signal noise.
In the integrated circuit device according to this embodiment,
the link controller may be disposed in the second direction with respect to the physical layer circuit.
According to this configuration, since the scan output lines can be provided by effectively utilizing the wiring area over the link controller disposed in the second direction with respect to the physical layer circuit, the layout efficiency can be increased.
In the integrated circuit device according to this embodiment, the integrated circuit device may comprise:
a logic circuit block that receives data received by the high-speed interface circuit block and controls the scan driver block;
the high-speed interface circuit block may be disposed between the logic circuit block and the scan driver block.
This prevents a situation in which signal noise from a signal line and the like provided in the third direction with respect to the logic circuit block adversely affects the high-speed interface circuit block, for example.
In the integrated circuit device according to this embodiment,
the logic circuit block and the link controller may be integrally formed by automatic placement and routing.
This enables the main logic section of the integrated circuit device (i.e., logic circuit block and link controller) to be formed by one automatic placement and routing, for example, whereby the design efficiency and the work efficiency can be increased.
In the integrated circuit device according to this embodiment,
the integrated circuit device may include a shield line provided in the link controller in a lower layer of the plurality of scan output lines of the scan driver block passing over the link controller.
According to this configuration, a situation in which can be prevented in which noise due to a change in the voltage level of the scan output lines is transmitted to circuits and signal lines in the link controller due to capacitive coupling.
According to another embodiment of the invention, there is provided an integrated circuit device comprising:
a common voltage generation circuit that generates a common voltage applied to a common electrode of a display panel;
a high-speed interface circuit block that includes a physical layer circuit and transfers data through a serial bus using differential signals; and
first and second common voltage pads that output the common voltage generated by the common voltage generation circuit to the outside;
when a direction from a first side as a short side of the integrated circuit device toward a third side opposite to the first side is referred to as a first direction, a direction from a second side as a long side of the integrated circuit device toward a fourth side opposite to the second side is referred to as a second direction, a direction opposite to the first direction is referred to as a third direction, and a direction opposite to the second direction is referred to as a fourth direction, the first common voltage pad being disposed in the third direction with respect to the data driver block, and the second common voltage pad being disposed in the first direction with respect to the data driver block;
first and second differential input pads to which first and second signals forming the differential signals are input from the outside being disposed in the fourth direction with respect to the physical layer circuit; and
a common voltage line connecting the first and second common voltage pads being provided from the first common voltage pad to the second common voltage pad along the first direction, the common voltage line being provided in the second direction with respect to the physical layer circuit along the first direction in an arrangement region of the physical layer circuit.
According to this embodiment, the first and second common voltage pads are connected through the common voltage line. Therefore, deterioration in display quality due to the imbalanced parasitic resistance of the common voltage line can be reduced. The common voltage line is provided in the second direction with respect to the physical layer circuit along the first direction. Therefore, noise from the common voltage line can be prevented from being superimposed on the differential signals of the physical layer circuit, whereby a malfunction of the high-speed interface circuit due to noise can be prevented.
In the integrated circuit device according to this embodiment,
the common voltage line may be provided in the fourth direction with respect to the data driver block along the first direction in an arrangement region of the data driver block.
According to this configuration, since the data signal line from the data driver block does not intersect the common voltage line, a situation in which the display quality deteriorates due to a change in the level of the common voltage caused by noise from the data signal line can be prevented.
In the integrated circuit device according to this embodiment,
the high-speed interface circuit block may include a link controller that is disposed in the second direction with respect to the physical layer circuit and performs a link layer process; and
the common voltage line may be provided in the second direction with respect to the link controller along the first direction.
This prevents a situation in which noise from the signal line between the physical layer circuit and the link controller is transmitted to the common voltage line.
In the integrated circuit device according to this embodiment,
the common voltage generation circuit may be disposed in the third direction with respect to the data driver block.
In the integrated circuit device according to this embodiment,
the integrated circuit device may include a first shield line formed of an interconnect layer in a layer differing from the common voltage line and provided with a given power supply potential, the first shield line being provided to overlap the common voltage line.
This enables noise from the upper side or the lower side of the common voltage line to be effectively shielded using the first shield line.
In the integrated circuit device according to this embodiment,
the integrated circuit device may include second shield lines formed of an interconnect layer in the same layer as the common voltage line and provided with a given power supply potential, the second shield lines being provided on either side of the common voltage line.
This enables noise from each side of the common voltage line to be effectively shielded using the second shield lines.
In the integrated circuit device according to this embodiment, the integrated circuit device may comprise:
first to Nth circuit blocks (N is an integer equal to or larger than two) disposed along a first direction, the first to Nth circuit blocks including:
at least one data driver block that drives a plurality of data lines of the display panel;
a grayscale voltage generation circuit block that generates grayscale voltages; and
a logic circuit block that receives data received by the high-speed interface circuit block and transfers grayscale adjustment data for adjusting the grayscale voltages to the grayscale voltage generation circuit block;
when a direction perpendicular to the first direction is referred to as a second direction, a direction opposite to the first direction is referred to as a third direction, and a direction opposite to the second direction is referred to as a fourth direction, the grayscale voltage generation circuit block may be disposed in the third direction with respect to the data driver block, and the high-speed interface circuit block and the logic circuit block may be disposed in the first direction with respect to the data driver block.
According to this configuration, since the first to Nth circuit blocks are disposed along the first direction, the width of the integrated circuit device in the second direction can be reduced, whereby a reduction in area can be achieved. Moreover, interconnects can be provided utilizing the free space in the second direction with respect to the grayscale voltage generation circuit block and the logic circuit block, whereby the wiring efficiency can be increased. Furthermore, since the data driver block can be disposed near the center of the integrated circuit device, data signal output lines from the data driver block can be efficiently and simply provided.
In the integrated circuit device according to this embodiment, the integrated circuit device may include:
local lines provided between adjacent circuit blocks among the first to Nth circuit blocks, the local lines being formed of an interconnect layer lower than an Ith (I is an integer equal to or larger than three) layer;
global lines provided between nonadjacent circuit blocks among the first to Nth circuit blocks, the global lines being formed of an interconnect layer in a layer equal to or higher than the Ith layer to pass over a circuit block disposed between the nonadjacent circuit blocks along the first direction; and
grayscale global lines that supplies the grayscale voltages from the grayscale voltage generation circuit block to the data driver, the grayscale global lines being provided over the data driver block along the first direction.
This allows the adjacent circuit blocks to be connected along a short path using the local lines, whereby an increase in chip area due to the wiring region can be prevented. Moreover, since the global lines are provided between the nonadjacent circuit blocks, the grayscale global line can be provided over the local lines, even if the number of local lines is large.
In the integrated circuit device according to this embodiment, the integrated circuit device may comprise:
first to Nth circuit blocks (N is an integer equal to or larger than two) disposed along a first direction, the first to Nth circuit blocks including:
at least one data driver block that drives a plurality of data lines of the display panel;
a power supply circuit block that generates a power supply voltage; and
a logic circuit block that receives data received by the high-speed interface circuit block and transfers power supply adjustment data for adjusting the power supply voltage to the power supply circuit block;
when a direction perpendicular to the first direction is referred to as a second direction, a direction opposite to the first direction is referred to as a third direction, and a direction opposite to the second direction is referred to as a fourth direction, the power supply circuit block may be disposed in the third direction with respect to the data driver block, and the high-speed interface circuit block and the logic circuit block may be disposed in the first direction with respect to the data driver block.
According to this configuration, interconnects can be provided utilizing the free space in the second direction with respect to the power supply circuit block and the logic circuit block, whereby the wiring efficiency can be increased.
In the integrated circuit device according to this embodiment, the integrated circuit device may include:
local lines provided between adjacent circuit blocks among the first to Nth circuit blocks, the local lines being formed of an interconnect layer lower than an Ith (I is an integer equal to or larger than three) layer;
global lines provided between nonadjacent circuit blocks among the first to Nth circuit blocks, the global lines being formed of an interconnect layer in a layer equal to or higher than the Ith layer to pass over a circuit block disposed between the nonadjacent circuit blocks along the first direction; and
a power supply global line that supplies the power supply voltage from the power supply circuit block, the power supply global line being provided over the data driver block along the first direction.
According to this configuration, since the global lines are provided between the nonadjacent circuit blocks, the power supply global line can be provided over the local lines, even if the number of local lines is large, whereby the wiring efficiency can be increased.
In the integrated circuit device according to this embodiment, the integrated circuit device may comprise:
first to Nth circuit blocks (N is an integer equal to or larger than two) disposed along the first direction, the first to Nth circuit blocks including:
the data driver block;
a grayscale voltage generation circuit block that generates grayscale voltages; and
a logic circuit block that receives data received by the high-speed interface circuit block and transfers grayscale adjustment data for adjusting the grayscale voltages to the grayscale voltage generation circuit block;
the grayscale voltage generation circuit block may be disposed in the third direction with respect to the data driver block, and the high-speed interface circuit block and the logic circuit block may be disposed in the first direction with respect to the data driver block.
According to this configuration, since the first to Nth circuit blocks are disposed along the first direction, the width of the integrated circuit device in the second direction can be reduced, whereby a reduction in area can be achieved. Moreover, interconnects can be provided utilizing the free space in the second direction with respect to the grayscale voltage generation circuit block and the logic circuit block, whereby the wiring efficiency can be increased. Furthermore, since the data driver block can be disposed near the center of the integrated circuit device, data signal output lines from the data driver block can be efficiently and simply provided.
The integrated circuit device according to this embodiment may include: local lines provided between adjacent circuit blocks among the first to Nth circuit blocks, the local lines being formed of an interconnect layer lower than an Ith (I is an integer equal to or larger than three) layer; global lines provided between nonadjacent circuit blocks among the first to Nth circuit blocks, the global lines being formed of an interconnect layer in a layer equal to or higher than the Ith layer to pass over a circuit block disposed between the nonadjacent circuit blocks along the first direction; and a grayscale global line that supplies the grayscale voltage from the grayscale voltage generation circuit block to the data driver, the grayscale global line being provided over the data driver block along the first direction.
This allows the adjacent circuit blocks to be connected through the local lines along a short path, whereby an increase in chip area due to an increase in wiring region can be prevented. Moreover, since the global lines are provided between the nonadjacent circuit blocks, the grayscale global line can be provided over the local lines, even if the number of local lines is large.
In the integrated circuit device according to this embodiment, the logic circuit block may transfer the grayscale adjustment data to the grayscale voltage generation circuit block by time division through n-bit (n is a positive integer) grayscale transfer lines, and the grayscale transfer lines may be provided over the data driver block along the first direction using the global lines.
According to this configuration, since the grayscale adjustment data can be transferred through the grayscale transfer lines by time division in units of n bits, the number of grayscale transfer lines can be reduced.
In the integrated circuit device according to this embodiment, the first to Nth circuit blocks may include first and second scan driver blocks that drive the scan lines, the grayscale voltage generation circuit block may be disposed between the first scan driver block and the data driver block, and the high-speed interface circuit block may be disposed between the second scan driver block and the data driver block.
In the integrated circuit device according to this embodiment, the integrated circuit device may comprise:
first to Nth circuit blocks (N is an integer equal to or larger than two) disposed along the first direction, the first to Nth circuit blocks including:
the data driver block;
a power supply circuit block that generates a power supply voltage; and
a logic circuit block that receives data received by the high-speed interface circuit block and transfers power supply adjustment data for adjusting the power supply voltage to the power supply circuit block;
the power supply circuit block may be disposed in the third direction with respect to the data driver block, and the high-speed interface circuit block and the logic circuit block may be disposed in the first direction with respect to the data driver block.
According to this configuration, interconnects can be provided utilizing the free space in the second direction with respect to the power supply circuit block and the logic circuit block, whereby the wiring efficiency can be increased.
The integrated circuit device according to this embodiment may include: local lines provided between adjacent circuit blocks among the first to Nth circuit blocks, the local lines being formed of an interconnect layer lower than an Ith (I is an integer equal to or larger than three) layer; global lines provided between nonadjacent circuit blocks among the first to Nth circuit blocks, the global lines being formed of an interconnect layer in a layer equal to or higher than the Ith layer to pass over a circuit block disposed between the nonadjacent circuit blocks along the first direction; and a power supply global line that supplies the power supply voltage from the power supply circuit block, the power supply global line being provided over the data driver block along the first direction.
According to this configuration, since the global lines are provided between the nonadjacent circuit blocks, the power supply global line can be provided over the local lines, even if the number of local lines is large, whereby the wiring efficiency can be increased.
In the integrated circuit device according to this embodiment, the logic circuit block may transfer the power supply adjustment data to the power supply circuit block by time division through m-bit (m is a positive integer) power supply transfer lines, and the power supply transfer lines may be provided over the data driver block along the first direction using the global lines.
According to this configuration, since the power supply adjustment data can be transferred through the power supply transfer lines by time division in units of m bits, the number of power supply transfer lines can be reduced.
In the integrated circuit device according to this embodiment, the first to Nth circuit blocks may include first and second scan driver blocks that drive the scan lines, the power supply circuit block may be disposed between the first scan driver block and the data driver block, and the high-speed interface circuit block may be disposed between the second scan driver block and the data driver block.
According to a further embodiment of the invention, there is provided an electronic instrument comprising:
one of the above integrated circuit devices; and
a display panel driven by the integrated circuit device.
Preferred embodiments of the invention are described below in detail. Note that the embodiments described below do not in any way limit the scope of the invention defined by the claims laid out herein. Note that all elements of the embodiments described below should not necessarily be taken as essential requirements for the invention.
In recent years, a high-speed I/F circuit (high-speed interface circuit) which serially transfers data using differential signals has attracted attention. Since the high-speed I/F circuit handles small-amplitude differential signals, the high-speed I/F circuit tends to be affected by noise, whereby a malfunction such as a data transfer error may occur due to noise. Therefore, it is desirable to minimize the effect of noise on the high-speed I/F circuit. When providing a scan driver (gate driver) in an integrated circuit device such as a display driver, the amplitude of the output signal of the scan driver is about 10 to 20 V, for example, which is much larger than the amplitude of the differential signals. Therefore, the high-speed I/F circuit may malfunction due to noise from the output signal of the scan driver when no measures are taken.
The scan driver block SB outputs a scan signal (gate signal) with an amplitude of about 10 to 20 V as a select signal of the scan line of the display panel. The scan signals are input to the pads provided in the scan driver pad arrangement region PR through the scan output lines indicated by H1. The scan signals are output to the scan lines (gate lines) of the external display panel through the pads.
The physical layer circuit PHY included in the high-speed I/F circuit block HB is a circuit which transfers data through a serial bus using differential signals. For example, the physical layer circuit PHY receives data (packet) using differential signals. Specifically, the physical layer circuit PHY may include a receiver circuit to which first and second signals forming small-amplitude differential signals are input. The physical layer circuit PHY may include a serial/parallel conversion circuit which converts serial data received through the serial bus into parallel data. The physical layer circuit PHY may include a transmitter circuit which transmits data using differential signals, and a parallel/serial conversion circuit which converts parallel data into serial data.
The link controller LKC included in the high-speed I/F circuit block HB performs a link layer process such as processing a packet. Specifically, the link controller LKC analyzes a packet received through the physical layer circuit PHY. Or, the link controller LKC may generate a packet transmitted through the physical layer circuit PHY. The link controller LKC may detect a communication error or control a transfer sequence at the link layer level.
In
According to the embodiment shown in
In
According to the arrangement relationship shown in
However, according to the arrangement relationship shown in
According to this embodiment, even if the scan driver block SB, the high-speed I/F circuit block HB, and the scan driver pad arrangement region PR have the arrangement relationship shown in
In
In
The logic circuit block LB receives data received by the high-speed I/F circuit block HB. Specifically, the logic circuit block LB receives data received by the physical layer circuit PHY using differential signals and extracted (analyzed) by a packet analysis circuit of the link controller LKC. The logic circuit block LB controls the scan driver block SB. Specifically, the logic circuit block LB controls various timings such as the scan line scan start timing of the scan driver block SB. The logic circuit block LB also controls the high-speed I/F circuit block HB and a data driver block described later. The logic circuit block LB may be formed by automatic placement and routing using a gate array (G/A) or the like.
In
According to the arrangement shown in
A large number of I/O signal lines from an 10 pad region are provided in the logic circuit block LB along the direction D1. The data driver blocks are disposed in the direction D3 with respect to the logic circuit block LB, as described later, and a large number of global lines are provided over the data driver blocks along the direction D1. Specifically, a large number of signal lines such as the global lines and the I/O signal lines are provided in the direction D3 with respect to the logic circuit block LB. Therefore, if the high-speed I/F circuit block HB is disposed in the direction D3 with respect to the logic circuit block LB, the high-speed I/F circuit block HB may malfunction due to noise from these signal lines.
In
When disposing the high-speed I/F circuit block HB between the logic circuit block LB and the scan driver block SB, noise from the scan output line may be transmitted to the physical layer circuit PHY, whereby a malfunction or the like may occur. In
When the logic circuit block LB and the link controller LKC are adjacently disposed along the direction D1, as shown in
This enables the main logic section of the integrated circuit device 10 to be formed by one automatic placement and routing, for example, whereby the design efficiency and the work efficiency can be increased. Moreover, a signal skew and a jitter between the logic circuit block LB and the link controller LKC are optimally reduced by the above integral automatic placement and routing.
The arrangement configuration of the logic circuit block LB, the physical layer circuit PHY, the link controller LKC, and the scan driver block SB is not limited to that shown in
In the link controller LKC, shield lines may be provided in the lower layer of the scan output lines of the scan driver block SB passing over the link controller LKC. For example, shield lines formed using a metal layer in the lower layer of a metal layer forming the scan output lines are provided.
In
In
As shown in
Since a liquid crystal element (electro-optical element in a broad sense) deteriorates when a direct-current voltage is applied for a long period of time, a drive method such as frame inversion drive, scan line inversion drive, data line inversion drive, or dot inversion drive is used.
Scan line inversion drive is employed in a signal waveform example shown in
The positive period T1 is a period in which the voltage level of the pixel electrode to which the grayscale voltage is supplied through the data line is higher than the voltage level of the common electrode 322. In the period T1, a positive voltage is applied to the liquid crystal element. The negative period T2 is a period in which the voltage level of the pixel electrode to which the grayscale voltage is supplied through the data line is lower than the voltage level of the common electrode 322. In the period T2, a negative voltage is applied to the liquid crystal element.
As is clear from
4. Common Voltage Line of Integrated Circuit Device
The high-speed I/F circuit is easily affected by external noise, as described above. On the other hand, the display quality of the display panel deteriorates when the parasitic resistance of the common voltage line increases. Therefore, it is desirable to employ a layout method described below.
In
In
The common voltage generation circuit VCB generates the common voltage VCOM applied to the common electrode of the display panel. Specifically, the common voltage generation circuit VCB generates the common voltage VCOM of which the polarity is reversed in units of scan periods, for example.
The data driver block DB is a circuit which drives the data lines of the display panel. In this case, two or more data driver blocks may be provided along the direction D1, for example. A memory block may be provided which is disposed adjacent to the data driver block DB in the direction D1 and stores image data used in the data driver block DB. Or, the memory block may be disposed adjacent to the data driver block DB in the direction D4.
In
First and second differential input pads PP and PM for externally inputting first and second signals DP and DM forming differential signals are disposed in the direction D4 (host side) with respect to the physical layer circuit PHY. A common voltage line VCL (in-chip common voltage line) which connects the common voltage pads PC1 and PC2 is provided from the common voltage pad PC1 to the common voltage pad PC2 along the direction D1. Specifically, the common voltage line VCL is provided in the direction D2 with respect to the physical layer circuit PHY along the direction D1 in the arrangement region of the physical layer circuit PHY. That is, the common voltage line VCL provided from the common voltage pad PC1 in the direction D1 turns along the direction D2 to run around the physical layer circuit PHY so as to avoid the physical layer circuit PHY. The common voltage line VCL is thus provided in the direction D2 with respect to the physical layer circuit PHY along the direction D1, continues in the direction D1, and then turns along the direction D4. The common voltage line VCL is then connected to the common voltage pad PC2.
In
In
In
The common voltage generation circuit VCB is disposed in the direction D3 with respect to the data driver block DB. The common voltage generation circuit VCB may be disposed in the direction D1 with respect to the data driver block DB. As shown in
In this embodiment, the common voltage line VCL connects the common voltage pads PC1 and PC2 in the chip of the integrated circuit device 10, as shown in
For example, if the common voltage pads PC1 and PC2 are not electrically connected in the chip of the integrated circuit device 10 in
According to this embodiment, since the common voltage pads PC1 and PC2 are electrically connected through the common voltage line VCL, the parasitic resistance of the common voltage line at a position indicated by B2 in
In this embodiment, the common voltage line VCL is provided to avoid the differential signal lines which connect the physical layer circuit PHY and the differential input pads PP and PM. This prevents a situation in which noise from the common voltage line VCL, of which the voltage changes in units of horizontal scan periods, is superimposed on the input signals DP and the DM of the physical layer circuit PHY, for example. Specifically, if the common voltage line VCL provided from the common voltage pad PC1 along the direction D1 is linearly provided along the direction D1 in the region of the physical layer circuit PHY, the common voltage line VCL intersects the differential signal lines from the differential input pads PP and PM. As a result, noise from the common voltage line VCL is superimposed on the differential signals DP and DM through parasitic capacitors and the like, whereby a data transfer error or the like may occur.
According to this embodiment, since the common voltage line VCL is provided to avoid intersection with the signals DP and DM, such a problem can be prevented.
In
The signal lines which operate at a high speed are provided between the physical layer circuit PHY and the link controller LKC. Therefore, if the common voltage line VCL is provided between the physical layer circuit PHY and the link controller LKC, noise from the high-speed signal lines may be transmitted to the common voltage line VCL, whereby the display quality may deteriorate.
In
When providing the panel common voltage line under the integrated circuit device 10, as shown in
The switch circuit SEL includes a P-type (first conductivity type) transistor TL1 and an N-type (second conductivity type) transistor TL2. The output of the operational amplifier OPH is connected with the source of the transistor TL1, and a polarity inversion signal POL which specifies the polarity inversion timing is input to the gate of the transistor TL1. The output of the operational amplifier OPL is connected with the source of the transistor TL2, and the polarity inversion signal POL is input to the gate of the transistor TL2. The common voltage VCOM is output to the drains of the transistors TL1 and TL2.
The high-potential-side voltage VCOMH and the low-potential-side voltage VCOML of the common voltage VCOM may be obtained by causing a power supply circuit (not shown) to boost the power supply voltage using a charge pump method, for example.
The logic circuit block LB receives data received by the high-speed I/F circuit block HB. The logic circuit block LB transfers grayscale adjustment data for adjusting the grayscale voltage to the grayscale voltage generation circuit block GB, and transfers power supply adjustment data for adjusting the power supply voltage to the power supply circuit block PB.
In
The grayscale voltage generation circuit block GB is disposed between the first scan driver block SB1 and the data driver blocks DB1 to DBJ. The high-speed I/F circuit block HB is disposed between the second scan driver block SB2 and the data driver blocks DB1 to DBJ. The common voltage generation circuit VCB is disposed in the direction D4 with respect to the scan driver block SB1.
In
When disposing the scan driver blocks SB1 and SB2 on either end of the integrated circuit device 10, as shown in
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For example, when mounting the integrated circuit device 10 on a glass substrate (array substrate) using bumps by means of COG technology, the contact resistance of the bumps increases on each end of the integrated circuit device 10. Specifically, since the coefficient of thermal expansion differs between the integrated circuit device 10 and the glass substrate, stress (thermal stress) caused by the difference in coefficient of thermal expansion becomes greater on each end of the integrated circuit device 10 than at the center of the integrated circuit device 10. As a result, the contact resistance of the bumps increases with time on each end of the integrated circuit device 10. In particular, the narrower the integrated circuit device 10, the larger the difference in stress between each end and the center, and the greater the increase in contact resistance of the bumps on each end.
In the high-speed I/F circuit block HB, the impedance is matched between the transmission side and the reception side in order to prevent signal reflection. Therefore, an impedance mismatch may occur when the contact resistance of the bumps connected to the pads PP and PM of the high-speed I/F circuit block HB increases, whereby the signal quality of high-speed serial transfer may deteriorate. Therefore, it is desirable to dispose the high-speed I/F circuit block HB near the center of the integrated circuit device 10, taking the contact resistance into consideration.
In
When providing the long common voltage line VCL on the narrow integrated circuit device 10 along the direction D1, as shown in
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In
When other signal lines are provided over the common voltage line VCL, the shield lines SLD1, SLD2, and SLD3 may be provided as shown in
The shielding method for the common voltage line VCL described with reference to
As indicated by H4 in
The voltage level of the scan output lines changes at an amplitude of 10 to 20 V in specific cycles. Therefore, signal noise caused by a change in the voltage level of the scan output lines may be transmitted to the common voltage line VCL through parasitic capacitors, whereby the display characteristics may deteriorate.
In this case, a change in the voltage level of the scan output lines is shielded by the shield lines SLD1 to SLD3 and the like and is prevented from being transmitted to the common voltage line VCL by employing the shielding method described with reference to
A display panel includes data lines (source lines), scan lines (gate lines), and pixels, each of the pixels being specified by one of the data lines and one of the scan lines. A display operation is implemented by changing the optical properties of an electro-optical element (liquid crystal element in a narrow sense) in each pixel region. The display panel may be formed using an active matrix type panel using a switching element such as a TFT or TFD. The display panel may be a panel other than the active matrix type panel, or may be a panel (e.g. organic EL panel) other than the liquid crystal panel.
A memory 20 (display data RAM) stores image data. A memory cell array 22 includes memory cells, and stores image data (display data) of at least one frame (one screen). A row address decoder 24 (MPU/LCD row address decoder) decodes a row address, and selects a wordline of the memory cell array 22. A column address decoder 26 (MPU column address decoder) decodes a column address, and selects a bitline of the memory cell array 22. A write/read circuit 28 (MPU write/read circuit) writes image data into the memory cell array 22 or reads image data from the memory cell array 22.
A logic circuit 40 (driver logic circuit) generates a control signal for controlling the display timing, a control signal for controlling the data processing timing, and the like. The logic circuit 40 may be formed by automatic placement and routing (e.g., gate array (G/A)), for example.
A control circuit 42 generates various control signals, and controls the entire device. Specifically, the control circuit 42 outputs grayscale adjustment data (gamma correction data) for adjusting grayscale characteristics (gamma characteristics) to a grayscale voltage generation circuit 110, and outputs power supply adjustment data for adjusting the power supply voltage to a power supply circuit 90. The control circuit 42 also controls a memory write/read process using the row address decoder 24, the column address decoder 26, and the write/read circuit 28. A display timing control circuit 44 generates various control signals for controlling the display timing, and controls reading of image data from the memory 20 into the display panel. A host (MPU) interface circuit 46 implements a host interface for generating an internal pulse and accessing the memory 20 on each occasion of access from a host. An RGB interface circuit 48 implements an RGB interface for writing video image RGB data into the memory 20 based on a dot clock signal. The integrated circuit device may be configured to include only one of the host interface circuit 46 and the RGB interface circuit 48.
A data driver 50 is a circuit which generates a data signal for driving the data line of the display panel. Specifically, the data driver 50 receives the image data (grayscale data) from the memory 20, and receives a plurality of (e.g. 256 stages) grayscale voltages (reference voltages) from the grayscale voltage generation circuit 110. The data driver 50 selects the voltage corresponding to the image data from the grayscale voltages, and outputs the selected voltage to the data line of the display panel as the data signal (data voltage).
A scan driver 70 is a circuit which generates a scan signal for driving the scan line of the display panel. Specifically, the scan driver 70 sequentially shifts a signal (enable input/output signal) using a built-in shift register, and outputs a signal obtained by converting the level of the shifted signal to each scan line of the display panel as the scan signal (scan voltage). The scan driver 70 may include a scan address generation circuit and an address decoder. The scan address generation circuit may generate and output a scan address, and the address decoder may decode the scan address to generate the scan signal.
The power supply circuit 90 is a circuit which generates various power supply voltages. Specifically, the power supply circuit 90 increases an input power supply voltage or an internal power supply voltage by a charge-pump method using a boost capacitor and a boost transistor included in a voltage booster circuit provided in the power supply circuit 90. The power supply circuit 90 supplies the resulting voltages to the data driver 50, the scan driver 70, the grayscale voltage generation circuit 110, and the like.
The grayscale voltage generation circuit 110 (gamma correction circuit) is a circuit which generates the grayscale voltage and supplies the grayscale voltage to the data driver 50. Specifically, the grayscale voltage generation circuit 110 may include a ladder resistor circuit which divides the voltage between the high-potential-side power supply and the low-potential-side power supply using resistors, and outputs the grayscale voltages to resistance division nodes. The grayscale voltage generation circuit 110 may also include a grayscale register section into which the grayscale adjustment data is written, a grayscale voltage setting circuit which variably sets (controls) the grayscale voltage output to the resistance division node based on the written grayscale adjustment data, and the like.
A high-speed I/F circuit 200 (serial interface circuit) is a circuit which implements a high-speed serial transfer through a serial bus. Specifically, the high-speed I/F circuit 200 implements a high-speed serial transfer between the integrated circuit device and the host (host device) by current-driving or voltage-driving differential signal lines of the serial bus.
A physical layer circuit 210 (transceiver) is a circuit which receives or transmits data (packet) and a clock signal using differential signals (differential data signals and differential clock signals). Specifically, the physical layer circuit 210 transmits or receives data and the like by current-driving or voltage-driving differential signal lines of the serial bus. The physical layer circuit 210 may include a clock receiver circuit 212, a data receiver circuit 214, a transmitter circuit 216, and the like.
The link controller 230 performs a process of a link layer (or transaction layer) higher than the physical layer. Specifically, the link controller 230 may include a packet analysis circuit 232. When the physical layer circuit 210 has received a packet from the host (host device) through the serial bus, the packet analysis circuit 232 analyzes the received packet. Specifically, the packet analysis circuit 232 separates the header and data of the received packet and extracts the header. b The link controller 230 may include a packet generation circuit 234. The packet generation circuit 234 generates a packet when transmitting a packet to the host through the serial bus. Specifically, the packet generation circuit 234 generates the header of the packet to be transmitted, and assembles the packet by combining the header and data. The packet generation circuit 234 directs the physical layer circuit 210 to transmit the generated packet.
The driver I/F circuit 240 performs an interface process between the high-speed I/F circuit 200 and an internal circuit of the display driver. Specifically, the driver I/F circuit 240 generates host interface signals including an address 0 signal A0, a write signal XWR, a read signal XRD, a parallel data signal PDATA, a chip select signal XCS, and the like, and outputs the generated signals to the internal circuit (host interface circuit 46) of the display driver.
In
The host-side clock transmitter circuit 222 outputs differential clock signals CKP and CKM. The client-side clock receiver circuit 212 differentially amplifies the differential clock signals CKP and CKM, and outputs the resulting clock signal CKC to the circuit in the subsequent stage.
The host-side data transmitter circuit 224 outputs differential data signals DP and DM. The client-side data receiver circuit 214 differentially amplifies the differential data signals DP and DM, and outputs the resulting data DATAC to the circuit in the subsequent stage. In
The configuration of the physical layer circuit 210 is not limited to
The output-side (display panel side) I/F region 12 is a region which serves as an interface between the integrated circuit device 10 and the display panel, and may include pads and elements connected to the pads, such as output transistors and protective elements. Specifically, the output-side I/F region 12 may include output transistors for outputting the data signals to the data lines and outputting the scan signals to the scan lines, for example. When the display panel is a touch panel or the like, the output-side I/F region 12 may include input transistors.
The input-side (host-side) I/F region 14 is a region which serves as an interface between the integrated circuit device 10 and a host (MPU, image processing controller, or baseband engine), and may include pads and elements connected to the pads, such as input (input/output) transistors, output transistors, and protective elements. Specifically, the input-side I/F region 14 may include input transistors for inputting signals (digital signals) from the host, output transistors for outputting signals to the host, and the like.
An output-side I/F region or an input-side I/F region may be provided along the short side SD1 or SD3. Bumps serving as external connection terminals and the like may be provided in the I/F (interface) regions 12 and 14, or may be provided in a region (first to Nth circuit blocks CB1 to CBN) other than the I/F (interface) regions 12 and 14. When providing the bumps in a region other than the I/F regions 12 and 14, the bumps are formed using a small bump technology (e.g. bump technology using a resin core) other than a gold bump technology.
The first to Nth circuit blocks CB1 to CBN may include at least two (or three) different circuit blocks (circuit blocks having different functions). For example, when the integrated circuit device 10 is a display driver, the circuit blocks CB1 to CBN may include at least two of a data driver block, a memory block, a scan driver block, a logic circuit block, a grayscale voltage generation circuit block, and a power supply circuit block. Specifically, the circuit blocks CB1 to CBN may include at least a data driver block and a logic circuit block, and may further include a grayscale voltage generation circuit block. When the integrated circuit device 10 includes a built-in memory, the circuit blocks CB1 to CBN may include a memory block.
In
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The layout arrangement of the integrated circuit device 10 according to this embodiment is not limited to those shown in
According to the arrangement method shown in
In
However, the arrangement method shown in
First, a reduction in chip size is required for an integrated circuit device such as a display driver in order to reduce cost. However, if the chip size is reduced by merely shrinking the integrated circuit device using a microfabrication technology, the size of the integrated circuit device is reduced not only in the short side direction but also in the long side direction. This makes mounting difficult due to the narrow pitch.
Second, the configurations of the memory and the data driver of the display driver are changed depending on the type of display panel (amorphous TFT or low-temperature polysilicon TFT), the number of pixels (QCIF, QVGA, or VGA), the specification of the product, and the like. According to the arrangement method shown in
According to the arrangement method shown in
According to the arrangement method shown in
According to the arrangement method shown in
The ladder resistor circuit 120 divides the voltage between a high-potential-side power supply (power supply voltage) VDDRH and a low-potential-side power supply (power supply voltage) VDDRL using resistors, and outputs one of grayscale voltages V0 to V255 to each of resistance division nodes RT0 to RT255.
The control circuit 140 includes a grayscale register section 142 and an address decoder 144. The grayscale adjustment data (data for adjusting grayscale characteristics) from the logic circuit (logic circuit block) is written into the grayscale register section 142. The address decoder 144 decodes an address signal from the logic circuit, and outputs a register address signal corresponding to the address signal. In the grayscale register section 142, the grayscale adjustment data is written into a register of which the register address signal from the address decoder 144 is active based on a latch signal from the logic circuit.
The grayscale voltage setting circuit 130 (grayscale selector) variably sets (controls) the grayscale voltage output to the resistance division nodes RT0 to RT255 based on the grayscale adjustment data written into the grayscale register section 142. Specifically, the grayscale voltage setting circuit 130 variably sets the grayscale voltage by variably controlling the resistance values of variable resistance circuits included in the ladder resistor circuit 120.
The grayscale voltage generation circuit is not limited to the configuration shown in
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According to the layout method shown in
According to the layout method shown in
In
Specifically, it is desirable to set grayscale characteristics (gamma characteristics) optimum for the type of display panel in order to increase the display quality. When enabling the grayscale characteristics to be adjusted corresponding to the characteristics of various display panels, the amount of grayscale adjustment data increases. Therefore, when parallely writing a large amount of grayscale adjustment data into the grayscale register section 142 instead of time division, the number of bits of the transfer line increases, whereby the number of transfer lines increases. According to the layout method in which the data driver blocks DB1, DB2, . . . are disposed between the grayscale voltage generation circuit block GB and the logic circuit block LB, the number of global lines for controlling the data driver supplying the power supply voltage, and supplying the grayscale voltage is limited if the number of transfer lines increases. As a result, the width of the integrated circuit device in the direction D2 increases by the number of grayscale adjustment data transfer lines, thereby making it difficult to realize a narrow chip.
In this case, the grayscale voltage generation circuit block GB and the logic circuit block LB may be disposed adjacently, and the grayscale adjustment data may be transferred using the local lines connecting the grayscale voltage generation circuit block GB and the logic circuit block LB. According to this method, the grayscale voltage generation circuit block GB and the logic circuit block LB are disposed on the right or left of the data driver block DB1, DB2, . . . . Therefore, the free space for disposing the scan driver pads and the like is formed on the right or left of the data driver block DB1, DB2, . . . , whereby the layout efficiency decreases.
On the other hand, the number of grayscale transfer lines GTL can be reduced by transferring the grayscale adjustment data by time division, as shown in FIG. 18B. This provides a space for other global lines, whereby the width of the integrated circuit device in the direction D2 can be reduced. As a result, a narrow chip can be realized. Moreover, the free space for disposing the scan driver pads and the like is equally formed on the right or left of the data driver block DB1, DB2, . . . , whereby the layout efficiency can be increased.
A specific grayscale adjustment data transfer method is described below. In
As shown in
In the data valid period TA, the logic circuit block LB outputs the address signals A3 to A0 corresponding to the register addresses of registers R0 to RI of the grayscale register section 142 and the data signals D7 to D0 corresponding to the grayscale adjustment data written into the registers R0 to RI. The logic circuit block LB also outputs the latch signal LAT for capturing the data signals D7 to D0. In the grayscale register section 142, the grayscale adjustment data of the data signals D7 to D0 is written into one of the registers R0 to RI specified by the register address of the address signals A3 to A0 based on the latch signal LAT (falling edge of the latch signal LAT). This causes grayscale adjustment data DAR0, DAR1, DAR2, . . . to be written into the grayscale register section 142 by time division. The numbers of bits of the address signals and the data signals are not limited to four and eight, but may be arbitrary.
Specifically, a processing section (CPU or MPU) provided outside the integrated circuit device issues a grayscale adjustment command, and outputs a parameter as the grayscale adjustment data to the integrated circuit device. The logic circuit block LB which has received the parameter writes the grayscale adjustment data corresponding to the parameter into the registers R0 to RI of the grayscale register section 142 using the address signals A3 to A0 and the data signals D7 to D0. This enables the grayscale characteristics to be adjusted from the outside, whereby the display quality of the display panel can be increased.
When an electrostatic voltage is applied to the display panel or the like in an electrostatic discharge immunity test (ESD immunity test) or the like, noise may be superimposed on the latch signal LAT in the period TB shown in
In the register map of the grayscale register section 142 shown in
According to this configuration, even if noise is superimposed on the latch signal LAT or the like in the period TB, since the register is not mapped on the register address (Fh), wrong grayscale adjustment data is not written into the register. This prevents a situation in which the display state of the display panel becomes abnormal due to application of an electrostatic voltage, whereby an integrated circuit device and an electronic instrument with high ESD immunity can be provided.
The register address of the grayscale register section 142 onto which the register is not mapped is not limited to (Fh)=(1111), differing from
In order to reduce the width of the integrated circuit device in the direction D2, it is necessary to efficiently provide the signal lines and the power supply lines between the circuit blocks disposed along the direction D1. Therefore, it is desirable to provide the signal lines and the power supply lines between the circuit blocks using a global wiring method.
According to the global wiring method, local lines formed of interconnect layers (e.g. first to fourth aluminum interconnect layers ALA, ALB, ALC, and ALD) located under an Ith layer (I is an integer equal to or larger than three) are provided between the adjacent circuit blocks among the first to Nth circuit blocks CB1 to CBN. Global lines formed of an interconnect layer (e.g. fifth aluminum interconnect layer ALE) located over the Ith layer are provided between the nonadjacent circuit blocks among the first to Nth circuit blocks CB1 to CBN to pass over the circuit block disposed between the nonadjacent circuit blocks along the direction D1.
In
More specifically, repeater blocks RP1 to RP3 are disposed in
For example, when supplying the write data signal, the address signal, and the memory control signal from the logic circuit block LB to the memory blocks MB1 to MB3 using the memory global line GLM, the rising waveforms and the falling waveforms of these signals are rounded if these signals are not buffered. As a result, the time required for writing data into the memory blocks MB1 to MB3 may be increased, or a write error may occur.
On the other hand, when the repeater blocks RP1 to RP3 shown in
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It is necessary to supply the grayscale voltage from the grayscale voltage generation circuit block GB to the data drivers DR1 to DR3. Therefore, the grayscale global line GLG is provided along the direction D1.
The address signal, the memory control signal, and the like are supplied to the row address decoders RD1 to RD3 through the memory global line GLM. Therefore, it is desirable to provide the memory global line GLM near the row address decoders RD1 to RD3.
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A time division transfer of the power supply adjustment data may be implemented using a method similar to the time division transfer method for the grayscale adjustment data described with reference to
Suppose that the display panel is a QVGA panel in which the number of pixels in the vertical scan direction (data line direction) is VPN=320 and the number of pixels in the horizontal scan direction (scan line direction) is HPN=240, as shown in
In
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On the other hand, when the number of bits of image data read in units of horizontal scan periods increases, it is necessary to increase the number of memory cells (sense amplifiers) arranged along the direction D2. As a result, the width W of the integrated circuit device in the direction D2 increases, whereby the width of the chip cannot be reduced. Moreover, since the length of the wordline WL increases, a signal delay of the wordline WL occurs.
In order to solve such a problem, it is desirable to employ a method in which the image data stored in the memory blocks MB1 to MB4 is read from the memory blocks MB1 to MB4 into the data driver blocks DB1 to DB4 a plurality of times (RN times) in one horizontal scan period.
In
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According to the method shown in
Readings in one horizontal scan period may be achieved using a first method in which the row address decoder (wordline select circuit) selects different wordlines in each memory block in one horizontal scan period or a second method in which the row address decoder (wordline select circuit) selects a single wordline in each memory block a plurality of times in one horizontal scan period. Alternatively, readings in one horizontal scan period may be achieved by combining the first method and the second method.
In
When the wordline WL1a of the memory block has been selected and the first image data has been read from the memory block, as indicated by A1 in
When the wordline WL1b of the memory block has been selected and the second image data has been read from the memory block, as indicated by A2 in
Each of the data drivers DRa and DRb outputs the data signals of 30 data lines corresponding to 30 pixels as described above, whereby the data signals of 60 data lines corresponding to 60 pixels are output in total.
A situation in which the width W of the integrated circuit device in the direction D2 increases due to an increase in the scale of the data driver can be prevented by disposing (stacking) the data drivers DRa and DRb along the direction D1, as shown in
In
The number of subpixels of the display panel in the horizontal scan direction is referred to as HPNS, and the degree of multiplexing of the multiplexer of each driver cell is referred to as NDM. In this case, the number Q of driver cells disposed along the direction D2 may be expressed as Q=HPNS/(DBN×IN×NDM). In
When the width (pitch) of the driver cells in the direction D2 is referred to as WD and the width of the peripheral circuit section (e.g. buffer circuit and wiring region) of the data driver block in the direction D2 is referred to as WPCB, the width WB (maximum width) of the first to Nth circuit blocks CB1 to CBN in the direction D2 may be expressed as Q×WD≦WB<(Q+1)×WD+WPCB. When the width of the peripheral circuit section (e.g. row address decoder RD and wiring region) of the memory block in the direction D2 is referred to as WPC, the width WB (maximum width) of the first to Nth circuit blocks CB1 to CBN in the direction D2 may be expressed as Q×WD≦WB<(Q+1)×WD+WPC.
When the number of pixels of the display panel in the horizontal scan direction is referred to as HPN, the number of bits of image data of one pixel is referred to as PDB, the number of memory blocks is referred to as MBN (=DBN), and the read count of image data from the memory block in one horizontal scan period is referred to as RN. In this case, the number of sense amplifiers (sense amplifiers which output one bit of image data) arranged in the sense amplifier block SAB along the direction D2 may be expressed as P=(HPN×PDB)/(MBN×RN). In
The number of subpixels of the display panel in the horizontal scan direction is referred to as HPNS, and the degree of multiplexing of the multiplexer of each driver cell is referred to as NDM. In this case, the number P of sense amplifiers disposed along the direction D2 may be expressed as P=(HPNS×PDB)/(MBN×RN×NDM). In
When the width (pitch) of each sense amplifier of the sense amplifier block SAB in the direction D2 is referred to as WS, the width WSAB of the sense amplifier block SAB (memory block) in the direction D2 may be expressed as WSAB=P×WS. When the width of the peripheral circuit section of the memory block in the direction D2 is referred to as WPC, the width WB (maximum width) of the circuit blocks CB1 to CBN in the direction D2 may also be expressed as P×WS≦WB<(P+PDB)×WS+WPC.
In
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Although only some embodiments of the invention have been described in detail above, those skilled in the art would readily appreciate that many modifications are possible in the embodiments without materially departing from the novel teachings and advantages of the invention. Accordingly, such modifications are intended to be included within the scope of the invention. Any term (e.g., output-side I/F region, input-side I/F region, and liquid crystal element) cited with a different term (e.g., first interface region, second interface region, and electro-optical element) having a broader meaning or the same meaning at least once in the specification and the drawings can be replaced by the different term in any place in the specification and the drawings. The scan output line wiring method described with reference to
| Number | Date | Country | Kind |
|---|---|---|---|
| 2006-315705 | Nov 2006 | JP | national |
| 2006-315706 | Nov 2006 | JP | national |
