Patent Grant
8547773
Japanese Patent Application No. 2005-192479, filed on Jun. 30, 2005, Japanese Patent Application No. 2005-253389, filed on Sep. 1, 2005, and Japanese Patent Application No. 2006-34499, filed on Feb. 10, 2006, are hereby incorporated by reference in their entirety.
The present invention relates to an integrated circuit device and an electronic instrument.
A display driver (LCD driver) is an example of an integrated circuit device which drives a display panel such as a liquid crystal panel (JP-A-2001-222249). A reduction in the chip size is required for the display driver in order to reduce cost.
However, the size of the display panel incorporated in a portable telephone or the like is almost constant. Therefore, if the chip size is reduced by merely shrinking the integrated circuit device as the display driver by using a microfabrication technology, it becomes difficult to mount the integrated circuit device.
A first aspect of the invention relates to an integrated circuit device comprising:
at least one data driver block for driving data lines;
a plurality of control transistors, each of the control transistors being provided corresponding to each output line of the data driver block and controlled by using a common control signal; and
a pad arrangement region in which data driver pads for electrically connecting the data lines and the output lines of the data driver block are disposed;
the control transistors being disposed in the pad arrangement region.
A second aspect of the invention relates to an integrated circuit device comprising:
first to Nth circuit blocks (N is an integer of two or more) disposed along a first direction when a direction from a first side which is a short side of the integrated circuit device toward a third side opposite to the first side is a first direction and a direction from a second side which is a long side of the integrated circuit device toward a fourth side opposite to the second side is a second direction;
a first interface region which is disposed along the fourth side on the second direction side of the first to Nth circuit blocks and serves as a pad arrangement region;
a second interface region which is disposed along the second side and on a fourth direction side of the first to Nth circuit blocks and serves as a pad arrangement region, the fourth direction being opposite to the second direction; and
the first to Nth circuit blocks including at least one data driver block for driving data lines,
data driver pads for electrically connecting the data lines and output lines of the data driver block, and a plurality of control transistors, each of the control transistors being provided corresponding to each output line of the data driver block and controlled using a common control signal, being disposed in the first interface region.
A third aspect of the invention relates to an electronic instrument comprising:
the above integrated circuit device; and
a display panel driven by the integrated circuit device.
The invention may provide an integrated circuit device which can reduce the circuit area, and an electronic instrument including the same.
One embodiment of the invention relates to an integrated circuit device comprising:
at least one data driver block for driving data lines;
a plurality of control transistors, each of the control transistors being provided corresponding to each output line of the data driver block and controlled by using a common control signal; and
a pad arrangement region in which data driver pads for electrically connecting the data lines and the output lines of the data driver block are disposed;
the control transistors being disposed in the pad arrangement region.
According to this embodiment, each control transistor is provided corresponding to each output line of the data driver block, and each control transistor is controlled using the common control signal. The control transistors are disposed in the pad arrangement region. Since the control transistors are controlled using the common control signal, the wiring region is not increased to a large extent even if the control transistors are disposed in the pad arrangement region. Therefore, the control transistors can be disposed by effectively utilizing the pad arrangement region, whereby the area of the integrated circuit device can be reduced.
In the integrated circuit device according to this embodiment, the common control signal may be input to a gate of the control transistor, and the output line of the data driver block may be connected with a drain of the control transistor.
The potential of the output line of the data driver block and the like can be controlled using the common control signal by using such a control transistor. Moreover, when such a control transistor is disposed in the pad arrangement region, an increase in the area of the integrated circuit device can be minimized.
In the integrated circuit device according to this embodiment, a common potential may be supplied to a source of the control transistor, and the output line of the data driver block may be set at the common potential when the common control signal is active.
The output line of the data driver block can be set at the common potential using the common control signal by using such a control transistor. Moreover, when such a control transistor is disposed in the pad arrangement region, an increase in the area of the integrated circuit device can be minimized.
In the integrated circuit device according to this embodiment, the control transistor may be a discharge transistor which sets the output line of the data driver block at a ground potential when a discharge signal which is the common control signal has become active.
A problem caused by residual electric charge in the data line and the like can be prevented while reducing the area of the integrated circuit device by disposing such a discharge transistor in the pad arrangement region as the control transistor.
In the integrated circuit device according to this embodiment, the control transistor may be disposed in a lower layer of the data driver pad so that the control transistor at least partially overlaps the data driver pad.
This allows the control transistors to be disposed by effectively utilizing the region in the lower layer of the pads, whereby the area of the integrated circuit device can be reduced.
The integrated circuit device according to this embodiment may comprise: an operational amplifier for performing impedance conversion of a data signal output to the data line; wherein transistors forming a differential section and a driver section of the operational amplifier may be disposed in the data driver block.
This prevents a situation in which the wiring region is unnecessarily increased.
The integrated circuit device according to this embodiment may comprise: an electrostatic protection element connected with the output line of the data driver block and disposed in the pad arrangement region; wherein, when a direction in which the data lines are arranged is a first direction and a direction perpendicular to the first direction is a second direction, the control transistor may be disposed on the second direction side of the data driver block, and the electrostatic protection element may be disposed on the second direction side of the control transistor.
This reduces the area of the integrated circuit device while preventing electrostatic destruction of the control transistor.
In the integrated circuit device according to this embodiment, the pad arrangement region may include a plurality of arrangement areas arranged along the first direction; and K (K is an integer of two or more) of the data driver pads arranged along the second direction and K of the electrostatic protection elements each of which is connected with each of the K data driver pads may be disposed in each of the arrangement areas.
This allows the data driver pads and the electrostatic protection elements to be efficiently disposed in each arrangement area corresponding to the pad pitch.
In the integrated circuit device according to this embodiment, the K data driver pads arranged along the second direction may be disposed so that center positions of the data driver pads are displaced from each other in the first direction.
This allows a large number of data driver pads to be disposed along the first direction.
In the integrated circuit device according to this embodiment, a first electrostatic protection element of the K electrostatic protection elements may include: a first diode provided between a high-potential-side power supply and a first output line of the data driver block; and a second diode provided between a low-potential-side power supply and the first output line of the data driver block; a second electrostatic protection element of the K electrostatic protection elements may include: a third diode provided between the high-potential-side power supply and a second output line of the data driver block; and a fourth diode provided between the low-potential-side power supply and the second output line of the data driver block; and the first, second, third, and fourth diodes may be disposed along the second direction in each of the arrangement areas.
The width of the arrangement area in the first direction can be reduced by disposing the first to fourth diodes in this manner, whereby a narrow pad pitch can be dealt with.
In the integrated circuit device according to this embodiment, the first and third diodes may be formed in a first well region; the second and fourth diodes may be formed in a second well region; and the first and second well regions may be isolated in the second direction.
This reduces the width of the arrangement area in the first direction, whereby a narrow pad pitch can be dealt with.
In the integrated circuit device according to this embodiment, the electrostatic protection element may include a diffusion region of which a long side extends along the first direction and a short side extends along the second direction.
This makes it possible to increase the width of a connection line connected to the pad, whereby the wiring impedance can be reduced.
The integrated circuit device according to this embodiment may comprise: a power supply protection circuit provided between a high-potential-side power supply and a low-potential-side power supply; wherein the power supply protection circuit may be disposed on the second direction side of the electrostatic protection element.
This allows the power supply protection circuit to be efficiently arranged even when the power supply protection circuit has a large circuit scale.
The integrated circuit device according to this embodiment may comprise: a memory block which stores image data used by the data driver block; and a pad block in which the data driver pads and the control transistors are disposed; wherein the data driver block, the memory block, and the pad block may be integrated into a macrocell as a driver macrocell; wherein the data driver block and the memory block may be disposed along a first direction; and wherein the pad block may be disposed on the second direction side of the data driver block and the memory block, the second direction being perpendicular to the first direction.
By integrating the data driver block, the pad block, and the like into a macrocell, a completed macrocell formed by routing the output lines of the data driver block to the pads by a manual layout can be used as the driver macrocell, for example. Therefore, the output line wiring region can be reduced, whereby the area of the integrated circuit device can be reduced.
In the integrated circuit device according to this embodiment, the data driver block may include a plurality of subpixel driver cells, each of the subpixel driver cells outputting a data signal corresponding to image data of one subpixel, and the subpixel driver cells may be disposed in the data driver block along a first direction and a second direction perpendicular to the first direction.
A layout can be flexibly designed corresponding to the specification of the data driver by disposing the subpixel driver cells in a matrix.
Another embodiment of the invention relates to an integrated circuit device comprising:
first to Nth circuit blocks (N is an integer of two or more) disposed along a first direction when a direction from a first side which is a short side of the integrated circuit device toward a third side opposite to the first side is a first direction and a direction from a second side which is a long side of the integrated circuit device toward a fourth side opposite to the second side is a second direction;
a first interface region which is disposed along the fourth side on the second direction side of the first to Nth circuit blocks and serves as a pad arrangement region;
a second interface region which is disposed along the second side and on a fourth direction side of the first to Nth circuit blocks and serves as a pad arrangement region, the fourth direction being opposite to the second direction; and
the first to Nth circuit blocks including at least one data driver block for driving data lines,
data driver pads for electrically connecting the data lines and output lines of the data driver block, and a plurality of control transistors, each of the control transistors being provided corresponding to each output line of the data driver block and controlled using a common control signal, being disposed in the first interface region.
According to this embodiment, since the first to Nth circuit blocks are disposed along the first direction, the width of the integrated circuit device in the second direction can be reduced, whereby a narrow integrated circuit device can be provided. According to this embodiment, since the control transistors can be disposed by effectively utilizing the pad arrangement region, the area of the integrated circuit device can be further reduced in the second direction.
A further embodiment of the invention relates to an electronic instrument comprising:
the above integrated circuit device: and
a display panel driven by the integrated circuit device.
These embodiments of the invention will be described in detail below. Note that the embodiments described below do not in any way limit the scope of the invention laid out in the claims herein. In addition, not all of the elements of the embodiments described below should be taken as essential requirements of the invention.
Image data supplied from a host is written into the memory block MB. The data driver block DB converts the digital image data written into the memory block MB into an analog data voltage, and drives data lines of a display panel. In
However, the comparative example shown in
First, a reduction in the chip size is required for an integrated circuit device such as a display driver in order to reduce cost. However, if the chip size is reduced by merely shrinking the integrated circuit device 500 by using a microfabrication technology, the size of the integrated circuit device 500 is reduced not only in the short side direction but also in the long side direction. Therefore, it becomes difficult to mount the integrated circuit device 500 as shown in
Second, the configurations of the memory and the data driver of the display driver are changed corresponding to the type of display panel (amorphous TFT or low-temperature polysilicon TFT), the number of pixels (QCIF, QVGA, or VGA), the specification of the product, and the like. Therefore, in the comparative example shown in
If the layout of the memory and the data driver is changed so that the pad pitch coincides with the cell pitch in order to avoid such a problem, the development period is increased, whereby cost is increased. Specifically, since the circuit configuration and the layout of each circuit block are individually designed and the pitch is adjusted thereafter in the comparative example shown in
As shown in
The integrated circuit device 10 includes an output-side I/F region 12 (first interface region in a broad sense) provided along the side SD4 and on the D2 side of the first to Nth circuit blocks CB1 to CBN. The integrated circuit device 10 includes an input-side I/F region 14 (second interface region in a broad sense) provided along the side SD2 and on the D4 side of the first to Nth circuit blocks CB1 to CBN. In more detail, the output-side I/F region 12 (first I/O region) is disposed on the D2 side of the circuit blocks CB1 to CBN without other circuit blocks interposed therebetween, for example. The input-side I/F region 14 (second I/O region) is disposed on the D4 side of the circuit blocks CB1 to CBN without other circuit blocks interposed therebetween, for example. Specifically, only one circuit block (data driver block) exists in the direction D2 at least in the area in which the data driver block exists. When the integrated circuit device 10 is used as an intellectual property (IP) core and incorporated in another integrated circuit device, the integrated circuit device 10 may be configured to exclude at least one of the I/F regions 12 and 14.
The output-side (display panel side) I/F region 12 is a region which serves as an interface between the integrated circuit device 10 and the display panel, and includes pads and various elements such as output transistors and protective elements connected with the pads. In more detail, the output-side I/F region 12 includes output transistors for outputting data signals to data lines and scan signals to scan lines, for example. When the display panel is a touch panel, the output-side I/F region 12 may include input transistors.
The input-side I/F region 14 is a region which serves as an interface between the integrated circuit device 10 and a host (MPU, image processing controller, or baseband engine), and may include pads and various elements connected with the pads, such as input (input-output) transistors, output transistors, and protective elements. In more detail, the input-side I/F region 14 includes input transistors for inputting signals (digital signals) from the host, output transistors for outputting signals to the host, and the like.
An output-side or input-side I/F region may be provided along the short side SD1 or SD3. Bumps which serve as external connection terminals may be provided in the I/F (interface) regions 12 and 14, or may be provided in other regions (first to Nth circuit blocks CB1 to CBN). When providing the bumps in the region other than the I/F regions 12 and 14, the bumps are formed by using a small bump technology (e.g. bump technology using resin core) other than a gold bump technology.
The first to Nth circuit blocks CB1 to CBN may include at least two (or three) different circuit blocks (circuit blocks having different functions). Taking an example in which the integrated circuit device 10 is a display driver, the circuit blocks CB1 to CBN may include at least two of a data driver block, a memory block, a scan driver block, a logic circuit block, a grayscale voltage generation circuit block, and a power supply circuit block. In more detail, the circuit blocks CB1 to CBN may include at least a data driver block and a logic circuit block, and may further include a grayscale voltage generation circuit block. When the integrated circuit device 10 includes a built-in memory, the circuit blocks CB1 to CBN may further include a memory block.
In
In
In
The layout arrangement shown in
The layout arrangement of the integrated circuit device 10 according to this embodiment is not limited to those shown in
In this embodiment, as shown in
The widths W1, WB, and W2 shown in
The widths of the circuit blocks CB1 to CBN in the direction D2 may be identical, for example. In this case, it suffices that the width of each circuit block be substantially identical, and the width of each circuit block may differ in the range of several to 20 μm (several tens of microns), for example. When a circuit block with a different width exists in the circuit blocks CB1 to CBN, the width WB may be the maximum width of the circuit blocks CB1 to CBN. In this case, the maximum width may be the width of the data driver block in the direction D2, for example. In the case where the integrated circuit device includes a memory, the maximum width may be the width of the memory block in the direction D2. A vacant region having a width of about 20 to 30 μm may be provided between the circuit blocks CB1 to CBN and the I/F regions 12 and 14, for example.
In this embodiment, a pad of which the number of stages in the direction D2 is one or more may be disposed in the output-side I/F region 12. Therefore, the width W1 of the output-side I/F region 12 in the direction D2 may be set at “0.13 mm≦W1≦0.4 mm” taking the pad width (e.g. 0.1 mm) and the pad pitch into consideration. Since a pad of which the number of stages in the direction D2 is one can be disposed in the input-side I/F region 14, the width W2 of the input-side I/F region 14 may be set at “0.1 mm≦W2≦0.2 mm”. In order to realize a slim integrated circuit device, interconnects for logic signals from the logic circuit block, grayscale voltage signals from the grayscale voltage generation circuit block, and a power supply must be formed on the circuit blocks CB1 to CBN by using global interconnects. The total width of these interconnects is about 0.8 to 0.9 mm, for example. Therefore, the widths WB of the circuit blocks CB1 to CBN may be set at “0.65 mm≦WB≦1.2 mm” taking the total width of these interconnects into consideration.
Since “0.65 mm≦WB≦1.2 mm” is satisfied even if W1=0.4 mm and W2=0.2 mm, WB>W1+W2 is satisfied. When the widths W1, WB, and W2 are minimum values, W1=0.13 mm, WB=0.65 mm, and W2=0.1 mm so that the width W of the integrated circuit device is about 0.88 mm. Therefore, “W=0.88 mm<2×WB=1.3 mm” is satisfied. When the widths W1, WB, and W2 are maximum values, W1=0.4 mm, WB=1.2 mm, and W2=0.2 mm so that the width W of the integrated circuit device is about 1.8 mm. Therefore, “W=1.8 mm<2×WB=2.4 mm” is satisfied. Therefore, the relational equation “W<2×WB” is satisfied so that a slim integrated circuit device is realized.
In the comparative example shown in
In this embodiment, the circuit blocks CB1 to CBN are disposed along the direction D1 as shown in
In this embodiment, since the circuit blocks CB1 to CBN are disposed along the direction D1, it is possible to easily deal with a change in the product specifications and the like. Specifically, since product of various specifications can be designed by using a common platform, the design efficiency can be increased. For example, when the number of pixels or the number of grayscales of the display panel is increased or decreased in
In this embodiment, the widths (heights) of the circuit blocks CB1 to CBN in the direction D2 can be uniformly adjusted to the width (height) of the data driver block or the memory block, for example. Since it is possible to deal with an increase or decrease in the number of transistors of each circuit block by increasing or decreasing the length of each circuit block in the direction D1, the design efficiency can be further increased. For example, when the number of transistors is increased or decreased in
As a second comparative example, a narrow data driver block may be disposed in the direction D1, and other circuit blocks such as the memory block may be disposed along the direction D1 on the D4 side of the data driver block, for example. However, in the second comparative example, since the data driver block having a large width lies between other circuit blocks such as the memory block and the output-side I/F region, the width W of the integrated circuit device in the direction D2 is increased, so that it is difficult to realize a slim chip. Moreover, an additional interconnect region is formed between the data driver block and the memory block, whereby the width W is further increased. Furthermore, when the configuration of the data driver block or the memory block is changed, the pitch difference described with reference to
As a third comparative example of this embodiment, only circuit blocks (e.g. data driver blocks) having the same function may be divided and arranged in the direction D1. However, since the integrated circuit device can be provided with only a single function (e.g. function of the data driver) in the third comparative example, development of various products cannot be realized. In this embodiment, the circuit blocks CB1 to CBN include circuit blocks having at least two different functions. Therefore, various integrated circuit devices corresponding to various types of display panels can be provided as shown in
A logic circuit 40 (e.g. automatic placement and routing circuit) generates a control signal for controlling display timing, a control signal for controlling data processing timing, and the like. The logic circuit 40 may be formed by automatic placement and routing such as a gate array (G/A). A control circuit 42 generates various control signals and controls the entire device. In more detail, the control circuit 42 outputs grayscale characteristic (γ-characteristic) adjustment data (γ-correction data) to a grayscale voltage generation circuit 110 and controls voltage generation of a power supply circuit 90. The control circuit 42 controls write/read processing for the memory using the row address decoder 24, the column address decoder 26, and the write/read circuit 28. A display timing control circuit 44 generates various control signals for controlling display timing, and controls reading of image data from the memory into the display panel. A host (MPU) interface circuit 46 realizes a host interface which accesses the memory by generating an internal pulse each time accessed by the host. An RGB interface circuit 48 realizes an RGB interface which writes motion picture RGB data into the memory based on a dot clock signal. The integrated circuit device 10 may be configured to include only one of the host interface circuit 46 and the RGB interface circuit 48.
In
The data driver 50 is a circuit for driving a data line of the display panel.
A scan driver 70 is a circuit for driving a scan line of the display panel.
The power supply circuit 90 is a circuit which generates various power supply voltages.
The grayscale voltage generation circuit 110 (γ-correction circuit) is a circuit which generates grayscale voltages.
When R, G, and B data signals are multiplexed and supplied to a low-temperature polysilicon TFT display driver or the like (
In this embodiment, in order reduce the width of the integrated circuit device in the direction D2 to realize a narrow chip, elements which are generally disposed in the circuit block are disposed in the pad arrangement regions such as the output-side I/F region and the input-side I/F region. The data driver occupies a large area in the integrated circuit device. Therefore, the area of the integrated circuit device can be reduced by disposing the transistors of the data driver in the pad arrangement region.
On the other hand, the number of output lines of the data driver is generally very large. Therefore, when the transistors forming the operational amplifiers included in the data driver are disposed in the pad arrangement region, a number of signal lines must be provided in the pad arrangement region, whereby the area of the wiring region is increased. As a result, the width of the integrated circuit device in the direction D2 cannot be reduced.
In this embodiment, control transistors of the data driver controlled by using a control signal common to the data drivers are disposed in the pad arrangement region.
In
The control transistors TC1, TC2, TC3, TC4, . . . are respectively provided corresponding to output lines QL1, QL2, QL3, QL4, . . . of the data driver block DB, and controlled by using a common control signal CTL. The control transistor may be either an N-type (first conductivity type in a broad sense) transistor or a P-type (second conductivity type in a broad sense) transistor. Or, a circuit formed by combining an N-type transistor and a P-type transistor, such as a transfer gate transistor, may be used.
Data driver pads (pad metals) for electrically connecting the data lines of the display panel and the output line QL1, QL2, QL3, QL4, . . . of the data driver block DB are disposed in the pad arrangement region. A pad other than the data driver pad or a dummy pad may be disposed in the pad arrangement region. Or, an electrostatic protection element or a power supply protection circuit described later may be disposed in the pad arrangement region. The pad arrangement region is a region between the side (boundary or edge) of the circuit block and the side (e.g. second or fourth side) of the integrated circuit device, such as the output-side I/F region 12 or the input-side I/F region 14 shown in
In this embodiment, the control transistors TC1, TC2, TC3, . . . are disposed in the pad arrangement region, as shown in
For example, an output transistor forming the driver section of the operational amplifier is controlled by inputting an input signal which differs for each data driver (subpixel driver cell) to its gate. Therefore, when such an output transistor is disposed in the pad arrangement region, the width of the integrated circuit device may be increased-in the direction D2 due to the input signal wiring region.
On the other hand, the control transistors TC1, TC2, TC3, TC4, . . . are controlled by using the common control signal CTL common to the data drivers (subpixel driver cells) instead of a signal which differs for each data driver. Therefore, the area of the wiring region is not increased to a large extent even if the control transistors TC1, TC2, TC3, TC4, . . . are disposed in the pad arrangement region, whereby the width of the integrated circuit device can be reduced in the direction D2.
The operational amplifier OP1 performs impedance conversion of the data signal output to the data line. Specifically, the operational amplifier OP1 performs impedance conversion of an output signal from a D/A converter DAC1 in the preceding stage and outputs the data signal to the data line to drive the data line.
The switch circuit SWA1 is inserted in series between the pad P1 connected with the output line QL1 of the output section SSQ1 and the operational amplifier OP1. The switch circuit SWB1 is inserted in series between the pad P1 and the input (output of the D/A converter DAC1) of the operational amplifier OP1. The switch circuits SWA1 and SWB1 may be formed using a transfer gate including an N-type transistor and a P-type transistor. The switch circuits SWA1 and SWB1 are ON/OFF controlled based on an enable signal from the logic circuit block. In more detail, the switch circuit SWA1 is turned ON (conducting state) and the switch circuit SWB1 is turned OFF (non-conducting state) in the first period of one horizontal scan period. This allows the data line to be driven by the operational amplifier OP1 in the first period. In the second period subsequent to the first period, the switch circuit SWA1 is turned OFF and the switch circuit SWB1 is turned ON, whereby the output from the D/A converter DAC1 is directly output to the data line as the data signal. The operating current of the operational amplifier OP1 is terminated or limited in the second period. This reduces the operation period of the operational amplifier OP1, whereby power consumption can be reduced.
The transistors TDN1 and TDP1 are eight-color display mode transistors. In the eight-color display mode, the gates of the transistors TDN1 and TDP1 are controlled using control signals BEN1 and XBEN1. In more detail, the gates of the transistors TDN1 and TDP1 are controlled using the control signals BEN1 and XBEN1 generated based on the most significant bit of image data. In the normal operation mode, the control signals BEN1 and XBEN1 are respectively set at the L level and the H level, whereby the drains of the transistors TDN1 and TDP1 are set in a high impedance state.
The control transistor TC1 is a discharge transistor. Specifically, the control transistor TC1 sets the output line QL1 of the output section SSQ1 (data driver block) at a potential VSS (ground potential) when the common control signal CTL1 (discharge signal) has become active to discharge an electric charge in the data line (display panel) connected with the pad P1 to the VSS side. The common control signal CTL1 (discharge signal) is input to the gate of the control transistor TC1, and the output line QL1 of the output section SSQ1 (data driver block) is connected with the drain of the control transistor TC1.
The discharge control signal CTL1 may be generated based on an initialization signal (reset signal) and a detection signal from a voltage level drop detection circuit included in the data driver. Specifically, the control signal CTL1 becomes active when a high-potential-side power supply voltage has decreased to a voltage equal to or less than a given threshold voltage or when the initialization signal has become active. This allows an electric charge stored in the data line connected with the pad P1 to be discharged. This prevents a situation in which image persistence occurs in the display panel due to residual electric charge in the data line when an unexpected decrease in the power supply voltage occurs due to initialization or removal of a built-in battery.
In this embodiment, the control transistors TC1 and TC2 as shown in
When a transistor is disposed in the lower layer of a pad, the threshold voltage of the transistor may change due to stress applied when bonding a bonding wire or mounting using a bump. Moreover, the capacitance of an interlayer dielectric of the transistor may change from the designed capacitance. Therefore, the characteristics of the transistor on a wafer may change after mounting. Therefore, transistors for outputting an analog voltage, such as transistors (analog circuits) forming the differential sections (differential stage) and the driver sections (driver stage) of the operational amplifiers OP1 and OP2, are disposed in the data driver block instead of disposing the transistors in the lower layer of the pads.
On the other hand, transistors which function as digital switches and output a digital voltage, such as the control transistors TC1 and TC2, are disposed in the lower layer of the pads. This prevents the above problem and reduces the layout area of the integrated circuit device, whereby the width of the integrated circuit device in the direction D2 can be further reduced. For example, since the number of output lines of the data driver is very large, a significant area reduction effect can be obtained.
The gates of the output transistors forming the driver sections of the operational amplifiers OP1 and OP2 are controlled using gate control signals which differ between the output sections SSQ1 and SSQ2. Therefore, when disposing these output transistors in the pad arrangement region, it is necessary to provide gate control signal lines in the same number as the data lines in the pad arrangement region, whereby the area of the wiring region is increased.
On the other hand, the control transistors TC1 and TC2 shown in
In
In this embodiment, the control transistors TCN1, TCP1, TCN2, and TCP2 are also disposed in the pad arrangement region. In more detail, the control transistors TCN1, TCP1, TCN2, and TCP2 are disposed in the lower layer of (under) the pads P1 and P2 (pad metals) so that the control transistors TCN1, TCP1, TCN2, and TCP2 at least partially overlap the pads P1 and P2. Note that some of the control transistors TC1, TC2, TCN1, TCP1, TCN2, and TCP2 may not be disposed in the lower layer of the pads. Or, a modification may be made in which other transistors of the output sections SSQ1 and SSQ2 are disposed in the pad arrangement region.
In
In this embodiment, the electrostatic protection elements ESD1 and ESD2 are also disposed in the pad arrangement region. In more detail, the electrostatic protection elements ESD1 and ESD2 are disposed in the lower layer of the pads P1 and P2 so that the electrostatic protection elements ESD1 and ESD2 at least partially overlap the pads P1 and P2. This further reduces the width of the integrated circuit device in the direction D2.
In
In
According to this arrangement, since the control transistors TC1 to TCP2 are disposed immediately close to the data driver block, the output lines from the data driver block can be connected with the control transistors TC1 to TCP2 along a short path, whereby the layout efficiency and wiring efficiency can be increased. According to this arrangement, the electrostatic protection elements ESD1 and ESD2 are disposed close to the pads P1 and P2 in comparison with the control transistors TC1 to TCP2. Therefore, when a electrostatic voltage is applied to the pads P1 and P2, static electricity is discharged by the electrostatic protection elements ESD1 and ESD2 and applied to the control transistors TC1 to TCP2 after a time delay. This prevents a situation in which the control transistors TC1 to TCP2 are destroyed due to static electricity.
In this case, the electrostatic withstand voltage may be increased by increasing the drain area of the control transistors TC1 to TCP2. However, this method increases the width of the pad arrangement region in the direction D2, whereby the width of the integrated circuit device is increased in the direction D2.
According to the arrangement shown in
In
In
A large number of pads can be disposed along the direction D1 by disposing the pads P1 and P2 in a staggered arrangement, whereby a large number of data signals from the data driver block can be output to the data lines through the pads.
When the pad pitch is decreased by disposing the pads in a staggered arrangement, the width of the arrangement area AR1 is decreased in the direction D1. In
In
Specifically, as a method of a comparative example, the diodes DI1 and DI2 may be stacked along the direction D1, and the diodes DI3 and DI4 may be stacked along the direction D1 on the upper side of the diodes DI1 and DI2. However, this method increases the width of the arrangement area AR1 in the direction D1, since the diodes are stacked along the direction D1 and the P-type well region and the N-type well region are arranged along the direction D1.
In
As shown in
In
In
The integrated circuit device according to this embodiment includes at least one driver macrocell (driver macroblock) in which a plurality of circuit blocks are integrated into a macrocell (macro or macroblock), as shown in
The driver macrocell shown in
In
In general, the number of pads connected with the output lines of the data driver is very large. When connecting the output lines of the data driver with the data driver pads using an automatic routing tool, the width of the integrated circuit device in the direction D2 is increased due to an increase in the area of the output line wiring region. This makes it difficult to realize a narrow chip.
In
Moreover, macrocell integration as shown in
In
In the comparative example shown in
In
In the comparative example shown in
In
In
In
If the relationship “WDB+WMB≦WPB” is satisfied, when arranging the driver macrocells along the direction D1, the pad blocks are arranged along the direction D1 without an unnecessary space being formed between the adjacent pad blocks. Therefore, the data driver pads are efficiently arranged along the direction D1, whereby the width of the integrated circuit device in the direction D1 can be reduced.
If the relationship “WDB+WMB≦WPB” is satisfied, the repeater block RP (additional circuit) as shown in
In
If this relationship is satisfied, when arranging the driver macrocells along the direction D1, the pad blocks are arranged along the direction D1 so that an unnecessary space is not formed, whereby the pads can be arranged along the direction D1 at a uniform pad pitch. When the pads are arranged at a uniform pad pitch, stress uniformly occurs in the pad arrangement region when mounting the integrated circuit device on a glass substrate using bumps or the like, whereby connection failure can be prevented. When a space exists between the pads, the flow of an adhesive such as an anisotropic conductive material (e.g. ACF) may change due to the space, whereby connection failure or the like may occur. On the other hand, such a problem can be prevented by arranging the pads at a uniform pad pitch. The relationship “WDB+WMB+WAB≦NP×PP” may be satisfied. In this case, the pad pitch in the direction D1 can be made more uniform, whereby the stress can be further equalized.
When an additional circuit such as the repeater block RP is not disposed, the width WAB may be set at zero. A dummy pad (e.g. pad which is not connected with the bump or bonding wire) other than the data driver pad may be disposed in the pad block PDB. In this case, the number of pads NP may be the sum of the number of data driver pads and the number of dummy pads.
Consider the case where the display panel is a QVGA panel in which the number of pixels VPN in the vertical scan direction (data line direction) is 320 and the number of pixels HPN in the horizontal scan direction (scan line direction) is 240, as shown in
In
In
However, when the number of bits of image data read in units of horizontal scan periods is increased, it is necessary to increase the number of memory cells (sense amplifiers) arranged in the direction D2. As a result, the width W of the integrated circuit device is increased in the direction D2 to hinder a reduction in the width of the chip. Moreover, the length of the wordline WL is increased, whereby a signal delay occurs in the wordline WL.
In this embodiment, image data stored in the memory blocks MB1 to MB4 is read from the memory blocks MB1 to MB4 into the data driver blocks DB1 to DB4 a plurality of times (RN times) in one horizontal scan period.
In
In
According to the method shown in
In addition to the QVGA (320×240) display panel shown in
A plurality of read operations in one horizontal scan period may be implemented using a first method in which the row address decoder (wordline select circuit) selects different wordlines in each memory block in one horizontal scan period, or a second method in which the row address decoder (wordline select circuit) selects a single wordline in each memory block a plurality of times in one horizontal scan period. Or, a plurality of read operations in one horizontal scan period may be implemented by combining the first method and the second method.
When the wordline WL1a of the memory block has been selected and the first image data has been read from the memory block, as indicated by A1 in
When the wordline WL1b of the memory block has been selected and the second image data has been read from the memory block, as indicated by A2 in
Each of the data drivers DRa and DRb outputs data signals for 30 data lines corresponding to 30 pixels, whereby the data signals for 60 data lines corresponding to 60 pixels are output in total.
A problem in which the width W of the integrated circuit device in the direction D2 is increased due to an increase in the size of the data driver can be prevented by disposing (stacking) the data drivers DRa and DRb along the direction D1, as shown in
In
In
When the width (pitch) of the driver cells DRC1 to DR30 in the direction D2 is WD, and the width of the peripheral circuit section (e.g. buffer circuit and/or interconnect region) included in the data driver block in the direction D2 is WPCB, the width WB (maximum width) of the first to Nth circuit blocks CB1 to CBN in the direction D2 may be expressed as “Q×WD≦WB<(Q+1)×WD+WPCB”. When the width of the peripheral circuit section (e.g. row address decoder RD and/or interconnect region) included in the memory block in the direction D2 is WPC, the width WB may be expressed as “Q×WD≦WB<(Q+1)×WD+WPC”.
Suppose that the number of pixels of the display panel in the horizontal scan direction is HPN, the number of bits of image data of one pixel is PDB, the number of memory blocks is MBN (=DBN), and the number of read operations of image data from the memory block in one horizontal scan period is RN. In this case, the number P of sense amplifiers (sense amplifiers which output one bit of image data) arranged in the sense amplifier block SAB along the direction D2 may be expressed as “P=(HPN×PDB)/(MBN×RN)”. In
When the width (pitch) of each sense amplifier included in the sense amplifier block SAB in the direction D2 is WS, the width WSAB of the sense amplifier block SAB (memory block) in the direction D2 may be expressed as “WSAB=P×WS”. When the width of the peripheral circuit section included in the memory block in the direction D2 is WPC, the width WB (maximum width) of the circuit blocks CB1 to CBN in the direction D2 may also be expressed as “P×WS≦WB<(P+PDB)×WS+WPC”.
For example, the driver cell DRC1 of the data driver DRa shown in
Likewise, the driver cell DRC2 includes the R, G, and B subpixel driver cells SDC4, SDC5, and SDC6. The R, G, and B image data (R2, G2, B2) corresponding to the second data signals is input to the subpixel driver cells SDC4, SDC5, and SDC6 from the memory block. The subpixel driver cells SDC4, SDC5, and SDC6 perform D/A conversion of the image data (R2, G2, B2), and output the second R, G, and B data signals (data voltages) to the R, G, and B pads corresponding to the second data lines. The above description also applies to the remaining subpixel driver cells.
The number of subpixels is not limited to three, but may be four or more. The arrangement of the subpixel driver cells is not limited to the arrangement shown in
The portion of the sense amplifier block corresponding to one pixel includes R sense amplifiers SAR0 to SAR5, G sense amplifiers SAG0 to SAG5, and B sense amplifiers SAB0 to SAB5. In
In the configuration shown in
A modification may be made in which the sense amplifiers are not stacked in the direction D1. The rows of memory cells connected with each sense amplifier may be switched using column select signals. In this case, a plurality of image data read operations in one horizontal scan period may be realized by selecting a single wordline in the memory block a plurality of times in one horizontal scan period.
The latch circuit LAT included in each subpixel driver cell latches six-bit image data of one subpixel from the memory block MB1. The level shifter L/S converts the voltage level of the six-bit image data signal from the latch circuit LAT. The D/A converter DAC performs D/A conversion of the six-bit image data using the grayscale voltage. The output section SSQ includes a (voltage-follower-connected) operational amplifier OP which performs impedance conversion of the output signal from the D/A converter DAC, and drives one data line corresponding to one subpixel. The output section SSQ may include a discharge transistor (switch element), an eight-color-display transistor, and a DAC driver transistor in addition to the operational amplifier OP.
As shown in
For example, the latch circuit LAT (or another logic circuit) is disposed in the LV region (first circuit region) of the subpixel driver cell. The D/A converter DAC and the output section SSQ including the operational amplifier OP are disposed in the MV region (second circuit region). The level shifter L/S converts the LV level signal into an MV level signal.
In
In more detail, the buffer circuit BF1 includes an LV buffer disposed in the LV region and an MV buffer disposed in the MV region. The LV buffer receives and buffers the LV level driver control signal (e.g. latch signal) from the logic circuit block LB, and outputs the driver control signal to the circuit (LAT) disposed in the LV region of the subpixel driver cell on the D2 side of the LV buffer. The MV buffer receives the LV level driver control signal (e.g. DAC control signal or output control signal) from the logic circuit block LB, converts the LV level driver control signal into an MV level driver control signal using a level shifter, buffers the converted signal, and outputs the buffered signal to the circuit (DAC and SSQ) disposed in the MV region of the subpixel driver cell on the D2 side of the MV buffer
In this embodiment, the subpixel driver cells SDC1 to SDC180 are disposed so that the MV regions (or LV regions) of the subpixel driver cells are adjacent to each other along the direction D1, as shown in
It is unnecessary to provide a guard ring or the like between the subpixel driver cells by disposing the subpixel driver cells so that the MV regions are adjacent to each other, as shown in
According to the arrangement method shown in
According to the arrangement method shown in
According to the method shown in
In
A display panel 400 includes a plurality of data lines (source lines), a plurality of scan lines (gate lines), and a plurality of pixels specified by the data lines and the scan lines. A display operation is realized by changing the optical properties of an electro-optical element (liquid crystal element in a narrow sense) in each pixel region. The display panel 400 may be formed by an active matrix type panel using switch elements such as a TFT or TFD. The display panel 400 may be a panel other than an active matrix type panel, or may be a panel other than a liquid crystal panel.
In
Although only some embodiments of the invention have been described in detail above, those skilled in the art will readily appreciate that many modifications are possible in the embodiments without departing from the novel teachings and advantages of this invention. Accordingly, all such modifications are intended to be included within the scope of this invention. For example, any term (such as the output-side I/F region, the input-side I/F region, and two pieces) cited with a different term having broader or the same meaning (such as the first interface region, the second interface region, and K pieces) at least once in this specification or drawings can be replaced by the different term in any place in this specification and drawings.
The method according to the above embodiments in which the control transistors are disposed in the pad arrangement region may also be applied to an integrated circuit device having an arrangement and a configuration differing from those shown in
| Number | Date | Country | Kind |
|---|---|---|---|
| 2005-192479 | Jun 2005 | JP | national |
| 2005-253389 | Sep 2005 | JP | national |
| 2006-034499 | Feb 2006 | JP | national |
| Number | Name | Date | Kind |
|---|---|---|---|
| 4456977 | Hayashi | Jun 1984 | A |
| 4472638 | Nishizawa et al. | Sep 1984 | A |
| 4549174 | Funada et al. | Oct 1985 | A |
| 4566038 | Dimick | Jan 1986 | A |
| 4587629 | Dill et al. | May 1986 | A |
| 4648077 | Pinkham et al. | Mar 1987 | A |
| 4975753 | Ema | Dec 1990 | A |
| 4990996 | Kumar et al. | Feb 1991 | A |
| 5001108 | Taguchi | Mar 1991 | A |
| 5040152 | Voss et al. | Aug 1991 | A |
| 5058058 | Yasuda et al. | Oct 1991 | A |
| 5233420 | Piri et al. | Aug 1993 | A |
| 5267211 | Kobayashi et al. | Nov 1993 | A |
| 5272665 | Uesugi | Dec 1993 | A |
| 5325338 | Runaldue et al. | Jun 1994 | A |
| 5414443 | Kanatani et al. | May 1995 | A |
| 5426603 | Nakamura et al. | Jun 1995 | A |
| 5490114 | Butler et al. | Feb 1996 | A |
| 5517051 | Chatterjee | May 1996 | A |
| 5544306 | Deering et al. | Aug 1996 | A |
| 5555209 | Smith et al. | Sep 1996 | A |
| 5598346 | Agrawal et al. | Jan 1997 | A |
| 5652689 | Yuan | Jul 1997 | A |
| 5659514 | Hazani | Aug 1997 | A |
| 5701269 | Fujii | Dec 1997 | A |
| 5739803 | Neugebauer | Apr 1998 | A |
| 5744837 | Kamiura et al. | Apr 1998 | A |
| 5751065 | Chittipeddi et al. | May 1998 | A |
| 5767865 | Inoue et al. | Jun 1998 | A |
| 5815136 | Ikeda et al. | Sep 1998 | A |
| 5850195 | Berlien, Jr. et al. | Dec 1998 | A |
| 5860084 | Yaguchi | Jan 1999 | A |
| RE36089 | Ooishi et al. | Feb 1999 | E |
| 5903420 | Ham | May 1999 | A |
| 5909125 | Kean | Jun 1999 | A |
| 5917770 | Tanaka | Jun 1999 | A |
| 5920885 | Rao | Jul 1999 | A |
| 5933364 | Aoyama et al. | Aug 1999 | A |
| 5962899 | Yang et al. | Oct 1999 | A |
| 6005296 | Chan | Dec 1999 | A |
| 6025822 | Motegi et al. | Feb 2000 | A |
| 6034541 | Kopec, Jr. et al. | Mar 2000 | A |
| 6111786 | Nakamura | Aug 2000 | A |
| 6118425 | Kudo et al. | Sep 2000 | A |
| 6125021 | Duvvury et al. | Sep 2000 | A |
| 6140983 | Quanrud | Oct 2000 | A |
| 6225990 | Aoki et al. | May 2001 | B1 |
| 6229336 | Felton et al. | May 2001 | B1 |
| 6229753 | Kono et al. | May 2001 | B1 |
| 6246386 | Perner | Jun 2001 | B1 |
| 6259459 | Middleton | Jul 2001 | B1 |
| 6262541 | Asai | Jul 2001 | B1 |
| 6278148 | Watanabe et al. | Aug 2001 | B1 |
| 6324088 | Keeth et al. | Nov 2001 | B1 |
| 6339417 | Quanrud | Jan 2002 | B1 |
| 6340963 | Anno et al. | Jan 2002 | B1 |
| 6421286 | Ohtani et al. | Jul 2002 | B1 |
| 6489689 | Nojiri | Dec 2002 | B2 |
| 6552705 | Hirota | Apr 2003 | B1 |
| 6559508 | Lin et al. | May 2003 | B1 |
| 6580631 | Keeth et al. | Jun 2003 | B1 |
| 6611407 | Chang | Aug 2003 | B1 |
| 6646283 | Akimoto et al. | Nov 2003 | B1 |
| 6697037 | Alt et al. | Feb 2004 | B1 |
| 6724378 | Tamura et al. | Apr 2004 | B2 |
| 6731538 | Noda et al. | May 2004 | B2 |
| 6791632 | Lee et al. | Sep 2004 | B2 |
| 6822631 | Yatabe | Nov 2004 | B1 |
| 6826116 | Noda et al. | Nov 2004 | B2 |
| 6839097 | Park et al. | Jan 2005 | B2 |
| 6858901 | Ker et al. | Feb 2005 | B2 |
| 6862247 | Yamazaki | Mar 2005 | B2 |
| 6873310 | Matsueda | Mar 2005 | B2 |
| 6873566 | Choi | Mar 2005 | B2 |
| 6898096 | Endo et al. | May 2005 | B2 |
| 6999353 | Noda et al. | Feb 2006 | B2 |
| 7034792 | Tamura | Apr 2006 | B2 |
| 7078948 | Dosho | Jul 2006 | B2 |
| 7081879 | Sun et al. | Jul 2006 | B2 |
| 7102223 | Kanaoka et al. | Sep 2006 | B1 |
| 7110274 | Endo et al. | Sep 2006 | B1 |
| 7142221 | Sakamaki et al. | Nov 2006 | B2 |
| 7158439 | Shionori et al. | Jan 2007 | B2 |
| 7164415 | Ooishi et al. | Jan 2007 | B2 |
| 7176864 | Moriyama et al. | Feb 2007 | B2 |
| 7180495 | Matsueda | Feb 2007 | B1 |
| 7193623 | Moon | Mar 2007 | B2 |
| 7233511 | Endo et al. | Jun 2007 | B2 |
| 7256976 | Sato | Aug 2007 | B2 |
| 7280329 | Kim et al. | Oct 2007 | B2 |
| 7317627 | Endo et al. | Jan 2008 | B2 |
| 7330163 | Nakai et al. | Feb 2008 | B2 |
| 7342302 | Kanaoka et al. | Mar 2008 | B2 |
| 7369195 | Wu et al. | May 2008 | B2 |
| 7391668 | Natori et al. | Jun 2008 | B2 |
| 7411804 | Kumagai et al. | Aug 2008 | B2 |
| 7411861 | Kodaira et al. | Aug 2008 | B2 |
| 7466603 | Ong | Dec 2008 | B2 |
| 7471573 | Kodaira et al. | Dec 2008 | B2 |
| 7480164 | Endo et al. | Jan 2009 | B2 |
| 7508370 | Sekiguchi et al. | Mar 2009 | B2 |
| 7522441 | Kumagai et al. | Apr 2009 | B2 |
| 7629652 | Suzuki et al. | Dec 2009 | B2 |
| 7759804 | Kanaoka et al. | Jul 2010 | B2 |
| 7940500 | Yang et al. | May 2011 | B2 |
| 8054710 | Ito et al. | Nov 2011 | B2 |
| 20010008498 | Ooishi | Jul 2001 | A1 |
| 20010014051 | Watanabe et al. | Aug 2001 | A1 |
| 20010022744 | Noda et al. | Sep 2001 | A1 |
| 20020011998 | Tamura | Jan 2002 | A1 |
| 20020015128 | Sakaguchi | Feb 2002 | A1 |
| 20020036625 | Nakamura | Mar 2002 | A1 |
| 20020067328 | Yumoto et al. | Jun 2002 | A1 |
| 20020080104 | Aoki | Jun 2002 | A1 |
| 20020105510 | Tsuchiya | Aug 2002 | A1 |
| 20020113783 | Tamura et al. | Aug 2002 | A1 |
| 20020126108 | Koyama et al. | Sep 2002 | A1 |
| 20020154557 | Mizugaki et al. | Oct 2002 | A1 |
| 20030020845 | Lee et al. | Jan 2003 | A1 |
| 20030034948 | Imamura | Feb 2003 | A1 |
| 20030053022 | Kaneko et al. | Mar 2003 | A1 |
| 20030053321 | Ishiyama | Mar 2003 | A1 |
| 20030156103 | Ota | Aug 2003 | A1 |
| 20030169244 | Kurokawa et al. | Sep 2003 | A1 |
| 20030189541 | Hashimoto | Oct 2003 | A1 |
| 20030223164 | Ebara | Dec 2003 | A1 |
| 20040004877 | Uetake | Jan 2004 | A1 |
| 20040017341 | Maki | Jan 2004 | A1 |
| 20040021652 | Abe et al. | Feb 2004 | A1 |
| 20040021947 | Schofield et al. | Feb 2004 | A1 |
| 20040056252 | Kasai | Mar 2004 | A1 |
| 20040070900 | Ker et al. | Apr 2004 | A1 |
| 20040095307 | Kim | May 2004 | A1 |
| 20040124472 | Lin et al. | Jul 2004 | A1 |
| 20040140970 | Morita | Jul 2004 | A1 |
| 20040164943 | Ogawa et al. | Aug 2004 | A1 |
| 20040174646 | Ko | Sep 2004 | A1 |
| 20040239606 | Ota | Dec 2004 | A1 |
| 20040246215 | Yoo | Dec 2004 | A1 |
| 20050001797 | Miller et al. | Jan 2005 | A1 |
| 20050001846 | Shiono | Jan 2005 | A1 |
| 20050045955 | Kim et al. | Mar 2005 | A1 |
| 20050047266 | Shionori et al. | Mar 2005 | A1 |
| 20050052340 | Goto et al. | Mar 2005 | A1 |
| 20050057580 | Yamano et al. | Mar 2005 | A1 |
| 20050057581 | Horiuchi et al. | Mar 2005 | A1 |
| 20050073470 | Nose et al. | Apr 2005 | A1 |
| 20050087807 | Righter | Apr 2005 | A1 |
| 20050093777 | Kim et al. | May 2005 | A1 |
| 20050116960 | Shioda et al. | Jun 2005 | A1 |
| 20050122303 | Hashimoto | Jun 2005 | A1 |
| 20050184979 | Sakaguchi | Aug 2005 | A1 |
| 20050195149 | Ito | Sep 2005 | A1 |
| 20050212788 | Fukuda et al. | Sep 2005 | A1 |
| 20050212826 | Fukuda et al. | Sep 2005 | A1 |
| 20050219189 | Fukuo | Oct 2005 | A1 |
| 20050243043 | Jeoung et al. | Nov 2005 | A1 |
| 20050253976 | Sekiguchi et al. | Nov 2005 | A1 |
| 20050262293 | Yoon | Nov 2005 | A1 |
| 20050270262 | Oh | Dec 2005 | A1 |
| 20050280613 | Takei et al. | Dec 2005 | A1 |
| 20050285862 | Noda et al. | Dec 2005 | A1 |
| 20060017681 | Jang et al. | Jan 2006 | A1 |
| 20060028417 | Harada et al. | Feb 2006 | A1 |
| 20060050042 | Yi | Mar 2006 | A1 |
| 20060062483 | Kondo et al. | Mar 2006 | A1 |
| 20060145972 | Zhang et al. | Jul 2006 | A1 |
| 20060244710 | Iriguchi et al. | Nov 2006 | A1 |
| 20070000971 | Kumagai et al. | Jan 2007 | A1 |
| 20070001886 | Ito et al. | Jan 2007 | A1 |
| 20070001973 | Kumagai et al. | Jan 2007 | A1 |
| 20070001982 | Ito et al. | Jan 2007 | A1 |
| 20070001983 | Ito et al. | Jan 2007 | A1 |
| 20070001984 | Kumagai et al. | Jan 2007 | A1 |
| 20070002061 | Kumagai et al. | Jan 2007 | A1 |
| 20070002188 | Kumagai et al. | Jan 2007 | A1 |
| 20070002509 | Kumagai et al. | Jan 2007 | A1 |
| 20070013635 | Ito et al. | Jan 2007 | A1 |
| 20070013687 | Kodaira et al. | Jan 2007 | A1 |
| 20070013706 | Kodaira et al. | Jan 2007 | A1 |
| 20070013707 | Kodaira et al. | Jan 2007 | A1 |
| 20070016700 | Kodaira et al. | Jan 2007 | A1 |
| 20070035503 | Kurokawa et al. | Feb 2007 | A1 |
| 20070187762 | Saiki et al. | Aug 2007 | A1 |
| 20100059882 | Suzuki et al. | Mar 2010 | A1 |
| 20100252924 | Kanaoka et al. | Oct 2010 | A1 |
| Number | Date | Country |
|---|---|---|
| 1534560 | Oct 2004 | CN |
| 1542964 | Nov 2004 | CN |
| 0 499 478 | Aug 1992 | EP |
| A-56-130888 | Oct 1981 | JP |
| A 63-225993 | Sep 1988 | JP |
| A 1-171190 | Jul 1989 | JP |
| A-2-79294 | Mar 1990 | JP |
| A 4-370595 | Dec 1992 | JP |
| A 5-181154 | Jul 1993 | JP |
| A-05-189957 | Jul 1993 | JP |
| A-8-181219 | Jul 1995 | JP |
| A 7-281634 | Oct 1995 | JP |
| A 8-69696 | Mar 1996 | JP |
| A-8-236706 | Sep 1996 | JP |
| A-9-265274 | Oct 1997 | JP |
| A 11-261011 | Sep 1999 | JP |
| A 11-274424 | Oct 1999 | JP |
| A 11-330393 | Nov 1999 | JP |
| A-2000-020032 | Jan 2000 | JP |
| A-2000-252435 | Sep 2000 | JP |
| A-2001-067868 | Mar 2001 | JP |
| 2001-222249 | Aug 2001 | JP |
| A 2001-222276 | Aug 2001 | JP |
| A-2002-6334 | Jan 2002 | JP |
| A-2002-83933 | Mar 2002 | JP |
| A-2002-182232 | Jun 2002 | JP |
| A 2002-244624 | Aug 2002 | JP |
| A-2002-313925 | Oct 2002 | JP |
| A-2002-358777 | Dec 2002 | JP |
| A 2003-022063 | Jan 2003 | JP |
| A-2003-23092 | Jan 2003 | JP |
| 2003-107528 | Apr 2003 | JP |
| A-2003-203984 | Jul 2003 | JP |
| A-2003-289104 | Oct 2003 | JP |
| A 2003-330433 | Nov 2003 | JP |
| A 2004-040042 | Feb 2004 | JP |
| A-2004-95577 | Mar 2004 | JP |
| A 2004-146806 | May 2004 | JP |
| A 2004-159314 | Jun 2004 | JP |
| A 2004-328456 | Nov 2004 | JP |
| A 2005-17725 | Jan 2005 | JP |
| A 2005-72607 | Mar 2005 | JP |
| A 2005-085820 | Mar 2005 | JP |
| 2005-167212 | Jun 2005 | JP |
| A-2005-150559 | Jun 2005 | JP |
| A-2006-228770 | Aug 2006 | JP |
| A 1992-17106 | Sep 1992 | KR |
| 1999-88197 | Dec 1999 | KR |
| A 2001-100814 | Nov 2001 | KR |
| 10-2005-0011743 | Jan 2005 | KR |
| 501080 | Sep 2002 | TW |
| 522366 | Mar 2003 | TW |
| 525134 | Mar 2003 | TW |
| I224300 | Mar 2003 | TW |
| 563081 | Nov 2003 | TW |
| WO 2004-025849 | Mar 2004 | WO |
| Entry |
|---|
| U.S. Appl. No. 11/270,569, filed Nov. 10, 2005 in the name of Satoru Kodaira et al. |
| U.S. Appl. No. 11/270,546, filed Nov. 10, 2005 in the name of Satoru Kodaira et al. |
| U.S. Appl. No. 11/270,552, filed Nov. 10, 2005 in the name of Satoru Kodaira et al. |
| U.S. Appl. No. 11/270,694, filed Nov. 10, 2005 in the name of Satoru Kodaira et al. |
| U.S. Appl. No. 11/270,749, filed Nov. 10, 2005 in the name of Satoru Kodaira et al. |
| U.S. Appl. No. 11/270,551, filed Nov. 10, 2005 in the name of Takashi Kumagai et al. |
| U.S. Appl. No. 11/270,779, filed Nov. 10, 2005 in the name of Takashi Kumagai et al. |
| U.S. Appl. No. 11/270,585, filed Nov. 10, 2005 in the name of Takashi Kumagai et al. |
| U.S. Appl. No. 11/270,747, filed Nov. 10, 2005 in the name of Takashi Kumagai et al. |
| U.S. Appl. No. 11/270,632, filed Nov. 10, 2005 in the name of Takashi Kumagai et al. |
| U.S. Appl. No. 11/270,553, filed Nov. 10, 2005 in the name of Takashi Kumagai et al. |
| U.S. Appl. No. 11/270,631, filed Nov. 10, 2005 in the name of Takashi Kumagai et al. |
| U.S. Appl. No. 11/270,665, filed Nov. 10, 2005 in the name of Takashi Kumagai et al. |
| U.S. Appl. No. 11/270,549, filed Nov. 10, 2005 in the name of Satoru Kodaira et al. |
| U.S. Appl. No. 11/270,666, filed Nov. 10, 2005 in the name of Satoru Kodaira et al. |
| U.S. Appl. No. 11/270,630, filed Nov. 10, 2005 in the name of Satoru Kodaira et al. |
| U.S. Appl. No. 11/270,586, filed Nov. 10, 2005 in the name of Satoru Kodaira et al. |
| U.S. Appl. No. 11/270,547, filed Nov. 10, 2005 in the name of Satoru Kodaira et al. |
| Filed Jun. 30, 2006 in the name of Satoru Ito et al. |
| Filed Jun. 30, 2006 in the name of Satoru Kodaira et al. |
| Filed Jun. 30, 2006 in the name of Takashi Kumagai et al. |
| Office Action issued in JP Application No. 2006-154200 on Jun. 19, 2007 (with English translation). |
| U.S. Appl. No. 12/000,882, filed Dec. 18, 2007 in the name of Kodaira et al. |
| Sedra & Smith, Microelectronic Circuit (Jun. 1990), Saunder College Publishing, 3rd Edition, Chapter 5, p. 300. |
| Jan. 18, 2012 Notice of Allowance issued in U.S. Appl. No. 11/477,720. |
| Jul. 20, 2012 Office Action issued in U.S. Appl. No. 13/022,995. |
| Nov. 22, 2011 Office Action issued in Japanese Application No. 2008-035576 (with translation). |
| Nov. 22, 2011 Office Action issued in Japanese Application No. 2008-124746 (with translation). |
| Nov. 29, 2011 Office Action issued in U.S. Appl. No. 11/477,741. |
| Feb. 9, 2012 Notice of Allowance issued in U.S. Appl. No. 11/703,686. |
| U.S. Office Action dated Feb. 25, 2013 from U.S. Appl. No. 13/022,995. |
| Aug. 5, 2011 Notice of Allowance issued in U.S. Appl. No. 11/477,720. |
| Aug. 10, 2011 Notice of Allowance issued in U.S. Appl. No. 11/477,670. |
| Aug. 30, 2012 Office Action issued in U.S. Appl. No. 13/137,995. |
| Jun. 6, 2013 Office Action issued in U.S. Appl. No. 13/022,995. |
| Number | Date | Country | |
|---|---|---|---|
| 20070013634 A1 | Jan 2007 | US |
