Patent Grant
7495988
Japanese Patent Application No. 2005-192684, filed on Jun. 30, 2005, is hereby incorporated by reference in its entirety.
The present invention relates to an integrated circuit device and an electronic instrument.
In recent years, an increase in resolution of a display panel provided in an electronic instrument has been demanded accompanying a widespread use of electronic instruments. Therefore, a driver circuit which drives a display panel is required to exhibit high performance. However, since many types of circuits are necessary for a high-performance driver circuit, the circuit scale and the circuit complexity tend to be increased in proportion to an increase in resolution of a display panel. Therefore, since it is difficult to reduce the chip area of the driver circuit while maintaining the high performance or providing another function, manufacturing cost cannot be reduced.
A high-resolution display panel is also provided in a small electronic instrument, and high performance is demanded for its driver circuit. However, the circuit scale cannot be increased to a large extent since a small electronic instrument is limited in space. Therefore, since it is difficult to reduce the chip area while providing high performance, a reduction in manufacturing cost or provision of another function is difficult.
In particular, when reducing the size of the chip including a display memory, since a minute current flows through a bitline connected with memory cells, the chip tends to be affected by noise. Therefore, the potential of the bitline becomes unstable, whereby an erroneous detection occurs.
The invention of JP-A-2001-222276 cannot solve the above problems.
According to a first aspect of the invention, there is provided an integrated circuit device having a display memory which stores at least part of data displayed in a display panel which has a plurality of scan lines and a plurality of data lines,
wherein the display memory includes a plurality of wordlines, a plurality of bitlines, and a plurality of memory cells;
wherein a plurality of first power supply interconnects for supplying a first power supply voltage to the memory cells are formed in a metal interconnect layer in which the wordlines are formed;
wherein a plurality of second power supply interconnects for supplying a second power supply voltage to the memory cells are formed in another metal interconnect layer in which the bitlines are formed, the second power supply voltage being higher than the first power supply voltage;
wherein a plurality of bitline protection interconnects are formed in a layer above the bitlines, each of the bitline protection interconnects at least partially covering one of the bitlines in a plan view; and
wherein a third power supply interconnect for supplying a third power supply voltage to circuits of the integrated circuit device other than the display memory are formed in a layer above the bitline protection interconnects, the third power supply voltage being higher than the second power supply voltage.
According to a second aspect of the invention, there is provided an integrated circuit device having a display memory which stores at least part of data displayed in a display panel which has a plurality of scan lines and a plurality of data lines,
wherein the display memory includes a plurality of wordlines, a plurality of bitlines, and a plurality of memory cells;
wherein a plurality of first power supply interconnects for supplying a first power supply voltage to the memory cells are formed in a metal interconnect layer in which the wordlines are formed;
wherein a plurality of second power supply interconnects for supplying a second power supply voltage to the memory cells are formed in another metal interconnect layer in which the bitlines are formed, the second power supply voltage being higher than the first power supply voltage;
wherein the wordlines are formed in a layer above the bitlines, each of the wordlines at least partially covering one of the bitlines in a plan view, and each of the first power supply interconnects at least partially covering one of the bitlines in a plan view; and
wherein a third power supply interconnect for supplying a third power supply voltage to circuits of the integrated circuit device other than the display memory is formed in a layer above the wordlines, the third power supply voltage being higher than the second power supply voltage.
According to a third aspect of the invention, there is provided an electronic instrument, comprising:
any of the above-described integrated circuit devices; and
a display panel.
The invention may provide an integrated circuit device which can prevent an erroneous detection by protecting bitlines, even when the degrees of freedom of the layout of the integrated circuit device including a display memory are increased or the size of the integrated circuit device is reduced by providing an interconnect for supplying a relatively high voltage in a layer above the bitlines, and an electronic instrument including the same.
According to one embodiment of the invention, there is provided an integrated circuit device having a display memory which stores at least part of data displayed in a display panel which has a plurality of scan lines and a plurality of data lines,
wherein the display memory includes a plurality of wordlines, a plurality of bitlines, and a plurality of memory cells;
wherein a plurality of first power supply interconnects for supplying a first power supply voltage to the memory cells are formed in a metal interconnect layer in which the wordlines are formed;
wherein a plurality of second power supply interconnects for supplying a second power supply voltage to the memory cells are formed in another metal interconnect layer in which the bitlines are formed, the second power supply voltage being higher than the first power supply voltage;
wherein a plurality of bitline protection interconnects are formed in a layer above the bitlines, each of the bitline protection interconnects at least partially covering one of the bitlines in a plan view; and
wherein a third power supply interconnect for supplying a third power supply voltage to circuits of the integrated circuit device other than the display memory are formed in a layer above the bitline protection interconnects, the third power supply voltage being higher than the second power supply voltage.
In the embodiment, since the bitline protection interconnect exists between the bitlines and the third power supply interconnect, capacitive coupling between the bitlines and the third power supply interconnect can be prevented. Therefore, a problem in which the potential of the bitline rises due to capacitive coupling when the potential of the third power supply interconnect rises can be prevented, for example. This prevents the potential of the bitline from becoming unstable, whereby data stored in the memory cell is not erroneously detected.
In this integrated circuit device, the wordlines may be formed in a layer between the layers in which the bitlines and the bitline protection interconnects are respectively formed, each of the wordlines at least partially covering one of the bitlines in a plan view.
Since the wordlines are set at a select potential in one horizontal scan period within one vertical scan period and set at an unselect potential in the remaining period, the wordlines can exhibit a shielding function equal to that of the bitline protection interconnect.
In this integrated circuit device, each of the first power supply interconnects may at least partially cover one of the bitlines in a plan view.
Since the first power supply voltage supplied to the memory cell is constant (e.g. VSS), the first power supply interconnect can exhibit a bitline protection function equal to that of the bitline protection interconnect.
In this integrated circuit device,
each of the memory cells may have a short side and a long side;
in each of the memory cells, the bitlines may be formed along a first direction in which the short side of each of the memory cells extends; and
in each of the memory cells, the wordlines may be formed along a second direction in which the long side of each of the memory cells extends.
The above description shows an example of the memory cell layout to which the embodiment is applied.
In this layout, two of the first power supply interconnects may be provided in each of the memory cells.
In this case, capacitive coupling between the bitline in each memory cell and the third power supply interconnect can be prevented by the bitline protection interconnect, the wordline, and two first power supply interconnects.
In this integrated circuit device, a protection interconnect non-formation region in which the bitline protection interconnects are not formed may be provided in a layer above a region in which the first power supply interconnects are formed, or in a layer above a region in which the second power supply interconnects are formed.
Therefore, even if gas is generated in a layer below the bitline protection interconnects due to a heat treatment or the like after the formation of the bitline protection interconnects, the gas can be discharged through the protection interconnect non-formation region, whereby breakage of the interconnects of the memory cell and others can be prevented.
In this integrated circuit device, the bitline protection interconnects may extend in the first direction in which the bitlines extend.
This enables each of the bitlines to be entirely covered by one of the bitline protection interconnects in a plan view.
In this case, since the protection interconnect non-formation region can also extend in the first direction, the protection interconnect non-formation region is not formed above the bitlines.
Alternatively, the bitline protection interconnects may extend in the second direction, instead of the first direction.
In this case, since the protection interconnect non-formation region also extend in the second direction, part of the protection interconnect non-formation region is disposed above the bitlines. However, by disposing the protection interconnect non-formation region to a position above the wordlines or the first power supply interconnects in a plan view, the bitline protection function can be secured by the wordlines or the first power supply interconnects.
For instance, in this integrated circuit device,
two of the first power supply interconnects may be provided in each of the memory cells; and
end sections of one of the bitline protection interconnects in the first direction may at least partially cover the two of the first power supply interconnects in a plan view.
This causes the bitline protection interconnects or the first power supply interconnects to always exist between the bitlines and the third power supply interconnect in a plan view.
In this integrated circuit device, one of the first and second power supply voltages may be supplied to the bitline protection interconnects.
This causes the bitline protection interconnects to be set at a constant potential instead of a floating potential, and so the bitline protection function which prevents capacitive coupling is improved. Alternatively, for this purpose, the bitline protection interconnects may be electrically connected to one of the first and second power supply interconnects.
According to one embodiment of the invention, there is provided an integrated circuit device having a display memory which stores at least part of data displayed in a display panel which has a plurality of scan lines and a plurality of data lines,
wherein the display memory includes a plurality of wordlines, a plurality of bitlines, and a plurality of memory cells;
wherein a plurality of first power supply interconnects for supplying a first power supply voltage to the memory cells are formed in a metal interconnect layer in which the wordlines are formed;
wherein a plurality of second power supply interconnects for supplying a second power supply voltage to the memory cells are formed in another metal interconnect layer in which the bitlines are formed, the second power supply voltage being higher than the first power supply voltage;
wherein the wordlines are formed in a layer above the bitlines, each of the wordlines at least partially covering one of the bitlines in a plan view, and each of the first power supply interconnects at least partially covering one of the bitlines in a plan view; and
wherein a third power supply interconnect for supplying a third power supply voltage to circuits of the integrated circuit device other than the display memory is formed in a layer above the wordlines, the third power supply voltage being higher than the second power supply voltage.
In this embodiment, capacitive coupling between the bitlines and the third power supply interconnect can be prevented by the wordlines and the first power supply interconnects without providing the bitline protection interconnect.
According to one embodiment of the invention, there is provided an electronic instrument, comprising:
any of the above-described integrated circuit devices; and
a display panel.
In this electronic instrument, the integrated circuit device may be mounted on a substrate which forms the display panel.
In this electronic instrument, the integrated circuit device may be mounted on a substrate which forms the display panel so that the wordlines of the integrated circuit device are parallel to a direction in which the data lines of the display panel extend.
These embodiments of the invention will be described below, with reference to the drawings. Note that the embodiments described below do not in any way limit the scope of the invention laid out in the claims herein. In addition, not all of the elements of the embodiments described below should be taken as essential requirements of the invention. In the drawings, components denoted by the same reference numbers have the same meanings.
1. Display Driver
The display panel 10 includes the display region 12 having PX pixels in the direction X and PY pixels in the direction Y, for example. When the display panel 10 supports a QVGA display, PX=240 and PY=320 so that the display region 12 is displayed in 240×320 pixels. The number of pixels PX of the display panel 10 in the direction X coincides with the number of data lines in the case of a black and white display. In the case of a color display, one pixel is formed by three subpixels including an R subpixel, a G subpixel, and a B subpixel. Therefore, the number of data lines is (3×PX) in the case of a color display. Accordingly, the “number of pixels corresponding to the data lines” means the “number of subpixels in the direction X” in the case of a color display. The number of bits of each subpixel is determined corresponding to the grayscale. When the grayscale values of three subpixels are respectively G bits, the grayscale value of one pixel is 3G When each subpixel represents 64 grayscales (six bits), the amount of data for one pixel is 6×3=18 bits.
The relationship between the number of pixels PX and the number of pixels PY may be PX>PY, PX<PY, or PX=PY.
The display driver 20 has a length CX in the direction X and a length CY in the direction Y. A long side IL of the display driver 20 having the length CX is parallel to a side PL1 of the display region 12 on the side of the display driver 20. Specifically, the display driver 20 is mounted on the display panel 10 so that the long side IL is parallel to the side PL1 of the display region 12.
The above-mentioned ratio “1:10” is merely an example. The ratio is not limited thereto. For example, the ratio may be 1:11 or 1:9.
In
In a display driver 22 shown in
On the other hand, since the display driver 20 of the embodiment is formed so that the length CX of the long side IL is equal to the length LX of the side PL1 of the display region 12 as shown in
In the embodiment, the display driver 20 is formed so that the length CX of the long side IL is equal to the length LX of the side PL1 of the display region 12. However, the invention is not limited thereto.
The distance DY can be reduced while achieving a reduction in the chip size by setting the length of the long side IL of the display driver 20 to be equal to the length LX of the side PL1 of the display region 12 and reducing the length of the short side IS. Therefore, manufacturing cost of the display driver 20 and manufacturing cost of the display panel 10 can be reduced.
The data lines of the display panel 10 are divided into a plurality of (e.g. four) blocks, and one data line driver 100 drives the data lines for one block.
It is possible to flexibly meet the user's needs by providing the block width ICY and disposing each circuit within the block width ICY In more detail, since the number of data lines which drive the pixels is changed when the number of pixels PX of the drive target display panel 10 in the direction X is changed, it is necessary to design the data line driver 100 and the RAM 200 corresponding to such a change in the number of data lines. In a display driver for a low-temperature polysilicon (LTPS) TFT panel, since the scan driver 300 can be formed on the glass substrate, the scan line driver 300 may not be provided in the display driver 20.
In the embodiment, the display driver 20 can be designed merely by changing the data line driver 100 and the RAM 200 or removing the scan line driver 300. Therefore, since it is unnecessary to newly design the display driver 20 by utilizing the original layout, design cost can be reduced.
In
In
The length of the RAM 200 in the direction Y is set at RY. In the embodiment, the length RY is set to be equal to the block width ICY shown in
The RAM 200 having the length RY includes a plurality of wordlines WL and a wordline control circuit 240 which controls the wordlines WL. The RAM 200 includes a plurality of bitlines BL, a plurality of memory cells MC, and a control circuit (not shown) which controls the bitlines BL and the memory cells MC. The bitlines BL of the RAM 200 are provided parallel to the direction X. Specifically, the bitlines BL are provided parallel to the side PL1 of the display region 12. The wordlines WL of the RAM 200 are provided parallel to the direction Y. Specifically, the wordlines WL are provided parallel to the interconnects DQL.
Data is read from the memory cell MC of the RAM 200 by controlling the wordline WL, and the data read from the memory cell MC is supplied to the data line driver 100. Specifically, when the wordline WL is selected, data stored in the memory cells MC arranged along the direction Y is supplied to the data line driver 100.
A shield layer 290 (bitline protection interconnect layer in a broad sense) is formed in the fourth metal interconnect layer ALD. This enables effects exerted on the memory cells MC of the RAM 200 to be reduced even if various interconnects are formed in the fifth metal interconnect layer ALE in a layer above the memory cells MC of the RAM 200. A signal interconnect for controlling the control circuit for the RAM 200, such as the wordline control circuit 240, may be formed in the fourth metal interconnect layer ALD in the region in which the control circuit is formed.
An interconnect 296 formed in the third metal interconnect layer ALC may be used as the wordline WL or a voltage VSS interconnect (first power supply interconnect in a broad sense), for example. An interconnect 298 formed in the second metal interconnect layer ALB may be used as the bitline BL or a voltage VDD interconnect (second power supply interconnect in a broad sense), for example. An interconnect 299 formed in the first metal interconnect layer ALA may be used to connect with each node formed in a semiconductor layer of the RAM 200.
The bitline interconnect may be formed in the third metal interconnect layer ALC, and the wordline interconnect may be formed in the second metal interconnect layer ALB, differing from the above-described configuration.
As described above, since various interconnects can be formed in the fifth metal interconnect layer ALE of the RAM 200, various types of circuit blocks can be arranged along the direction X as shown in
2. Data Line Driver
2.1 Configuration of Data Line Driver
The output circuit 104 is formed by an operational amplifier, for example. However, the invention is not limited thereto. As shown in
The data line driver cell 110 includes an output circuit 140, the DAC 120, and the latch circuit 130, for example. However, the invention is not limited thereto. For example, the output circuit 140 may be provided outside the data line driver cell 110. The output circuit 140 may be either the output circuit 104 shown in
When the grayscale data indicating the grayscales of the R subpixel, the G subpixel, and the B subpixel is set at G bits, G-bit data is supplied to the data line driver cell 110 from the RAM 200. The latch circuit 130 latches the G-bit data. The DAC 120 outputs the grayscale voltage through the output circuit 140 based on the output from the latch circuit 130. This enables the data line provided in the display panel 10 to be driven.
2.2 A Plurality of Readings in One Horizontal Scan Period
The display driver 24 selects the wordline WL once in the 1H period. The data line driver 105 latches data output from the RAM 205 upon selection of the wordline WL, and drives the data lines. In the display driver 24, since the wordline WL is significantly longer than the bitline BL as shown in
The RAM 205 shown in
In the embodiment, the RAM 205 may be divided into a plurality of blocks and disposed in a state in which the divided blocks are rotated at 90 degrees. For example, the RAM 205 may be divided into four blocks and disposed in a state in which the divided blocks are rotated at 90 degrees, as shown in
In the embodiment, the length RY of the RAM 200 in the direction Y can be reduced by reading data a plurality of times in the 1H period, as shown in
In the embodiment, the RAM 200 divided into blocks can be provided in the display driver 20 as described above. In the embodiment, the 4BANK RAMs 200 can be provided in the display driver 20, for example. In this case, data line drivers 100-1 to 100-4 corresponding to each RAM 200 drive the corresponding data lines DL as shown in
In more detail, the data line driver 100-1 drives a data line group DLS1, the data line driver 100-2 drives a data line group DLS2, the data line driver 100-3 drives a data line group DLS3, and the data line driver 100-4 drives a data line group DLS4. Each of the data line groups DLS1 to DLS4 is one of four blocks into which the data lines DL provided in the display region 12 of the display panel 10 are divided, for example. The data lines of the display panel 10 can be driven by providing four data line drivers 100-1 to 1004 corresponding to the 4BANK RAM 200 and causing the data line drivers 100-1 to 100-4 to drive the corresponding data lines.
2.3 Divided Structure of Data Line Driver
The length RY of the RAM 200 shown in
In the embodiment, on the premise that data is read a plurality of times (e.g. twice) in one horizontal scan period in order to reduce the length RY of the RAM 200 shown in
For example, when the number of pixels PX is 240, the grayscale of the pixel is 18 bits, and the number of BANKs of the RAM 200 is four (4BANK), 1080 (=240×18÷4) bits of data must be output from each RAM 200 when reading data only once in the 1H period.
However, it is desired to reduce the length RY of the RAM 200 in order to reduce the chip area of the display driver 100. Therefore, as shown in
The data line driver 100A drives a part of the data lines of the display panel 10. The data line driver 100B drives a part of the data lines of the display panel 10 other than the data lines driven by the data line driver 100A. As described above, the data line drivers 100A and 100B cooperate to drive the data lines of the display panel 10.
In more detail, the wordlines WL1 and WL2 are selected in the 1H period as shown in
A latch signal SLB falls at a timing A2. The latch signal SLB is supplied to the data line driver 100B, for example. The data line driver 100B latches M-bit data supplied from the RAM 200 in response to the falling edge of the latch signal SLB, for example.
In more detail, data stored in a memory cell group MCS1 (M memory cells) is supplied to the data line drivers 100A and 100B through a sense amplifier circuit 210 upon selection of the wordline WL1, as shown in
Upon selection of the wordline WL2, data stored in a memory cell group MCS2 (M memory cells) is supplied to the data line drivers 100A and 100B through the sense amplifier circuit 210. The latch signal SLB falls in response to the selection of the wordline WL2. Therefore, the data stored in the memory cell group MCS2 (M memory cells) is latched by the data line driver 100B.
For example, when M is set at 540 bits, M=540 bit data is latched by each of the data line drivers 100A and 100B, since the data is read twice in the 1H period. Specifically, 1080-bit data in total is latched by the data line driver 100 so that 1080 bits necessary for the above-described example can be latched in the 1H period. Therefore, the amount of data necessary in the 1H period can be latched, and the length RY of the RAM 200 can be approximately halved. This enables the block width ICY of the display driver 20 to be reduced, whereby manufacturing cost of the display driver 20 can be reduced.
The outputs of the data line drivers 100A and 100B may be caused to rise based on control by using a data line enable signal (not shown) or the like as indicated by A3 and A4 shown in
When the number of pixels PY is 320 (the number of scan lines of the display panel 10 is 320) and 60 frames are displayed within one second, the 1H period is about 52 μs as shown in
The value M can be obtained by using the following equation, when BNK denotes the number of BANKs, N denotes the number of readings in the 1H period, and “the number of pixels PX×3” means the number of pixels (or the number of subpixels in the embodiment) corresponding to the data lines of the display panel 10 and coincides with the number of data lines DLN:
In the embodiment, the sense amplifier circuit 210 has a latch function. However, the invention is not limited thereto. For example, the sense amplifier circuit 210 need not have a latch function.
2.4 Subdivision of Data Line Driver
When the grayscale G bits of each subpixel are set at six bits (64 grayscales), 6-bit data is supplied from the RAM 200 to data line driver cells 110A-R and 110B-R for the R subpixel. In order to supply the 6-bit data, six sense amplifiers 211 among the sense amplifiers 211 included in the sense amplifier circuit 210 of the RAM 200 correspond to each data line driver cell 110, for example.
For example, it is necessary that a length SCY of the data line driver cell 110A-R in the direction Y be within a length SAY of the six sense amplifiers 211 in the direction Y. Likewise, it is necessary that the length of each data line driver cell in the direction Y be within the length SAY of the six sense amplifiers 211. When the length SCY cannot be set within the length SAY of the six sense amplifiers 211, the length of the data line driver 100 in the direction Y becomes greater than the length RY of the RAM 200, whereby the layout efficiency is decreased.
The size of the RAM 200 has been reduced in view of the process, and the sense amplifier 211 is also small. As shown in
In the embodiment, the data line drivers 100A and 100B divided by the number of readings N in the 1H period may be further divided into k (k is an integer larger than 1) blocks and stacked in the direction X.
As shown in
The operation of the configuration shown in
The latch signal SLA (first latch signal in a broad sense) falls in response to the selection of the wordline WL1 in the same manner as in the timing chart shown in
The above description also applies to the sense amplifier blocks 210-3 and 210-4. Specifically, data stored in the memory cell group MCS13 is latched by the data line driver cell 110A1-G, and data stored in the memory cell group MCS14 is latched by the data line driver cell 110A2-G.
When the wordline WL2 is selected, the latch signal SLB (an Nth latch signal in a broad sense) falls in response to the selection of the wordline WL2. The latch signal SLB is supplied to the data line driver 100B1 including the data line driver cell 110B1-R and the data line driver 100B2 including the data line driver cell 110B2-R. Therefore, G-bit data (data stored in the memory cell group MCS21) output from the sense amplifier block 210-1 in response to the selection of the wordline WL2 is latched by the data line driver cell 110B1-R. Likewise, G-bit data (data stored in the memory cell group MCS22) output from the sense amplifier block 210-2 in response to the selection of the wordline WL2 is latched by the data line driver cell 110B2-R. A data line driver cell 110A1-B is a B data line driver cell which latches B subpixel data.
The above description also applies to the sense amplifier blocks 210-3 and 210-4 when the wordline WL2 is selected. Specifically, data stored in the memory cell group MCS23 is latched by the data line driver cell 110B1-G and data stored in the memory cell group MCS24 is latched by the data line driver cell 110B2-G.
In
The latch signal SLA falls in response to selection of the wordline WL1. The latch signal SLA is supplied to the data line drivers 101A1, 101A2, and 101A3 in the same manner as described above.
According to this configuration, data stored in the memory cell group MCS11 is stored in the data line driver cell 111A1 as R subpixel data upon selection of the wordline WL1, for example. Likewise, data stored in the memory cell group MCS12 is stored in the data line driver cell 111A2 as G subpixel data, and data stored in the memory cell group MCS13 is stored in the data line driver cell 111A3 as B subpixel data, for example.
Therefore, the data written into the RAM 200 can be arranged in the order of R subpixel data, G subpixel data, and B subpixel data along the direction Y, as shown in Is
3. RAM
3.1 Memory Cell
3.1.1 Configuration of Memory Cell
Each memory cell MC may be formed by a static random access memory (SRAM), for example.
As shown in
The vertical memory cell MC includes the wordline WL formed in the layer (e.g. third metal layer) higher than the bitline. The wordline WL is formed to extend along the direction DR2 (second direction in a broad sense). Two first power supply interconnects VSSL1 and VSSL2 are formed in the same layer as the wordline WL along the direction DR2 (second direction in a broad sense). The voltage VSS is supplied to the inverter INV of the memory cell MC through the first power supply interconnect VSSL.
As shown in
3.1.2 Shield Interconnect of Memory Cell
When a sense amplifier enable signal SAE which enables the sense amplifier 211 rises as indicated by A13 shown in
The data held by the memory cell MC can be accurately detected as described above.
As indicated by A15 shown in
When the sense amplifier enable signal SAE then rises, the potential difference between the bitlines BL and /BL is detected by the sense amplifier 211. However, the potential of the bitline /BL, which has risen as indicated by A18, does not fall to a level lower than the potential of the bitline BL as indicated by A19. As a result, the potential difference is detected by the sense amplifier 211 in a state in which the potential of the bitline /BL is higher than the potential of the bitline BL.
Therefore, the sense amplifier 211 determines that the potential of the bitline BL is lower than the potential of the bitline /BL to detect data “0”. Specifically, data “0” is detected from the memory cell MC from which data “1” should be originally detected.
In the embodiment, the above-described abnormal reading can be prevented by providing a shield interconnect SHD1 (bitline protection interconnect in a broad sense) to the horizontal memory cell MC, as shown in
The shield interconnect SHD1 is an interconnect formed in the shield layer 290 shown in
The shield interconnect SHD1 is formed to extend along the direction DR1 in which the bitlines BL and /BL extend. As shown in
The shield interconnect non-formation regions NSH1 and NSH2 shown in
The shield interconnect SHD 1 shown in
It is preferable to set the shield interconnects SHD2 at a constant potential rather than a floating potential so as to exert a shielding effect. Therefore, it is preferable that the shield interconnect SDH2 be provided with a potential VDD or VSS or connected with the first power supply interconnects VSSL1 and VSSL2 or the second power supply interconnect VDDL.
When using the horizontal cell shown in
In the example shown in
The shield interconnect non-formation regions NSH may be formed along the wordline WL by dividing the shield interconnect SHD2 shown in
When using the horizontal memory cell shown in
When using the vertical memory cell shown in
3.2 Relationship Between Horizontal Cell and Sense Amplifier
As an advantage of using the horizontal cell, an increase in the degrees of freedom of the length MCY of the RAM 200 in the direction Y can be given. Since the length of the horizontal cell in the direction Y can be adjusted, a cell layout having a ratio of the length in the direction Y to the length in the direction X of 2:1 or 1.5:1 may be provided. In this case, when the number of horizontal cells arranged in the direction Y is set at 100, the length MCY of the RAM 200 in the direction Y can be designed in various ways by using the above-mentioned ratio.
On the other hand, when using the vertical cell shown in
3.3 Common Use of Sense Amplifier for Vertical Cells
As shown in
To deal with this problem, the memory cells MC for a plurality of bits (e.g. two bits) are associated with one sense amplifier 211 when selecting the wordline WL, as shown in
In
The switch circuit 220 connects one pair of bitlines BL and /BL with the sense amplifier 211 based on a select signal COLA (sense amplifier select signal in a broad sense). The switch circuit 230 connects the other pair of bitlines BL and /BL with the sense amplifier 211 based on a select signal COLB. The signal levels of the select signals COLA and COLB are controlled exclusively, for example. In more detail, when the select signal COLA is set as a signal which sets the switch circuit 220 to active, the select signal COLB is set as a signal which sets the switch circuit 230 to inactive. Specifically, the selective sense amplifier SSA selects 1-bit data from 2-bit (N-bit or L-bit in a broad sense) supplied through the two pairs of bitlines BL and /BL, and outputs the corresponding data, for example.
As a result, when using the vertical cell in which the length MCX of the memory cell MC is greater than the length MCY, an increase in the size of the RAM 200 in the direction X can be prevented by reducing the number of memory cells MC arranged in the direction X.
3.4 Read Operation from Vertical Memory Cell
The operation of the RAM 200 in which the vertical memory cells shown in
The select signal COLA is set to active at a timing B1 shown in
The select signal COLB is set to active at a timing B4, and the wordline WL1 is selected at a timing B5. In this case, since the select signal COLB is active, the selective sense amplifier SSA detects and outputs data stored in the B-side memory cell MC, that is, the memory cell MC-1B. When the latch signal SLB falls at a timing B6, the data line driver cell 110B-R latches the data stored in the memory cell MC-1B. In
The data latch operation of the data line driver 100 by reading data twice in the 1H period is completed in this manner.
The data latch operation of the data line driver 100 by reading data twice in the 1H period differing from the 1H period shown in
According to such a read method, data is stored in each memory cell MC of the RAM 200 as shown in
As shown in
In the read method shown in
The above description discloses that each selective sense amplifier SSA receives data from two of the memory cells MC selected by one wordline selection. However, the invention is not limited thereto. For example, each selective sense amplifier SSA may receive N-bit data from N memory cells MC of the memory cells MC selected by one wordline selection. In this case, the selective sense amplifier SSA selects 1-bit data received from a first memory cell MC of first to Nth memory cells MC (N memory cells MC) upon first selection of a single wordline. The selective sense amplifier SSA selects 1-bit data received from the Kth memory cell MC upon Kth (1≦K≦N) selection of the wordline.
As a modification of
In this case, each RAM block 200 outputs M-bit (M is an integer larger than 1) data upon one wordline selection. When the number of data lines DL of the display panel 10 is denoted by DLN, the number of grayscale bits of each pixel corresponding to each data line is denoted by G, and the number of RAM blocks 200 is denoted by BNK, the value M is given by the following equation:
The other control method is described below with reference to
The select signal COLA is set to active at a timing C1 shown in
The wordline WL2 is selected at a timing C4 so that the memory cells MC-2A and MC-2B are selected. In this case, since the select signal COLA is active, the selective sense amplifier SSA detects and outputs data stored in the A-side memory cell MC, that is, the memory cell MC-2A. When the latch signal SLB falls at a timing C5, the data line driver cell 110B-R latches the data stored in the memory cell MC-2A.
The data latch operation of the data line driver 100 by reading data twice in the 1H period is completed in this manner.
The read operation in the 1H period differing from the 1H period shown in
The wordline WL2 is selected at a timing C9 so that the memory cells MC-2A and MC-2B are selected. In this case, since the select signal COLB is active, the selective sense amplifier SSA detects and outputs data stored in the B-side memory cell MC, that is, the memory cell MC-2B. When the latch signal SLB falls at a timing C10, the data line driver cell 110B-R latches the data stored in the memory cell MC-2B.
The data latch operation of the data line driver 100 by reading data twice in the 1H period differing from the 1H period shown in
According to such a read method, data is stored in each memory cell MC of the RAM 200 as shown in
Data RB-1A to RB-6A and data RB-1B to RB-6B are 6-bit R subpixel data to be supplied to the data line driver cell 110B-R. The data RB-1A to RB-6A is R subpixel data in the 1H period shown in
As shown in
The data RA-1A (data latched by the data line driver 100A in the 1H period shown in
In the read method shown in
In the embodiment, the wordline WL is controlled by the wordline control circuit 240 shown in
3.5 Arrangement of Data Read Control Circuit
The row decoders 240 control the wordlines WL of the RAMs 200A and 200B based on signals from the CPU/LCD control circuit 250. Since data read control from each of the two memory cell arrays 200A and 200B to the LCD is performed by the row decoder 240 and the CPU/LCD control circuit 250, the row decoder 240 and the CPU/LCD control circuit 250 serve as a data read control circuit in a broad sense. The CPU/LCD control circuit 250 controls the two row decoders 240, two output circuits 260, two CPU write/read circuits 280, and one column decoder 270 based on control by an external host, for example.
The two CPU write/read circuits 280 write data from the host into the memory cell arrays 200A and 220B, or read data stored in the memory cell arrays 200A and 220B and output the data to the host based on signals from the CPU/LCD control circuit 250. The column decoder 270 controls selection of the bitlines BL and /BL of the memory cell arrays 200A and 200B based on signals from the CPU/LCD control circuit 250.
The output circuit 260 includes a plurality of sense amplifiers 211 to which 1 -bit data is respectively input as described above, and outputs M-bit data output from each of the memory cell arrays 200A and 200B upon selection of two different wordlines WL in the 1H period to the data line driver 100, for example. When four RAMs 200 are provided as shown in
Since the number of bits M read at one reading is reduced by reading data from each of the memory cell arrays 200A and 200B twice in the 1H period, the size of the column decoder 270 and the CPU write/read circuit 280 is halved. When two RAMs 200 are adjacent to each other as shown in
When using the horizontal cells shown in
4. Modification
In the modification shown in
In the modification shown in
When the wordline WL2 is selected, the data line driver 100-G latches data output from the RAM 200 in response to the selection of the wordline WL2. This causes data stored in the memory cell group MCS32 to be latched by the data line driver 100-G1, for example.
When the wordline WL3 is selected, the data line driver 100-B latches data output from the RAM 200 in response to the selection of the wordline WL3. This causes data stored in the memory cell group MCS33 to be latched by the data line driver 100-B1, for example.
The above description also applies to the memory cell groups MCS34, MCS35, and MCS36. Data stored in the memory cell groups MCS34, MCS35, and MCS36 is respectively stored in the data line driver cells 110-R2, 110-G2, and 110-B2, as shown in
The wordline WL2 is selected at a timing D3, and the data line driver 100-G latches data from the RAM 200 at a timing D4. This causes data output by the selection of the wordline WL2 to be latched by the data line driver 100-G The wordline WL3 is selected at a timing D5, and the data line driver 100-B latches data from the RAM 200 at a timing D6. This causes data output by the selection of the wordline WL3 to be latched by the data line driver 100-B.
According to the above-described operation, data is stored in the memory cells MC of the RAM 200 as shown in
For example, the data R1-1 to R1-6 is stored in the memory cell group MCS31 shown in
For example, the data stored in the memory cell groups MCS31 to MCS33 may be considered to be data for one pixel, and is data for driving the data lines differing from the data lines corresponding to the data stored in the memory cell groups MCS34 to MSC36. Therefore, data in pixel units can be sequentially written into the RAM 200 along the direction Y.
Among the data lines provided in the display panel 10, the data line corresponding to the R subpixel is driven, the data line corresponding to the G subpixel is then driven, and the data line corresponding to the B subpixel is then driven. Therefore, since all the data lines corresponding to the R subpixels have been driven even if a delay occurs in each reading when reading data three times in the 1H period, for example, the area of the region in which an image is not displayed due to the delay is reduced. Therefore, deterioration of display such as a flicker can be reduced.
5. Effect of the Embodiment
In the embodiment, the shield interconnects SHD2 are formed in the RAM 200 as shown in
The shield interconnect SHD2 is formed along the direction X, as shown in
Moreover, since the shield interconnect non-formation region NSH2 can be formed in a layer above the bitlines BL and /BL in the region in which the bitlines BL and /BL are not formed as shown in
In the embodiment, data is read from the RAM 200 a plurality of times in the 1H period, as described above. Therefore, the number of memory cells MC connected with one wordline can be reduced, or the data line driver 100 can be divided. For example, since the number of memory cells MC corresponding to one wordline can be adjusted by changing the number of readings in the 1H period, the length RX in the direction X and the length RY in the direction Y of the RAM 200 can be appropriately adjusted. Moreover, the number of divisions of the data line driver 100 can be changed by adjusting the number of readings in the 1H period.
Moreover, the number of blocks of the data line driver 100 and the RAM 200 can be easily changed or the layout size of the data line driver 100 and the RAM 200 can be easily changed corresponding to the number of data lines provided in the display region 12 of the drive target display panel 10. Therefore, the display driver 20 can be designed while taking other circuits provided to the display driver 20 into consideration, whereby design cost of the display driver 20 can be reduced. For example, when only the number of data lines is changed corresponding to the design change in the drive target display panel 10, the major design change target may be the data line driver 100 and the RAM 200. In this case, since the layout size of the data line driver 100 and the RAM 200 can be flexibly designed in the embodiment, a known library may be used for other circuits. Therefore, the embodiment enables effective utilization of the limited space, whereby design cost of the display driver 20 can be reduced.
In the embodiment, since data is read a plurality of times in the 1H period, M×2 memory cells MC can be provided in the direction Y of the RAM 200 to which M-bit data is output by the sense amplifier SSA as shown in
In the display driver 24 of the comparative example shown in
In the embodiment, the wordlines WL1 and WL2 and the like are formed to extend along the direction Y as shown in
When the 4BANK RAMs 200 are provided as shown in
In more detail, the same data line control signal SLC (data line driver control signal) is supplied to the data line drivers 100-1 to 100-4, and the same wordline control signal RAC (RAM control signal) is supplied to the RAMs 200-1 to 200-4, as shown in
Therefore, the wordline of the RAM 200 is selected similarly in each BANK, and the latch signals SLA and SLB supplied to the data line driver 100 fall similarly. Specifically, the wordline of one RAM 200 and the wordline of another RAM 200 are selected at the same time in the 1H period. This enables the data line drivers 100 to drive the data lines normally.
Although only some embodiments of the invention have been described in detail above, those skilled in the art will readily appreciate that many modifications are possible in the embodiments without departing from the novel teachings and advantages of this invention. Accordingly, all such modifications are intended to be included within the scope of this invention. For example, the terms mentioned in the specification or the drawings at least once together with different terms in a broader sense or a similar sense may be replaced with the different terms in any part of the specification or the drawings.
In the embodiment, image data for one display frame can be stored in the RAMs 200 provided in the display driver 20, for example. However, the invention is not limited thereto.
The display panel 10 may be provided with k (k is an integer larger than 1) display drivers, and 1/k of the image data for one display frame may be stored in each of the k display drivers. In this case, when the total number of data lines DL for one display frame is denoted by DLN, the number of data lines driven by each of the k display drivers is DLN/k.
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