Patent Grant
7388803
Japanese Patent Application No. 2005-193017, filed on Jun. 30, 2005, is hereby incorporated by reference in its entirety.
The present invention relates to an integrated circuit device and an electronic instrument.
In recent years, an increase in resolution of a display panel provided in an electronic instrument has been demanded accompanying a widespread use of electronic instruments. Therefore, a driver circuit which drives a display panel is required to have high performance. However, since many types of circuits are necessary for a high-performance driver circuit, the circuit scale and the circuit complexity tend to be increased in proportion to an increase in resolution of a display panel. Therefore, since it is difficult to reduce the chip area of the driver circuit while maintaining the high performance or providing an additional function, manufacturing cost cannot be reduced.
A high-resolution display panel is also provided in a small electronic instrument, and high performance is demanded for its driver circuit. However, since a small electronic instrument is limited in space, the circuit scale cannot be increased to a large extent. Therefore, since it is difficult to reduce the chip area while providing high performance, a reduction in manufacturing cost or provision of an additional function is difficult.
The invention disclosed in JP-A-2001-222276 cannot solve the above-described problems.
A first aspect of the invention relates to an integrated circuit device, comprising:
a RAM block including a plurality of wordlines, a plurality of bitlines, a plurality of memory cells, and a wordline control circuit; and
a data line driver block which drives a plurality of data line groups of a display panel based on data supplied from the RAM block,
wherein the data line driver block includes first to Nth (N is an integer larger than one) divided data line driver blocks, each of the first to Nth divided data line driver blocks driving a different data line group of the data line groups,
wherein the wordline control circuit drives an identical wordline N times from among the wordlines in one horizontal scan period of the display panel, and
wherein the first to Nth divided data line drivers are disposed along a first direction in which the bitlines extend.
A second aspect of the invention relates to an integrated circuit device, comprising:
a RAM block including a plurality of wordlines, a plurality of bitlines, a plurality of memory cells, and a wordline control circuit; and
a data line driver block which drives a plurality of data line groups of a display panel based on data supplied from the RAM block,
wherein the data line driver block includes first to Nth (N is an integer larger than one) divided data line driver blocks, each of the first to Nth divided data line driver blocks driving a different data line group of the data line groups,
wherein the wordline control circuit controls (L×J=N) times of reading of data from the RAM block in one horizontal scan period of the display panel, by selecting an identical wordline L times (L is an integer larger than one) and J wordlines (J is an integer larger than one) as the identical wordline selected L times in the one horizontal scan period, and
wherein the first to Nth divided data line drivers are disposed along a first direction in which the bitlines extend.
A third aspect of the invention relates to an integrated circuit device, comprising:
a RAM block including a plurality of wordlines, a plurality of bitlines, a plurality of memory cells, and a wordline control circuit; and
a data line driver block which drives a plurality of data line groups of a display panel based on data supplied from the RAM block,
wherein the data line driver block includes first to Nth (N is an integer larger than one) divided data line driver blocks, each of the first to Nth divided data line driver blocks driving a different data line group of the data line groups,
wherein the wordline control circuit sequentially selects N (N is an integer larger than one) different wordlines in one horizontal scan period of the display panel, and selects an identical wordline at least L times (L is an integer larger than one) in one vertical scan period of the display panel; and
wherein the first to Nth divided data line drivers are disposed along a first direction in which the bitlines extend.
A fourth aspect of the invention relates to an electronic instrument, comprising:
the above integrated circuit device; and
a display panel.
The invention may provide an integrated circuit device which allows a flexible circuit arrangement to enable an efficient layout, and an electronic instrument including the same.
An embodiment of the invention provides an integrated circuit device, comprising:
a RAM block including a plurality of wordlines, a plurality of bitlines, a plurality of memory cells, and a wordline control circuit; and
a data line driver block which drives a plurality of data line groups of a display panel based on data supplied from the RAM block,
wherein the data line driver block includes first to Nth (N is an integer larger than one) divided data line driver blocks, each of the first to Nth divided data line driver blocks driving a different data line group of the data line groups,
wherein the wordline control circuit drives an identical wordline N times from among the wordlines in one horizontal scan period of the display panel, and
wherein the first to Nth divided data line drivers are disposed along a first direction in which the bitlines extend.
According to the embodiment, since the data line driver block includes the divided data line drivers disposed along the first direction, the data line driver block can be efficiently arranged. As the resolution of the display panel is increased, the number of data lines is increased. In the embodiment, since the data line driver block can be configured by the divided data line drivers, the data line driver block can be efficiently arranged in the integrated circuit device even when driving a high-resolution display panel. Therefore, the chip area of the integrated circuit device can be reduced. Specifically, cost can be reduced. Moreover, since the width of the data line driver block can be adjusted to coincide with the width of the RAM block in the direction in which the wordlines extend, the data line driver block and the RAM block can be efficiently arranged in the integrated circuit device, whereby cost can be reduced.
With this embodiment, first to Nth latch signals may be supplied to the first to Nth divided data line drivers, respectively, and
the first to Nth divided data line drivers may latch data supplied from the RAM block based on the first to Nth latch signals.
According to the embodiment, since the first to Nth divided data line drivers can latch data supplied from the RAM block based on the first to Nth latch signals, the data from the RAM block can be latched by the corresponding divided data line driver. This enables the data line driver block to drive the data line groups based on the data supplied from the RAM block.
With this embodiment, when the identical wordline is selected first time, the first latch signal may be set to active so that data supplied from the RAM block in response to the first selection is latched by the first divided data line driver, and
when the identical wordline is selected Kth time (1≦K≦N; K is an integer), the Kth latch signal may be set to active so that data supplied from the RAM block in response to the Kth selection is latched by the Kth divided data line driver.
This enables the data supplied from the RAM block upon Kth selection to be latched by the Kth divided data line driver corresponding to Nth wordline selection.
With this embodiment, the RAM block may include a sense amplifier circuit which outputs M-bit data (M is an integer larger than one) upon one wordline selection,
at least M×N memory cells may be arranged in the RAM block along a second direction in which the wordlines extend, and
(M×N)-bit data may be supplied to the sense amplifier circuit upon one wordline selection.
This enables the number of memory cells arranged in the RAM block along the direction in which the wordlines extend to be set at “M×N”, whereby the memory cells can be efficiently arranged in the direction in which the wordlines extend corresponding to the size of the circuit of the RAM block such as the sense amplifier circuit. Moreover, since the number of memory cells arranged in the RAM block along the direction in which the bitlines extend can be reduced, the width of the RAM block in the direction in which the bitlines extend can be reduced.
With this embodiment, the sense amplifier circuit may detect and output M-bit data of the (M×N)-bit data based on a sense amplifier select signal.
This enables M-bit data of the (M×N)-bit data to be supplied to the data line driver block.
With this embodiment, the sense amplifier circuit may include a plurality of selective sense amplifiers, and
each time the identical wordline is selected N times in the one horizontal scan period, each of the selective sense amplifiers may receive N-bit data from first to Nth memory cells of M×N memory cells connected with the selected wordline, and may detect and output 1-bit data from a Kth (1≦K≦N; K is an integer) memory cell of the first to Nth memory cells based on the sense amplifier select signal.
This enables the RAM block to supply data to the data line driver block in M bit units corresponding to each of the N times of wordline selection.
With this embodiment, the sense amplifier select signal may be set so that the selective sense amplifier detects and outputs data received from the first memory cell when the identical wordline is selected first time, and detects and outputs data received from the Kth memory cell when the identical wordline is selected Kth time.
Therefore, since the selective sense amplifier can output data received from the Kth memory cell upon Kth wordline selection, data stored in the M×N memory cells can be output to the data line driver block by selecting the wordlines N times.
With this embodiment, each of the first to Nth divided data line driver may drive one of the data line groups based on the M-bit data supplied from the RAM block, and
when a grayscale of a pixel corresponding to a data line is G bits, each of the first to Nth divided data line drivers may drive M/G data lines.
This enables the data line driver block to drive the N×M/G data lines.
With this embodiment, each of the first to Nth divided data line drivers may drive one of the data line groups based on the M-bit data supplied from the RAM block, and
when a grayscale of a pixel corresponding to a data line is G bits, each of the first to Nth divided data line drivers may include M/G data line driver cells, and
each of the M/G data line driver cells may drive one of the data lines.
This enables each data line driver cell to receive G-bit data, whereby the data line can be driven based on the grayscale G bits.
With this embodiment, the value “M/G” may be a multiple of three when the display panel performs a color display,
the M/G data line driver cells may include M/3G R data line driver cells, M/3G G data line driver cells and M/3G B data line driver cells, each of M/3G R data line driver cells driving a data line corresponding to an R pixel, each of M/3G G data line driver cells driving a data line corresponding to a G pixel, and each of M/3G B data line driver cells driving a data line corresponding to a B pixel, and
the M/G data line driver cells may be arranged so that the R data line driver cells, the G data line driver cells, and the B data line driver cells are alternately disposed.
This enables the data line driver cells to be disposed along the second direction, whereby the data line driver block can be efficiently arranged even if the divided data line drivers are disposed along the first direction.
With this embodiment, the value “N” may be a multiple of three when the display panel performs a color display,
the M/G data line driver cells in a first group when dividing the first to Nth divided data line drivers into three groups may include M/G R data line driver cells, each of which drives a data line corresponding to an R pixel,
the M/G data line driver cells in a second group may include M/G G data line driver cells, each of which drives a data line corresponding to a G pixel,
wherein the M/G data line driver cells in a third group may include M/G B data line driver cells, each of which drives a data line corresponding to a B pixel, and
wherein the M/G data line driver cells may be arranged along the second direction.
According to the embodiment, the data line driver block can sequentially latch data corresponding to the R pixel, data corresponding to the G pixel, and data corresponding to the B pixel, for example. Therefore, when the data line driver block drives the data lines immediately after latching the data, all the data lines corresponding to the R pixels are driven first, and the data lines corresponding to the G pixels and the B pixels are driven thereafter. Specifically, since consecutive data lines which are not temporarily driven do not occur even when one horizontal scan period is reduced due to an increase in resolution, whereby deterioration of the image quality can be prevented.
With this embodiment, each of the first to Nth divided data line drivers may include first to Sth (S is an integer larger than one) subdivided data line drivers into which the divided data line driver is subdivided,
when a grayscale of a pixel corresponding to a data line is G bits, each of the first to Sth subdivided data line drivers may include M/(G×S) data line driver cells, each of which drives one of the data lines, and
the first to Sth subdivided data line drivers may be disposed along the first direction.
This enables the divided data line drivers to be efficiently arranged, whereby the data line driver block can be efficiently arranged in the integrated circuit device.
With this embodiment, an identical latch signal of the first to Nth latch signals may be supplied to each of the first to Sth subdivided data line drivers.
This enables the subdivided data line drivers to be disposed along the first direction without complicating the control.
Another embodiment of the invention provides an integrated circuit device, comprising:
a RAM block including a plurality of wordlines, a plurality of bitlines, a plurality of memory cells, and a wordline control circuit; and
a data line driver block which drives a plurality of data line groups of a display panel based on data supplied from the RAM block,
wherein the data line driver block includes first to Nth (N is an integer larger than one) divided data line driver blocks, each of the first to Nth divided data line driver blocks driving a different data line group of the data line groups,
wherein the wordline control circuit controls (L×J=N) times of reading of data from the RAM block in one horizontal scan period of the display panel, by selecting an identical wordline L times (L is an integer larger than one) and J wordlines (J is an integer larger than one) as the identical wordline selected L times in the one horizontal scan period, and
wherein the first to Nth divided data line drivers are disposed along a first direction in which the bitlines extend.
Therefore, the number of different wordlines selected in one horizontal scan period can be set at J while selecting the wordlines L×J times in one horizontal scan period. Therefore, even if the number of times the wordline is selected in one horizontal scan period is increased, an increase of the number of wordlines in the RAM block can be reduced. Specifically, the width of the RAM block in the first direction can be reduced.
A further embodiment of the invention provides an integrated circuit device, comprising:
a RAM block including a plurality of wordlines, a plurality of bitlines, a plurality of memory cells, and a wordline control circuit; and
a data line driver block which drives a plurality of data line groups of a display panel based on data supplied from the RAM block,
wherein the data line driver block includes first to Nth (N is an integer larger than one) divided data line driver blocks, each of the first to Nth divided data line driver blocks driving a different data line group of the data line groups,
wherein the wordline control circuit sequentially selects N (N is an integer larger than one) different wordlines in one horizontal scan period of the display panel, and selects an identical wordline at least L times (L is an integer larger than one) in one vertical scan period of the display panel; and
wherein the first to Nth divided data line drivers are disposed along a first direction in which the bitlines extend.
Therefore, the identical wordline can be selected L times in one vertical scan period while selecting the wordlines N times in one horizontal scan period. Therefore, even if the number of times the wordline is selected in one horizontal scan period is increased, an increase of the number of wordlines in the RAM block can be reduced. Specifically, the width of the RAM block in the first direction can be reduced.
With this embodiment, the RAM block may include a sense amplifier circuit which outputs M-bit data (M is an integer larger than one) upon one wordline selection,
at least M×L memory cells may be arranged in the RAM block along a second direction in which the wordlines extend, and
(M×L)-bit data may be supplied to the sense amplifier circuit upon one wordline selection.
This enables the number of memory cells arranged in the RAM block along the direction in which the wordlines extend to be set at “M×L”, whereby the memory cells can be efficiently arranged in he direction in which the wordlines extend corresponding to the size of the circuit of the RAM block such as the sense amplifier circuit. Moreover, since the number of memory cells arranged in the RAM block along the direction in which the bitlines extend can be reduced, the width of the RAM block in the direction in which the bitlines extend can be reduced.
With this embodiment, the wordlines may be formed parallel to a direction in which the data lines of the display panel extend.
In the integrated circuit device according to the embodiment, the length of the wordline can be reduced without providing a special circuit, in comparison with the case where the wordline is formed perpendicularly to the data line. In the embodiment, a host may select one of the RAM blocks and control the wordline of the selected RAM block. Since the length of the wordline to be controlled can be reduced as described above, the integrated circuit device according to the embodiment can reduce power consumption during write control from the host.
A still further embodiment of the invention provides an electronic instrument, comprising:
the above integrated circuit device; and
a display panel.
With this embodiment, the integrated circuit device may be mounted on a substrate which forms the display panel.
Note that the embodiments described hereunder do not in any way limit the scope of the invention defined by the claims laid out herein. Note also that not all of the elements of these embodiments should be taken as essential requirements to the means of the present invention. In the drawings, sections indicated by the same symbols have the same meanings.
1. Display Driver
The display panel 10 includes the display region 12 having PX pixels in the direction X and PY pixels in the direction Y, for example. When the display panel 10 supports a QVGA display, PX is 240 and PY is 320 so that the display region 12 is displayed in 240×320 pixels. The number of pixels PX of the display panel 10 in the direction X coincides with the number of data lines in the case of a black and white display. In the case of a color display, one pixel is formed by three subpixels including an R subpixel (R pixel in a broad sense), a G subpixel (G pixel in a broad sense), and a B subpixel (B pixel, in a broad sense). Therefore, the number of data lines is “3×PX” in the case of a color display. Accordingly, the “number of pixels corresponding to the data lines” means the “number of subpixels in the direction X” in the case of a color display. The number of bits of each subpixel is determined corresponding to the grayscale. When the grayscale values of three subpixels are respectively G, the grayscale value of one pixel is 3G bits. When the subpixel represents 64 grayscales (six bits), the amount of data for one pixel is 6×3=18 bits.
The relationship between the number of pixels PX and the number of pixels PY may be PX>PY, PX<PY, or PX=PY.
The display driver 20 has a length CX in the direction X and a length CY in the direction Y. A long side IL of the display driver 20 having the length CX is parallel to a side PL1 of the display region 12 on the side of the display driver 20. Specifically, the display driver 20 is mounted on the display panel 10 so that the long side IL is parallel to the side PL1 of the display region 12.
The above-mentioned ratio “1:10” is merely an example. The ratio is not limited thereto. For example, the ratio may be 1:11 or 1:9.
In
In a display driver 22 shown in
On the other hand, since the display driver 20 of the embodiment is formed so that the length CX of the long side IL is equal to the length LX of the side PL1 of the display region 12 as shown in
In the embodiment, the display driver 20 is formed so that the length CX of the long side IL is equal to the length LX of the side PL1 of the display region 12. However, the invention is not limited thereto.
The distance DY can be reduced while achieving a reduction in the chip size by setting the length of the long side IL of the display driver 20 to be equal to the length LX of the side PL1 of the display region 12 and reducing the length of the short side IS. Therefore, manufacturing cost of the display driver 20 and manufacturing cost of the display panel 10 can be reduced.
The data lines of the display panel 10 are divided into a plurality of (e.g. four) blocks, and one data line driver 100 drives the data lines for one block.
It is possible to flexibly meet the user's needs by providing the block width ICY and disposing each circuit within the block width ICY. In more detail, since the number of data lines which drive the pixels is changed when the number of pixels PX of the drive target display panel 10 in the direction X is changed, it is necessary to design the data line driver 100 and the RAM 200 corresponding to such a change in the number of data lines. In a display driver for a low-temperature polysilicon (LTPS) TFT panel, since the scan driver 300 can be formed on the glass substrate, the scan line driver 300 may not be provided in the display driver 20.
In the embodiment, the display driver 20 can be designed merely by changing the data line driver 100 and the RAM 200 or removing the scan line driver 300. Therefore, since it is unnecessary to newly design the display driver 20 by utilizing the original layout, design cost can be reduced.
In
In
The length of the RAM 200 in the direction Y is set at RY. In the embodiment, the length RY is set to be equal to the block width ICY shown in
The RAM 200 having the length RY includes a plurality of wordlines WL and a wordline control circuit 240 which controls the wordlines WL. The RAM 200 includes a plurality of bitlines BL, a plurality of memory cells MC, and a control circuit (not shown in
Data is read from the memory cell MC of the RAM 200 by controlling the wordline WL, and the data read from the memory cell MC is supplied to the data line driver 100. Specifically, when the wordline WL is selected, data stored in the memory cells MC arranged along the direction Y is supplied to the data line driver 100.
A shield layer 290 is formed in the fourth metal interconnect layer ALD. This enables effects exerted on the memory cells MC of the RAM 200 to be reduced even if various interconnects are formed in the fifth metal interconnect layer ALE in the upper layer of the memory cells MC of the RAM 200. A signal interconnect for controlling the control circuit for the RAM 200, such as the wordline control circuit 240, may be formed in the fourth metal interconnect layer ALD in the region in which the control circuit is formed.
An interconnect 296 formed in the third metal interconnect layer ALC may be used as the bitline BL or a voltage VSS interconnect, for example. An interconnect 298 formed in the second metal interconnect layer ALB may be used as the wordline WL or a voltage VDD interconnect, for example. An interconnect 299 formed in the first metal interconnect layer ALA may be used to connect with each node formed in a semiconductor layer of the RAM 200.
The wordline interconnect may be formed in the third metal interconnect layer ALC, and the bitline interconnect may be formed in the second metal interconnect layer ALB, differing from the above-described configuration.
As described above, since various interconnects can be formed in the fifth metal interconnect layer ALE of the RAM 200, various types of circuit blocks can be arranged along the direction X as shown in
2. Data Line Driver
2.1 Configuration of Data Line Driver
The output circuit 104 is formed by an operational amplifier, for example. However, the invention is not limited thereto. As shown in
The data line driver cell 110 includes an output circuit 140, the DAC 120, and the latch circuit 130, for example. However, the invention is not limited thereto. For example, the output circuit 140 may be provided outside the data line driver cell 110. The output circuit 140 may be either the output circuit 104 shown in
When the grayscale data indicating the grayscales of the R subpixel, the G subpixel, and the B subpixel is set at G bits, G-bit data is supplied to the data line driver cell 110 from the RAM 200. The latch circuit 130 latches the G-bit data. The DAC 120 outputs the grayscale voltage through the output circuit 140 based on the output from the latch circuit 130. This enables the data line provided in the display panel 10 to be driven.
2.2 A Plurality of Readings in One Horizontal Scan Period
The display driver 24 selects the wordline WL once in the 1H period. The data line driver 105 latches data output from the RAM 205 upon selection of the wordline WL, and drives the data lines. In the display driver 24, since the wordline WL is significantly longer than the bitline BL as shown in
The RAM 205 shown in
In the embodiment, the RAM 205 may be divided into a plurality of blocks and disposed in a state in which the divided blocks are rotated at 90 degrees. For example, the RAM 205 may be divided into four blocks and disposed in a state in which the divided blocks are rotated at 90 degrees, as shown in
In the embodiment, the length RY of the RAM 200 in the direction Y can be reduced by reading data a plurality of times in the 1H period, as shown in
In the embodiment, the RAM 200 divided into blocks can be provided in the display driver 20 as described above. In the embodiment, the 4BANK RAMs 200 can be provided in the display driver 20, for example. In this case, data line drivers 100-1 to 100-4 corresponding to each RAM 200 drive the corresponding data lines DL as shown in
In more detail, the data line driver 100-1 drives a data line group DLS1, the data line driver 100-2 drives a data line group DLS2, the data line driver 100-3 drives a data line group DLS3, and the data line driver 100-4 drives a data line group DLS4. Each of the data line groups DLS1 to DLS4 is one of four blocks into which the data lines DL provided in the display region 12 of the display panel 10 are divided, for example. The data lines of the display panel 10 can be driven by providing four data line drivers 100-1 to 100-4 corresponding to the 4BANK RAM 200 and causing the data line drivers 100-1 to 100-4 to drive the corresponding data lines.
2.3 Divided Structure of Data Line Driver
In the embodiment, on the premise that data is read N times (e.g. twice) in one horizontal scan period in order to reduce the length RY of the RAM 200 shown in
A plurality of data line driver cells 110 are provided in each of the data line drivers 100A and 100B. In more detail, M/G data line driver cells 110 are provided in the data line drivers 100A and 100B. When performing a color display, M/3G R data line driver cells 110, M/3G R data line driver cells 110, and M/3G R data line driver cells 110 are provided in each of the data line drivers 100A and 100B.
For example, when the number of pixels PX is 240, the grayscale of the pixel is 18 bits, and the number of BANKs of the RAM 200 is four (4BANK), 1080 (=240×18÷4) bits of data must be output from each RAM 200 in the 1H period.
However, it is desired to reduce the length RY of the RAM 200 in order to reduce the chip area of the display driver 100. Therefore, the data line driver 100 is divided into the data line drivers 100A and 100B in the direction X, as shown in
The data line driver 100A drives a part of the data lines of the display panel 10. The data line driver 100B drives a part of the data lines of the display panel 10 other than the data lines driven by the data line driver 100A. As described above, the data line drivers 100A and 100B cooperate to drive the data lines of the display panel 10.
In more detail, the wordlines WL1 and WL2 are selected in the 1H period as shown in
A latch signal SLB falls at a timing A2. The latch signal SLB is supplied to the data line driver 100B, for example. The data line driver 100B latches M-bit data supplied from the RAM 200 in response to the falling edge of the latch signal SLB, for example.
In more detail, data stored in a memory cell group MCS1 (memory cells) is supplied to the data line drivers 100A and 100B through a sense amplifier circuit 210 upon selection of the wordline WL1, as shown in
Upon selection of the wordline WL2, data stored in a memory cell group MCS2 (M memory cells) is supplied to the data line drivers 100A and 100B through the sense amplifier circuit 210. The latch signal SLB falls in response to the selection of the wordline WL2. Therefore, the data stored in the memory cell group MCS2 (M memory cells) is latched by the data line driver 100B.
For example, when M is set at 540 bits, 540-bit data (M=540) is latched by each of the data line drivers 100A and 100B, since the data is read twice in the 1H period. Specifically, 1080-bit data in total is latched by the data line driver 100 so that 1080 bits necessary for the above-described example can be latched in the 1H period. Therefore, the amount of data necessary in the 1H period can be latched, and the length RY of the RAM 200 can be approximately halved. This enables the block width ICY of the display driver 20 to be reduced, whereby manufacturing cost of the display driver 20 can be reduced.
The outputs of the data line drivers 100A and 100B may be caused to rise based on control by using a data line enable signal (not shown) or the like as indicated by A3 and A4 shown in
When the number of pixels PY is 320 (the number of scan lines of the display panel 10 is 320) and 60 frames are displayed within one second, the 1H period is about 52 μsec as shown in
The value M can be obtained by using the following equation. BNK indicates the number of BANKs, N indicates the number of readings in the 1H period, and G indicates the number of grayscale bits. The number of pixels PX×3 means the number of pixels DN corresponding to the data lines of the display panel 10.
In the embodiment, the sense amplifier circuit 210 has a latch function. However, the invention is not limited thereto. For example, the sense amplifier circuit 210 need not have a latch function.
2.4 Subdivision of Data Line Driver
When the grayscale G bits of each subpixel are set at six bits (64 grayscales), 6-bit data is supplied from the RAM 200 to data line driver cells 110A-R and 110B-R for the R subpixel. In order to supply the 6-bit data, six sense amplifiers 211 among the sense amplifiers 211 included in the sense amplifier circuit 210 of the RAM 200 correspond to each data line driver cell 110, for example.
For example, it is necessary that a length SCY of the data line driver cell 110A-R in the direction Y be within a length SAY of the six sense amplifiers 211 in the direction Y. Likewise, it is necessary that the length of each data line driver cell in the direction Y be within the length SAY of the six sense amplifiers 211. When the length SCY cannot be set within the length SAY of the six sense amplifiers 211, the length of the data line driver 100 in the direction Y becomes greater than the length RY of the RAM 200, whereby the layout efficiency is decreased.
The size of the RAM 200 has been reduced in view of the process, and the sense amplifier 211 is also small. As shown in
In the embodiment, the data line drivers 100A and 100B divided by the number of readings N in the 1H period may be further divided into S (S is an integer larger than one) blocks and stacked in the direction X.
As shown in
The operation of the configuration shown in
The latch signal SLA (first latch signal in a broad sense) falls in response to the selection of the wordline WL1 in the same manner as in the timing chart shown in
The above description also applies to the sense amplifier blocks 210-3 and 210-4. Specifically, data stored in the memory cell group MCS13 is latched by the data line driver cell 110A1-G (G data line driver cell in a broad sense), and data stored in the memory cell group MCS14 is latched by the data line driver cell 110A2-G (G data line driver cell in a broad sense).
When the wordline WL2 is selected, the latch signal SLB (second latch signal in a broad sense) falls in response to the selection of the wordline WL2. The latch signal SLB is supplied to the data line driver 100B1 including the data line driver cell 110B1-R and the data line driver 100B2 including the data line driver cell 110B2-R. Therefore, G-bit data (data stored in the memory cell group MCS21) output from the sense amplifier block 210-1 in response to the selection of the wordline WL2 is latched by the data line driver cell 110B1-R. Likewise, G-bit data (data stored in the memory cell group MCS22) output from the sense amplifier block 210-2 in response to the selection of the wordline WL2 is latched by the data line driver cell 110B2-R.
The above description also applies to the sense amplifier blocks 210-3 and 210-4 when the wordline WL2 is selected. Specifically, data stored in the memory cell group MCS23 is latched by the data line driver cell 110B1-G and data stored in the memory cell group MCS24 is latched by the data line driver cell 110B2-G A data line driver cell 110A1-B is a B data line driver cell which latches B subpixel data.
The R data line driver cell, the G data line driver cell, and the B data line driver cell are arranged in each of the data line drivers 100A and 100B along the direction Y (second direction in a broad sense).
In
The latch signal SLA falls in response to selection of the wordline WL1. The latch signal SLA is supplied to the data line drivers 101A1, 100A2, and 101A3 in the same manner as described above.
According to this configuration, data stored in the memory cell group MCS11 is stored in the data line driver cell 111A1 as R subpixel data upon selection of the wordline WL1, for example. Likewise, data stored in the memory cell group MCS12 is stored in the data line driver cell 111A2 as G subpixel data, and data stored in the memory cell group MCS13 is stored in the data line driver cell 111A3 as B subpixel data, for example.
Therefore, the data written into the RAM 200 can be arranged in the order of R subpixel data, G subpixel data, and B subpixel data along the direction Y, as shown in
3. RAM
3.1 Configuration of Memory Cell
Each memory cell MC may be formed by a static random access memory (SRAM), for example.
As shown in
In the memory cell MC, the length MCX along the bitlines BL and/BL is sufficiently greater than the length MCY along the main-wordline MWL and the sub-wordline SWL. In the embodiment, the memory cell MC having such a layout can be used for the RAM 200. However, the invention is not limited thereto. For example, the length MCY of the memory cell MC may be greater than the length MCX.
In the embodiment, the main-wordline MWL and the sub-wordline SWL are electrically connected at predetermined locations. This enables the resistance of the sub-wordline SWL to be reduced by using the main-wordline MWL which is the metal interconnect. In the embodiment, the main-wordline MWL and the sub-wordline SWL may be regarded as one wordline WL.
3.2. Common Use of Sense Amplifier
As shown in
In the embodiment, such memory cells MC can be efficiently arranged. As shown in
In
The switch circuit 220 connects one pair of bitlines BL and/BL with the sense amplifier 211 based on a select signal COLA (sense amplifier select signal in a broad sense). The switch circuit 230 connects the other pair of bitlines BL and/BL with the sense amplifier 211 based on a select signal COLB. The signal levels of the select signals COLA and COLB are controlled exclusively, for example. In more detail, when the select signal COLA is set to be a signal which sets the switch circuit 220 to active, the select signal COLB is set to be a signal which sets the switch circuit 230 to inactive. Specifically, the selective sense amplifier SSA selects 1-bit data from 2-bit data supplied through the two pairs of bitlines BL and/BL, and outputs the selected data, for example.
This prevents an increase in the size of the RAM 200 in the direction X, even if the length MCX of the memory cell MC is greater than the length MCY
3.3. Operation
The operation of the RAM 200 shown in
The select signal COLA is set to active at a timing B1 shown in
The select signal COLB is set to active at a timing B4, and the wordline WL1 is selected at a timing B5. In this case, since the select signal COLB is active, the selective sense amplifier SSA detects and outputs data stored in the B-side memory cell MC, that is, the memory cell MC-1B. When the latch signal SLB falls at a timing B6, the data line driver cell 110B-R latches the data stored in the memory cell MC-1B. In
The data latch operation of the data line driver 100 by reading data twice in the 1H period is completed in this manner.
The data latch operation of the data line driver 100 by reading data twice in the 1H period differing from the 1H period shown in
According to such a read method, data is stored in each memory cell MC of the RAM 200 as shown in
As shown in
In the read method shown in
The above description discloses that each selective sense amplifier SSA receives data from two of the memory cells MC selected by one wordline selection. However, the invention is not limited thereto. For example, each selective sense amplifier SSA may receive N-bit data from N memory cells MC of the memory cells MC selected by one wordline selection. In this case, the selective sense amplifier SSA selects 1-bit data received from a first memory cell MC of first to Nth memory cells MC (N memory cells MC) upon first selection of a single wordline. The selective sense amplifier SSA selects 1-bit data received from the Kth memory cell MC upon Kth (1≦K≦N) selection of the wordline.
As a modification of
The other control method is described below with reference to
The select signal COLA is set to active at a timing C1 shown in
The wordline WL2 is selected at a timing C4 so that the memory cells MC-2A and MC-2B are selected. In this case, since the select signal COLA is active, the selective sense amplifier SSA detects and outputs data stored in the A-side memory cell MC, that is, the memory cell MC-2A. When the latch signal SLB falls at a timing C5, the data line driver cell 110B-R latches the data stored in the memory cell MC-2A.
The data latch operation of the data line driver 100 by reading data twice in the 1H period is completed in this manner.
The read operation in the 1H period differing from the 1H period shown in
The wordline WL2 is selected at a timing C9 so that the memory cells MC-2A and MC-2B are selected. In this case, since the select signal COLB is active, the selective sense amplifier SSA detects and outputs data stored in the B-side memory cell MC, that is, the memory cell MC-2B. When the latch signal SLB falls at a timing C10, the data line driver cell 110B-R latches the data stored in the memory cell MC-2B.
The data latch operation of the data line driver 100 by reading data twice in the 1H period differing from the 1H period shown in
According to such a read method, data is stored in each memory cell MC of the RAM 200 as shown in
Data RB-1A to RB-6A and data RB-1B to RB-6B are 6-bit R subpixel data to be supplied to the data line driver cell 110B-R. The data RB-1A to RB-6A is R subpixel data in the 1H period shown in
As shown in
The data RA-1A (data latched by the data line driver 100A in the 1H period shown in
In the read method shown in
In the embodiment, the wordline WL is controlled by the wordline control circuit 240 shown in
3.4 Arrangement of Wordline Control Circuit
In the embodiment, when the number of memory cells arranged in the RAM 200 along the direction Y is “M×2”, the row decoder (wordline control circuit in a broad sense) 242 may be provided approximately in the middle of the RAM 200 in the direction Y, as shown in
As shown in
The CPU write/read circuits 280A and 280B write data from the host into the RAM 200, or read data stored in the RAM 200 and output the read data to the host based on signals from the CPU/LCD control circuit 250. The column decoders 270A and 270B control selection of the bitlines BL and/BL of the RAM 200 based on signals from the CPU/LCD control circuit 250.
The number of memory cells MC arranged in each of the RAMs 200A and 200B along the direction Y is not limited to M. For example, M−a (a is an arbitrary positive integer) memory cells MC may be arranged in the RAM 200A along the direction Y, and M+a memory cells MC may be arranged in the RAM 200B along the direction Y. The number of memory cells MC may be the reverse to that of this example.
Each of the output circuits 260A and 260B includes a plurality of selective sense amplifiers SSA, and outputs M-bit data in total output from the RAM 200A or 200B upon selection of the wordline WL1A or WL1B to the data line driver 100, for example.
In the embodiment, when two pairs of bitlines BL and/BL are connected with the selective sense amplifier SSA, M×2 memory cells are arranged in the RAM 200 along the direction Y, as shown in
However, this method makes it necessary to form the main-wordline MWL and the sub-wordline SWL in the memory cell MC. Moreover, wordline control becomes complicated by dividing the wordline into blocks, and an additional control circuit is required. Specifically, a reduction in design cost and manufacturing cost is hindered.
In the embodiment, the row decoder 242 is provided approximately in the middle of the RAM 200 in the direction Y. Moreover, since the length MCY of the memory cell MC is sufficiently smaller than the length MCX as shown in
The row decoder 242 controls selection of the wordlines WL of the RAMs 200A and 200B when outputting data to the data line driver 100, and controls selection of the wordline WL of one of the RAMs 200A and 200B when accessed from the host. This further reduces power consumption.
The AND circuits 242-2 and 242-3 may be provided in the row decoder 242, or may be provided in the RAMs 200A and 200B.
For example, when the row decoder 242 receives a wordline address WAD designated by the CPU/LCD control circuit 250, one of the coincidence detection circuits 242-1 performs coincidence detection. When the AND of signals input to the coincidence detection circuit 242-1 is logic “1”, the coincidence detection circuit 242-1 detects coincidence. The coincidence detection circuit 242-1 which has detected coincidence outputs a signal at a logic level “1” to a node ND, for example. The signal at a logic level “1” output to the node ND is supplied to the AND circuits 242-2 and 242-3.
As shown in
When selecting the wordline WL1B of the RAM 200B, the control signals R0 and/R0 are set in a pattern reverse to the above-described pattern, as shown in
Since the control signals R0 and/R0 are set at the H level (e.g. logic level “1”) during LCD output in which data is output to the data line driver 100, the wordlines of the RAMs 200A and 200B corresponding to the coincidence detection circuit 242-1 which has detected coincidence are selected.
As described above, since the row decoder 242 selects the wordline of the RAM 200A or 200B when accessed from the host, power consumption can be reduced.
3.5. Arrangement of Column Decoder
When the RAM 200 is disposed as shown in
Moreover, since a CPU/LCD control circuit 252 can be used in common by the RAM 200-1 and the RAM 200-2, the number of parts can be reduced. Therefore, the size of the CPU/LCD control circuit in the direction X can be reduced by using the CPU/LCD control circuit 252 shown in
As a result, a width BDX between the RAMs 200-1 and 200-2 in the direction X shown in
4. Modification
In the modification shown in
In the modification shown in
When the wordline WL2 is selected, the data line driver 100-G latches data output from the RAM 200 in response to the selection of the wordline WL2. This causes data stored in the memory cell group MCS32 to be latched by the data line driver 100-G1, for example.
When the wordline WL3 is selected, the data line driver 100-B latches data output from the RAM 200 in response to the selection of the wordline WL3. This causes data stored in the memory cell group MCS33 to be latched by the data line driver 100-B1, for example.
The above description also applies to the memory cell groups MCS34, MCS35, and MCS36. Data stored in the memory cell groups MCS34, MCS35, and MCS36 is respectively stored in the data line driver cells 110-R2, 110-G2, and 110-B2, as shown in
The wordline WL2 is selected at a timing D3, and the data line driver 100-G latches data from the RAM 200 at a timing D4. This causes data output by the selection of the wordline WL2 to be latched by the data line driver 100-G.
The wordline WL3 is selected at a timing D5, and the data line driver 100-B latches data from the RAM 200 at a timing D6. This causes data output by the selection of the wordline WL3 to be latched by the data line driver 100-B.
According to the above-described operation, data is stored in the memory cells MC of the RAM 200 as shown in
For example, the data R1-1 to R1-6 is stored in the memory cell group MCS31 shown in
For example, the data stored in the memory cell groups MCS31 to MCS33 may be considered to be data for one pixel, and is data for driving the data lines differing from the data lines corresponding to the data stored in the memory cell groups MCS34 to MSC36. Therefore, data in pixel units can be sequentially written into the RAM 200 along the direction Y.
Among the data lines provided in the display panel 10, the data line corresponding to the R subpixel is driven, the data line corresponding to the G subpixel is then driven, and the data line corresponding to the B subpixel is then driven. Therefore, since all the data lines corresponding to the R subpixels have been driven even if a delay occurs in each reading when reading data three times in the 1H period, for example, the area of the region in which an image is not displayed due to the delay is reduced. Therefore, deterioration of display such as a flicker can be reduced.
The modification illustrates the division into three blocks as an example. However, the invention is not limited thereto. When N is the multiple of three, ⅓ of the N divided data line drivers correspond to the first divided data line driver group, other ⅓ of the N divided data line drivers correspond to the second divided data line driver group, and the remaining ⅓ of the N divided data line drivers correspond to the first divided data line driver group.
5. Effect of Embodiment
Suppose that the length of the RAM 200 in the direction Y is set at RY when arranging the RAM 200 in the display driver 20 shown in
If the number of bits is increased accompanying an increase in resolution of the display panel, the length DDY1 of the data line driver 100 is further increased.
In the embodiment, the data line driver 100 can be divided into N divided data line drivers 100-1 to 100-N as shown in
In the embodiment, data is read from the RAM 200 a plurality of times in the 1H period, as described above. Therefore, the number of memory cells MC connected with one wordline can be reduced, or the data line driver 100 can be divided. For example, since the number of memory cells MC corresponding to one wordline can be adjusted by changing the number of readings in the 1H period, the length RX in the direction X and the length RY in the direction Y of the RAM 200 can be appropriately adjusted. Moreover, the number of divisions of the data line driver 100 can be changed by adjusting the number of readings in the 1H period.
Moreover, the number of blocks of the data line driver 100 and the RAM 200 can be easily changed or the layout size of the data line driver 100 and the RAM 200 can be easily changed corresponding to the number of data lines provided in the display region 12 of the drive target display panel 10. Therefore, the display driver 20 can be designed while taking other circuits provided to the display driver 20 into consideration, whereby design cost of the display driver 20 can be reduced. For example, when only the number of data lines is changed corresponding to the design change in the drive target display panel 10, the major design change target may be the data line driver 100 and the RAM 200. In this case, since the layout size of the data line driver 100 and the RAM 200 can be flexibly designed in the embodiment, a known library may be used for other circuits. Therefore, the embodiment enables effective utilization of the limited space, whereby design cost of the display driver 20 can be reduced.
In the embodiment, since data is read a plurality of times in the 1H period, M×2 memory cells MC can be provided in the direction Y of the RAM 200 from which M-bit data is output to the sense amplifiers SSA as shown in
In the display driver 24 of the comparative example shown in
In the embodiment, the wordlines WL1 and WL2 and the like are formed to extend along the direction Y as shown in
When the 4BANK RAMs 200 are provided as shown in
In more detail, the identical data line control signal SLC (data line driver control signal) is supplied to the data line drivers 100-1 to 100-4, and the identical wordline control signal RAC (RAM control signal) is supplied to the RAMs 200-1 to 200-4, as shown in
Therefore, the wordline of the RAM 200 is selected similarly in each BANK, and the latch signals SLA and SLB supplied to the data line driver 100 fall similarly. Specifically, the wordline of one RAM 200 and the wordline of another RAM 200 are selected at the same time in the 1H period. This enables the data line drivers 100 to drive the data lines normally.
In the embodiment, image data for one display frame can be stored in the RAMs 200 provided in the display driver 20, for example. However, the invention is not limited thereto.
The display panel 10 may be provided with k (k is an integer larger than one) display drivers, and 1/k of the image data for one display frame may be stored in each of the k display drivers. In this case, when the total number of data lines DL for one display frame is DLN, the number of data lines driven by each of the k display drivers is DLN/k.
Although only some embodiments of the invention have been described in detail above, those skilled in the art will readily appreciate that many modifications are possible in the embodiments without departing from the novel teachings and advantages of this invention. Accordingly, all such modifications are intended to be included within the scope of this invention. For example, the terms mentioned in the specification or the drawings at least once together with different terms in a broader sense or a similar sense may be replaced with the different terms in any part of the specification or the drawings.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2005-193017 | Jun 2005 | JP | national |
| Number | Name | Date | Kind |
|---|---|---|---|
| 5426603 | Nakamura et al. | Jun 1995 | A |
| 5490114 | Butler et al. | Feb 1996 | A |
| 5659514 | Hazani | Aug 1997 | A |
| 5739803 | Neugebauer | Apr 1998 | A |
| 5920885 | Rao | Jul 1999 | A |
| 6025822 | Motegi et al. | Feb 2000 | A |
| 6229753 | Kono et al. | May 2001 | B1 |
| 6246386 | Perner | Jun 2001 | B1 |
| 6324088 | Keeth et al. | Nov 2001 | B1 |
| 6421286 | Ohtani et al. | Jul 2002 | B1 |
| 6580631 | Keeth et al. | Jun 2003 | B1 |
| 6646283 | Akimoto et al. | Nov 2003 | B1 |
| 6724378 | Tamura et al. | Apr 2004 | B2 |
| 6731538 | Noda et al. | May 2004 | B2 |
| 6826116 | Noda et al. | Nov 2004 | B2 |
| 6862247 | Yamazaki | Mar 2005 | B2 |
| 6873310 | Matsueda | Mar 2005 | B2 |
| 6999353 | Noda et al. | Feb 2006 | B2 |
| 7078948 | Dosho | Jul 2006 | B2 |
| 7142221 | Sakamaki et al. | Nov 2006 | B2 |
| 7158439 | Shionoiri et al. | Jan 2007 | B2 |
| 7164415 | Ooishi et al. | Jan 2007 | B2 |
| 7176864 | Moriyama et al. | Feb 2007 | B2 |
| 7180495 | Matsueda | Feb 2007 | B1 |
| 7280329 | Kim et al. | Oct 2007 | B2 |
| 20020011998 | Tamura | Jan 2002 | A1 |
| 20020018058 | Tamura | Feb 2002 | A1 |
| 20040021947 | Schofield et al. | Feb 2004 | A1 |
| 20040239606 | Ota | Dec 2004 | A1 |
| 20050001846 | Shiono | Jan 2005 | A1 |
| 20050047266 | Shionori et al. | Mar 2005 | A1 |
| 20050057581 | Horiuchi et al. | Mar 2005 | A1 |
| 20050212788 | Fukuda et al. | Sep 2005 | A1 |
| 20050253976 | Sekiguchi et al. | Nov 2005 | A1 |
| 20070000971 | Kumagai et al. | Jan 2007 | A1 |
| 20070001886 | Ito et al. | Jan 2007 | A1 |
| 20070001968 | Kodaira et al. | Jan 2007 | A1 |
| 20070001969 | Kodaira et al. | Jan 2007 | A1 |
| 20070001970 | Kodaira et al. | Jan 2007 | A1 |
| 20070001971 | Kumagai et al. | Jan 2007 | A1 |
| 20070001972 | Kumagai et al. | Jan 2007 | A1 |
| 20070001973 | Kumagai et al. | Jan 2007 | A1 |
| 20070001974 | Kumagai et al. | Jan 2007 | A1 |
| 20070001975 | Kumagai et al. | Jan 2007 | A1 |
| 20070001982 | Ito et al. | Jan 2007 | A1 |
| 20070001983 | Ito et al. | Jan 2007 | A1 |
| 20070001984 | Kumagai et al. | Jan 2007 | A1 |
| 20070002061 | Kumagai et al. | Jan 2007 | A1 |
| 20070002062 | Kodaira et al. | Jan 2007 | A1 |
| 20070002063 | Kumagai et al. | Jan 2007 | A1 |
| 20070002188 | Kumagai et al. | Jan 2007 | A1 |
| 20070002509 | Kumagai et al. | Jan 2007 | A1 |
| 20070002667 | Kodaira et al. | Jan 2007 | A1 |
| 20070002670 | Kodaira et al. | Jan 2007 | A1 |
| 20070002671 | Kumagai et al. | Jan 2007 | A1 |
| 20070013074 | Kodaira et al. | Jan 2007 | A1 |
| 20070013634 | Saiki et al. | Jan 2007 | A1 |
| 20070013635 | Ito et al. | Jan 2007 | A1 |
| 20070013684 | Kodaira et al. | Jan 2007 | A1 |
| 20070013685 | Kodaira et al. | Jan 2007 | A1 |
| 20070013687 | Kodaira et al. | Jan 2007 | A1 |
| 20070013706 | Kodaira et al. | Jan 2007 | A1 |
| 20070013707 | Kodaira et al. | Jan 2007 | A1 |
| 20070016700 | Kodaira et al. | Jan 2007 | A1 |
| Number | Date | Country |
|---|---|---|
| A 11-261011 | Sep 1999 | JP |
| A-2001-067868 | Mar 2001 | JP |
| A 2001-222249 | Aug 2001 | JP |
| A 2001-222276 | Aug 2001 | JP |
| A-2002-358777 | Dec 2002 | JP |
| A 2004-146806 | May 2004 | JP |
| A 2004-328456 | Nov 2004 | JP |
| A-2005-17725 | Jan 2005 | JP |
| A 2005-72607 | Mar 2005 | JP |
| 10-2005-11743 | Jan 2005 | KR |
| Number | Date | Country | |
|---|---|---|---|
| 20070002669 A1 | Jan 2007 | US |
