The present invention relates generally to body biasing circuit solutions for systems including an integrated circuit (IC) device, and more particularly to body biasing circuit techniques that provide different body bias voltages to different blocks of an IC device.
Integrated circuit (IC) devices can include n-channel and p-channel transistors. In some IC devices, one or both types of transistors can be formed in wells. To increase the absolute value of the threshold voltage, the wells can be reverse biased (“back” biased). Thus, n-wells containing p-channel transistors can be reverse biased to a positive voltage greater than a high power supply for the transistors. Conversely, p-wells containing n-channel transistors can be reverse biased to a voltage more negative than their low source voltage (i.e., a voltage lower than ground).
Under certain operating conditions, IC devices can be subject to current transient events. Such events can result in a “droop” of a power supply voltage, which can slow the operation of some circuits. Conventionally, such circuits are designed with a timing “guard band”, at the cost of performance, to ensure proper operation in the event of a current transient event. Further, in some conventional approaches, in response to current transient events, the IC device can increase a reverse body bias voltage (increase the setting of a reverse body bias).
Various embodiments of the present invention will now be described in detail with reference to a number of drawings. The embodiments show integrated circuit devices, body bias control and generation circuits and related methods, including power up sequences. Body bias values can be varied between circuit blocks to vary (e.g., optimize) circuit block performance. According to some embodiments, in response to current transient events, body bias voltages for circuit blocks can be “collapsed” to lower body bias voltage levels.
In the various embodiments described below, like items are referred to with the same reference character but with the leading digits corresponding to the figure number.
Transistors receiving a body bias can also have a predetermined threshold voltage relationship with respect to a received power supply voltage. In some embodiments, transistors can have a threshold voltage setting that is less than or equal to 0.2V less than a supply voltage to the transistor.
Blocks (102-0 to 102-3) can include circuits of different types. According to particular embodiments, the blocks (102-0 to 102-3) can include but are not limited to any of: memory circuits; e.g., dynamic random access memory, (DRAM), static RAM (SRAM) or nonvolatile memory); processor circuits, e.g., one or more central processing units (CPUs), application PUs (APUs), graphic PUs (GPUs); application specific logic circuits; or analog circuits. Such different types of blocks can have transistors with different threshold voltages, and can have different responses to current transient events. In some embodiments, an IC device 100 can be a system-on-chip (SoC) type device, integrating processor circuits, memory circuits and other application specific circuits. In other embodiments, IC device 100 may be a system with one or more blocks segregated on individual die and assembled on one or more system boards.
IC device 100 includes a global body bias supply 110, which can provide one or more global body bias voltages (VBBG) to each block (102-0 to -3) via a global network 108. A global body bias supply 110 can be a voltage generating circuit, or can be an IC device connection (e.g., bond pad, pin, etc.) that receives an external voltage. A global body bias voltage generating circuit can generally include a charge pump circuit, a switched capacitor circuit, or a voltage regulator.
Each block (102-0 to -3) can include its own local bias circuit 112-0 to -3. Each local bias circuit (112-0 to -3) can generate one or more local body bias voltages (VBB0 to VBB3) from global body bias voltage(s) VBBG. Such local body bias voltages can be reverse body bias voltages that are applied to bodies of transistors within its block (102-0 to -3). Accordingly, body bias voltages for each block (102-0 to -3) can be tuned for the performance of the transistors within the block. Local body bias voltages (VBB0 to VBB3) can be static voltages, that generally do not change once the IC device is operational (but can vary between blocks) and/or can be dynamic voltages that change (e.g., change in response to an IC device mode or event).
According to some embodiments, local body bias voltages (VBB0 to VBB3) can have smaller settings than the global body bias voltage (VBBG) from which they are generated. For example, if a global body bias voltage is a positive voltage for p-channel transistors, corresponding local body bias voltages can have a lower positive voltage. Similarly, if a global body bias voltage is a negative voltage for n-channel transistors, corresponding local body bias voltages can have a higher voltage (i.e., can be less negative).
In the particular embodiment shown, each local bias circuit (112-0 to -3) can generate a local body bias voltage (VBB0 to VBB3) that varies in response to a control value (Ctrl0 to Ctrl3). Thus, a local body bias voltage (VBB0 to VBB3) can be set according to such a value. A control value (Ctrl0 to Ctrl3) can be an analog value or can be a digital value. In this way, a body bias voltage to each different section can be adjusted independently.
It is understood that any of the blocks (102-0 to -3) can include transistors without a reverse body bias voltage (i.e., transistors with bodies biased to a power supply level).
The various body bias connections shown in
Each collapse circuit (326-0 to -3) can selectively connect the bodies of transistors of its section to a “collapse” voltage. A collapse voltage can be a voltage having a setting less than the body bias voltage. In some embodiments, a collapse voltage can be a low power supply voltage level. As but one example, n-channel transistors can have a collapse voltage of zero volts (e.g., a low power supply level VSS), while p-channel transistors can have a collapse voltage of a high supply voltage (e.g., VDD, VCC). According to embodiments, collapse circuits (326-0 to -3) can collapse a body bias voltage to a collapse voltage in response to predetermined events. Such events can include events which can cause a current transient. In this way, a body bias voltage setting for transistors can be reduced in the event of a current transient event. This is in contrast to conventional approaches which either do not modify or can increase a body bias voltage setting in such cases.
In some embodiments, collapse circuits (326-0 to -3) can be programmable, being enabled in response to a selected set of events or modes of operation. In addition or alternatively, collapse circuits (326-0 to -3) can have a programmable delay between an event and the collapse operation.
As noted above, in very particular embodiments, such a tracking can be accomplished by having VBN collapse to VSS and VPB collapse to VDD.
As shown, reducing the setting of the reverse body bias can result in faster performance than maintaining the reverse body bias level. In this way, reducing a reverse body bias level during current transient events can increase performance, which can result in reduced guard-banding against such events.
A collapse circuit (626-0 to 626-n) can collapse body bias voltages to a set of transistors to a collapse voltage (VCollapse) as described herein, or equivalents. A collapse voltage (Vcollapse) can be static voltage or can be a dynamic voltage (e.g., a voltage that tracks power supply droop). In the embodiment shown, each collapse circuit (626-0 to 626-n) can collapse its body bias voltage in response to an enable signal (Coll_EN0 to Coll_ENn) generated by a corresponding event detect circuit (630-0 to -n).
Each event detect circuit (630-0 to -n) can activate its collapse enable signal (Coll_EN0 to Coll_ENn) in response to one or more predetermined conditions. Such conditions can include operations on an IC device and/or signals received from sources external to the IC device.
An event detect circuit 730 can also receive a block enable signal BLKEN as an input. A block enable signal BLKEN can enable a block 702 of the IC device. Enabling a block can include changing a state of the block, including from a “sleep” mode to an active mode. A block enable signal BLKEN can be for the block that includes the event detect circuit, or can be an entirely different block.
The embodiment of
The embodiment of
It is understood that embodiments can combine items of
A bias device 1036 can be a p-channel transistor having source and body connected to receive a global body bias value (Vglobal), a gate coupled to the output of amplifier 1038, and a drain connected to provide the body bias voltage (VBP) on body bias line 1044 (i.e., the drain is connected to one or more wells or other active regions containing p-channel transistors). A global body bias voltage (Vglobal) can be provided on a global body bias network 1008, which can provide such a value to multiple different blocks. In particular embodiments, a bias device 1036 can be a high voltage transistor (i.e., a transistor designed to withstand higher voltage levels than other transistors of the IC device, such as a thicker gate insulator, for example).
According to a difference between Vref and VBP, amplifier 1038 can drive bias device to raise or lower VBP with respect to Vglobal. In particular, as VBP falls below Vref, amplifier 1038 will increase the conductivity of bias device 1036 until VBP reaches a desired level.
A collapse circuit 1026 can include a collapse device 1040. A collapse device 1040 can drive VBP to a lower power supply level VDD in response to signal Coll_EN. A lower power supply (VDD) level can be lower than VBP.
To avoid large current draw through device 1036 (a contention state) the body bias control circuit may have a disable (not shown, but discussed for another embodiment below) asserted when Coll_EN is asserted. Alternatively, Vref may be set to the local VDD value during collapse events, which will also essentially turn off bias device 1036.
While embodiments can include continuous (e.g., analog) control of local reverse body bias voltages, alternate embodiments can include pulsed (e.g., digital) control of reverse body bias voltages.
Toggle logic 1150 can toggle between high and low values based on an output of comparator 1148. In the particular embodiment shown, toggle logic 1150 can be an SR type flip-flop circuit, with an output to level shifter 1152. Level shifter 1152 can shift output values from a lower voltage domain to a higher voltage domain. In the embodiment shown, level shifter 1152 can ensure a low value from toggle logic 1150 is driven to VGlobal. An output of level shifter 1152 can turn bias device 1136 off and on.
Bias device 1136 can be an n-channel transistor having source and body connected to VGlobal, a gate connected to receive the output of level shifter 1152 (Cx), and a drain connected to provide the body bias voltage (VBN) on body bias line 1144 (i.e., the drain is connected to one or more wells or other active regions containing n-channel transistors). A global body bias voltage (Vglobal) can be provided on a global body bias network 1108, which can provide such a value to multiple different blocks. Optional level shifter 1154 can shift a body bias voltage VBN to ensure compatibility with the common mode input range of comparator 1148. A bias device 1136 can be a high voltage transistor. The comparator may be continuous-time as shown, or clocked (i.e., a dynamic comparator).
If VBN is above a predetermined level, Vfb will be greater than Vref, and the output of comparator 1148 will be driven high. Toggle logic 1150 will drive level shifter 1152 accordingly, which will drive signal Cx high. This turns on the bias device 1136, resulting in the local body bias VBN being driven lower. Once VBN is above a predetermined level, Vfb will be below Vref, and the output of comparator 1148 will be driven low. By operation of toggle logic 1150 and level shifter 1152, signal Cx will be driven low, turning off bias device 1136. Thus, bias device 1136 can be continually turning on and off to maintain VBN at a desired level.
In some embodiments, the activation of a bias device (which establishes a body bias level from a global body bias) and the activation of a collapse device can be interlocked with one another. In particular, a bias device will be disabled when the corresponding collapse device is enabled. Particular examples of such embodiments will now be described.
Interlock logic 1256 can ensure that bias device 1240 is turned off whenever a collapse operation occurs (i.e., Coll_EN is high). Further, interlock logic 1256 can ensure that bias device 1240 is turned on only when there is no collapse operation (i.e., Coll_EN is low).
Bias control circuits for the p-wells (1328-0 to -n) can each include a digital-to-analog converter (DAC) 1358, amplifier 1338, bias device 1336, and collapse device 1340. DACs 1358 can receive input digital values from a local control circuit 1362, and from such values can generate reference voltages (VrefNwA to VrefNwZ). Amplifiers 1338 can have one input connected to receive the reference voltage (VrefNwA to VrefNwZ) and another input connected to the corresponding n-well (i.e., via 1334A to 1334Z). Output of amplifiers 1338 can control corresponding bias devices 1336. Bias devices 1336 can be p-channel transistors having source-drain paths connected between a global bias voltage VNwell_Global and their corresponding n-well. In such an arrangement, based on a difference between a reference voltage (VrefNwA to VrefNwZ) and a well voltage, the conductivity of the bias device 1336 can be varied to maintain the n-well at a desired bias voltage.
Collapse devices 1340 can be p-channel transistors having source-drain paths connected between the local power supply voltage (e.g., VDD) and their corresponding n-well. Activation of collapse devices 1340 can be controlled via signals from a collapse control circuit 1360.
Bias control circuits for the n-wells (1328-0′ to -n′) can have structures like those for the p-wells, but include n-channel bias devices 1336′ and collapse devices 1340′. Bias control circuits (1328-0′ to -n′) can operate in a similar fashion, varying the conductivity of the bias devices 1336′ according to a difference between a reference voltage (VrefPwA to VrefPwZ) and the voltage of their corresponding p-well. Reference voltages (VrefPwA to VrefPwZ) can be generated from digital values output from local control circuit 1362′. Collapse devices 1340′, when activated by collapse control circuit 1360, can collapse their corresponding well to the local power supply voltage (e.g., VSS).
Each event detect circuit can include local logic 1464-0 to -n, local delay 1466-0 to -n, global delay 1468-0 to -n, and output logic 1470-0 to -n. Local logic (1464-0 to -n) can combine signals corresponding to local events (i.e., events occurring on the block itself) (LOCAL EVENT0 to i). In the particular embodiment of
According to an embodiment, during the IC power up sequence, the charge pumps may not have time to drive the global bias values to their correct values. In this case, the core devices may be temporarily forward body biased, causing excessive power up currents. Consequently, one such GLOBAL EVENT may be the power up sequence, whereby the local body biases may be driven to the local supply voltages (applying zero body bias rather than forward body bias). When the supplies, including the global well biases, have been determined to be at their nominal voltages, the GLOBAL EVENT condition may be de-asserted to allow local well biases to be reverse biased, further reducing leakage currents.
While embodiments herein can include IC devices that generate local body bias voltages from global body bias voltages, embodiments can also include power-on sequences for such devices. A power-on sequence according to one particular embodiment is shown in
In one very particular embodiment, VHi_Max can be a power supply for a charge pump circuit that generates a global negative body bias used to generate VBPwell, and can have a level of about +3.3V. A positive reverse body bias (VBNwell) can be about +1.7V (which is greater than Vhi). A reverse body bias (VBPwell) can be about −0.9V. Vhi can be about +0.9V, and can be a supply voltage to p-channel transistors having the reverse body bias voltage VBNwell (of about +1.7V).
Referring still to
Local bias circuits (1612-0 to -n) can generate their local body bias voltages (VBN) from a negative global body bias voltage (VBPwell Global) provided to each block (1602-0 to -n) via a global network 1608. Local body bias voltages (VBN) can set with corresponding digital values (Dig. Ctrl). In a similar fashion, local bias circuits (1612-0′ to -n′) can generate their local body bias voltages (VBP) from a positive global body bias (VBNwell Global) provided to each block (1602-0 to -n) via a global network 1608′
In the embodiment shown, a negative global body bias voltage (VBPwell Global) can be provided from a global source 1610, which can include a charge pump circuit 1672 controlled by an oscillator circuit 1674. Charge pump circuit 1672 and oscillator circuit 1674 can operate at a voltage Vhi_Max, which can be an externally provided high supply voltage, such as the high voltage input-output (VDDIO) power supply.
A positive global body bias voltage (VBNwell Global) can be provided from global bias circuit 1610′, which in a particular embodiment can be DC-DC converter circuit, which can convert the voltage Vhi_Max, to a lower voltage level with high efficiency.
In a power up operation, Vhi_Max (e.g., ˜+3.3V) can be applied. A lower power supply voltage (e.g., ˜+0.9V) is not immediately enabled. In response to Vhi_Max, oscillator circuit 1674 can generate an oscillating signal as an input to charge pump circuit 1672. In response, the charge pump circuit 1672 can start to generate a negative global bias voltage (VBPwell Global). In response to negative global bias voltage (VBPwell Global), local bias circuits (1612-0 to -n) can generate their local body bias voltages (VBN).
At the same time, global source 1610′ can generate a positive global supply voltage (VBNwell Global) (e.g., ˜+2.2V) from the Vhi_Max voltage (e.g., ˜+3.3V). Once the high power supply voltage (VBNwell Global) is established, local bias circuits (1612-0′ to -n′) can generate their local body bias voltages (VBP).
After the local body bias voltages (VBN/VBP) are stable, a lower power supply voltage (e.g., ˜+0.9V) can then be enabled. Alternatively, the body biases may be pinned to the supply voltage so as not to apply forward body biases, until such time as the global body biases are stable.
Positive global supply 1710′ can be a DC-DC converter circuit that converts a high, positive power supply voltage (Vhi_Max) to a lower positive global bias voltage (VBNwell Global). In one particular embodiment, positive global supply 1710′ can be an LDO circuit that converts a voltage (Vhi_Max) of about +3.3V to a voltage (VBNwell Global) of about +2.2V.
The lower positive global bias voltage (VBNwell Global) can be provided by local bias circuits 1712′. In the particular embodiment shown, a local bias circuit 1712′ can generate a local body bias voltage (VBP/VBNwell Local) that varies according to a digital control value Dig. Ctrl0. Further, local bias control circuits 1712′ can be individually enabled or disabled according to an enable signal EN0. In one very particular embodiment, local bias circuits 1712′ can provide a local body bias voltage (VBP/VBNwell Local) that ranges from +2.0V to +0.6V.
Charge pump circuit 1772 can generate a negative global bias voltage (VBPwell Global). In one particular embodiment, charge pump 1772 can generate a negative global bias voltage (VBPwell Global) of about −1.0V, utilizing an oscillating signal of about 25 MHz and a power supply voltage of +3.3V.
The negative global bias voltage (VBPwell Global) can be provided local bias circuits 1712. In the particular embodiment shown, a local bias circuit 1712 can generate a local negative body bias voltage (VBN/VBPwell Local) that varies according to a digital control value Dig. Ctrln. Further, local bias control circuits 1712 can be individually enabled or disabled according to an enable signal ENn. In one very particular embodiment, local bias circuits 1712 can provide a local body bias voltage (VBN/VBPwell Local) that ranges from 0V to −0.8V.
Within the pump circuit, transistors P180/P181 can have sources and bodies commonly connected to a charge voltage Vcharge. Drains of transistors P180/181 can be cross coupled to their gates. Transistors N180/N181 can have sources and bodies commonly connected to an output node VBN_Source, which can provide the negative global supply voltage. Drains of transistors N180/181 can be cross coupled to their gates.
On one pump cycle, a polarity of signal applied to C181 from pump control logic 1876 can switch from high to low, and negative charge can be transferred to VBN_Source via transistor N181. In addition, a polarity of signal applied to C180 from pump control logic 1876 can switch from low to high, and transistor C180 can charge via transistor P180. On the next pump cycle, a polarity of signal applied to C180 can switch from high to low, and negative charge can be transferred to VBN_Source via transistor N180. The polarity of the signal applied to C180 can switch from low to high, and transistor C181 can charge via transistor P181.
Bias device 1936 can be an n-channel transistor having a source and body connected to receive a negative global bias voltage (VBPwell Global), a gate connected to the output of the comparator 1948, and a drain that provides the local body bias voltage (VBPwell Local).
As noted above, a programmable resistance circuit 1978 can be included in a feedback path between the local body bias voltage (VBPwell Local) and (+) input to the comparator 1948. A resistance presented by programmable resistance circuit 1978 can be established via a digital code (Code) applied via level shifter 1980. The level of the local body bias voltage (VBPwell Local) can be established with the digital code (Code).
If the local body bias voltage (VBPwell Local) is above a predetermined level which is set by the digital (Code), the (+) input to the comparator 1948 will be greater than Vref, and the output of comparator 1948 will be driven high, turning on bias device 1936, to pull the local body bias voltage (VBPwell Local) lower (i.e., toward VBPwell Global). Once the local body bias voltage (VBPwell Local) is below the predetermined level (again, set by the digital (Code)), the (+) input to the comparator 1948 will be greater than Vref, and the output of comparator 1948 will be driven low, turning off bias device 1936. Once the local body bias voltage (VBPwell Local) drifts high again, the bias device will be turned on. This repeats to maintain the local body bias voltage (VBPwell Local) within a desired range.
The output of the comparator 1948 can provide a control value NCtrl_Local, which can be used to control other bias devices. In the embodiment shown, the output of the comparator 1948 can be connected to the local body bias voltage (VBPwell Local) by a capacitor C190 and resistor R190.
Diode ladder 2082 can include a number of p-channel transistors connected in a “diode” fashion (gates connected to drains) in series with one another between a low power supply voltage (VSS) and high power supply voltage (Vhi_Max). Diode ladder 2082 provides a bias voltage for amplifier 2038.
Amplifier 2038 can have a (−) input connected to receive a reference voltage VREF, a (+) input connected to an output (VBNwell Global) via a feedback path that includes programmable resistance circuit 2078, and output that drives bias device 2036.
Bias device 2036 can be a p-channel transistor having a source and body connected to receive the power-up controlled high supply voltage Vhi_Max′, a gate connected to the output of amplifier 2038, and a drain that provides the positive global body bias voltage (VBNwell Global). Bias device and other constituent devices may be high voltage tolerant (e.g., thick-gate oxide).
In a manner like that of
The output of the amplifier 2038 can provide a global value PCtrl_Global, which can be used to control other bias devices. In the embodiment shown, the output of the amplifier 2038 can be connected to the global body bias voltage (VBNwell Global) by a capacitor C201 and resistor R201.
Bias device 2136 can be a p-channel transistor having a source and body connected to receive a positive global bias voltage (VBNwell Global), a gate connected to the output of the comparator 2148, and a drain that provides the local body bias voltage (VBPwell Local).
Local bias circuit 2112′ can operate in a manner similar to that of
The output of the comparator 2148 can provide a control value PCtrl_Local, which can be used to control other bias devices. In the embodiment shown, a capacitor C211 can be connected between the output of the comparator 2148 and a low power supply voltage (VSS).
Within blocks 2202-0/1/3 a negative global body bias voltage can be provided via a network 2208, while a positive global body bias voltage can be provided via a network 2208′. Blocks 2202-0/1 can also include local body bias circuits 2212, which can generate local negative body bias voltages for n-channel transistors from a global bias voltage on network 2208, as described in embodiments herein, or equivalents. Further, local body bias circuits 2212′ can generate local positive body bias voltages for p-channel transistors from a global body bias voltage on a network 2208′, as described in embodiments herein, or equivalents.
In
A body bias voltage VBB can be applied via a tap 2391 to the p-well 2385. P-channel DDC transistors are understood to have reverse doping types as compared to an n-channel DDC.
Further descriptions of a DDC transistor as well as an exemplary fabrication process and other aspects of a DDC transistor can be found in U.S. Pat. No. 8,273,617, titled “Electronic Devices and Systems, and Methods for Making and Using the Same.” A DDC transistor provides advantages for circuit design in that, among other reasons, a DDC transistor enables designs having pulled-in corners. The reason is the tighter distribution of the threshold voltage from device-to-device. Additionally, a DDC transistor includes a strong body coefficient by which body biasing can be used to further pull in design corners. A result of using a DDC transistor is the ability to implement improved integrated circuit designs according to desired targets for power and performance whereas when using conventional transistors circuit designers resort to designing conservatively for wider design corners thereby sacrificing the potential power and performance that could be otherwise achieved for a design. An advantage of using a DDC transistor as part of implementing on the embodiments described herein is in the ability to reliably design integrated circuits using a statistically-based, process variation-comprehending simulation model by which design corners could be shrunk.
As in the case of
It should be appreciated that in the foregoing descriptions of exemplary embodiments, various features are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure aiding in the understanding of one or more of the various inventive aspects. This method of disclosure, however, is not to be interpreted as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of the invention.
It is also understood that the embodiments may be practiced in the absence of an element and/or step not specifically disclosed. That is, an inventive feature of the invention may be elimination of an element.
Accordingly, while the various aspects of the particular embodiments set forth herein have been described in detail, the present invention could be subject to various changes, substitutions, and alterations without departing from the spirit and scope of the invention.
Number | Name | Date | Kind |
---|---|---|---|
3958266 | Athanas | May 1976 | A |
4000504 | Berger | Dec 1976 | A |
4021835 | Etoh et al. | May 1977 | A |
4208728 | Blahut et al. | Jun 1980 | A |
4242691 | Kotani et al. | Dec 1980 | A |
4276095 | Beilstein, Jr. et al. | Jun 1981 | A |
4315781 | Henderson | Feb 1982 | A |
4578128 | Mundt et al. | Mar 1986 | A |
4617066 | Vasudev | Oct 1986 | A |
4761384 | Neppl et al. | Aug 1988 | A |
4819043 | Yazawa et al. | Apr 1989 | A |
5034337 | Mosher et al. | Jul 1991 | A |
5144378 | Hikosaka | Sep 1992 | A |
5156989 | Williams et al. | Oct 1992 | A |
5156990 | Mitchell | Oct 1992 | A |
5166765 | Lee et al. | Nov 1992 | A |
5208473 | Komori et al. | May 1993 | A |
5298763 | Shen et al. | Mar 1994 | A |
5369288 | Usuki | Nov 1994 | A |
5384476 | Nishizawa et al. | Jan 1995 | A |
5461338 | Hirayama et al. | Oct 1995 | A |
5559368 | Hu et al. | Sep 1996 | A |
5608253 | Liu et al. | Mar 1997 | A |
5663583 | Matloubian et al. | Sep 1997 | A |
5712501 | Davies et al. | Jan 1998 | A |
5719422 | Burr et al. | Feb 1998 | A |
5726488 | Watanabe et al. | Mar 1998 | A |
5763921 | Okumura et al. | Jun 1998 | A |
5780899 | Hu et al. | Jul 1998 | A |
5847419 | Imai et al. | Dec 1998 | A |
5856003 | Chiu | Jan 1999 | A |
5861334 | Rho | Jan 1999 | A |
5877049 | Liu et al. | Mar 1999 | A |
5889315 | Farrenkopf et al. | Mar 1999 | A |
5895954 | Yasamura et al. | Apr 1999 | A |
5923987 | Burr | Jul 1999 | A |
5926703 | Yamaguchi et al. | Jul 1999 | A |
5989963 | Luning et al. | Nov 1999 | A |
6020227 | Bulucea | Feb 2000 | A |
6087210 | Sohn | Jul 2000 | A |
6087691 | Hamamoto | Jul 2000 | A |
6096611 | Wu | Aug 2000 | A |
6103562 | Son et al. | Aug 2000 | A |
6121153 | Kikkawa | Sep 2000 | A |
6140839 | Kaviani et al. | Oct 2000 | A |
6147383 | Kuroda | Nov 2000 | A |
6157073 | Lehongres | Dec 2000 | A |
6175582 | Naito et al. | Jan 2001 | B1 |
6184112 | Maszara et al. | Feb 2001 | B1 |
6190979 | Radens et al. | Feb 2001 | B1 |
6194259 | Nayak et al. | Feb 2001 | B1 |
6218895 | De et al. | Apr 2001 | B1 |
6229188 | Aoki et al. | May 2001 | B1 |
6245618 | An et al. | Jun 2001 | B1 |
6288429 | Iwata et al. | Sep 2001 | B1 |
6300177 | Sundaresan et al. | Oct 2001 | B1 |
6313489 | Letavic et al. | Nov 2001 | B1 |
6320222 | Forbes et al. | Nov 2001 | B1 |
6326666 | Bernstein et al. | Dec 2001 | B1 |
6358806 | Puchner | Mar 2002 | B1 |
6380019 | Yu et al. | Apr 2002 | B1 |
6391752 | Colinge et al. | May 2002 | B1 |
6426279 | Huster et al. | Jul 2002 | B1 |
6444550 | Hao et al. | Sep 2002 | B1 |
6444551 | Ku et al. | Sep 2002 | B1 |
6461920 | Shirahata | Oct 2002 | B1 |
6461928 | Rodder | Oct 2002 | B2 |
6472278 | Marshall et al. | Oct 2002 | B1 |
6482714 | Hieda et al. | Nov 2002 | B1 |
6484252 | Watanabe | Nov 2002 | B1 |
6489224 | Burr | Dec 2002 | B1 |
6492232 | Tang et al. | Dec 2002 | B1 |
6500739 | Wang et al. | Dec 2002 | B1 |
6503801 | Rouse et al. | Jan 2003 | B1 |
6506640 | Ishida et al. | Jan 2003 | B1 |
6518623 | Oda et al. | Feb 2003 | B1 |
6534373 | Yu | Mar 2003 | B1 |
6541829 | Nishinohara et al. | Apr 2003 | B2 |
6548842 | Bulucea et al. | Apr 2003 | B1 |
6551885 | Yu | Apr 2003 | B1 |
6573129 | Hoke et al. | Jun 2003 | B2 |
6600200 | Lustig et al. | Jul 2003 | B1 |
6620671 | Wang et al. | Sep 2003 | B1 |
6624488 | Kim | Sep 2003 | B1 |
6630710 | Augusto | Oct 2003 | B1 |
6660605 | Liu | Dec 2003 | B1 |
6667200 | Sohn et al. | Dec 2003 | B2 |
6670260 | Yu et al. | Dec 2003 | B1 |
6693333 | Yu | Feb 2004 | B1 |
6730568 | Sohn | May 2004 | B2 |
6737724 | Hieda et al. | May 2004 | B2 |
6743291 | Ang et al. | Jun 2004 | B2 |
6753230 | Sohn et al. | Jun 2004 | B2 |
6770944 | Nishinohara et al. | Aug 2004 | B2 |
6787424 | Yu | Sep 2004 | B1 |
6797994 | Hoke et al. | Sep 2004 | B1 |
6808994 | Wang | Oct 2004 | B1 |
6821825 | Todd et al. | Nov 2004 | B2 |
6822297 | Nandakumar et al. | Nov 2004 | B2 |
6831292 | Currie et al. | Dec 2004 | B2 |
6881641 | Wieczorek et al. | Apr 2005 | B2 |
6881987 | Sohn | Apr 2005 | B2 |
6893947 | Martinez et al. | May 2005 | B2 |
6916698 | Mocuta et al. | Jul 2005 | B2 |
6930007 | Bu et al. | Aug 2005 | B2 |
6930360 | Yamauchi et al. | Aug 2005 | B2 |
6963090 | Passlack et al. | Nov 2005 | B2 |
7002214 | Boyd et al. | Feb 2006 | B1 |
7008836 | Algotsson et al. | Mar 2006 | B2 |
7013359 | Li | Mar 2006 | B1 |
7015546 | Herr et al. | Mar 2006 | B2 |
7057216 | Ouyang et al. | Jun 2006 | B2 |
7061058 | Chakravarthi et al. | Jun 2006 | B2 |
7064039 | Liu | Jun 2006 | B2 |
7064399 | Babcock et al. | Jun 2006 | B2 |
7071103 | Chan et al. | Jul 2006 | B2 |
7078325 | Curello et al. | Jul 2006 | B2 |
7078776 | Nishinohara et al. | Jul 2006 | B2 |
7089515 | Hanafi et al. | Aug 2006 | B2 |
7106128 | Tschanz et al. | Sep 2006 | B2 |
7119381 | Passlack | Oct 2006 | B2 |
7164307 | Tschanz et al. | Jan 2007 | B2 |
7170120 | Datta et al. | Jan 2007 | B2 |
7176745 | Itoh et al. | Feb 2007 | B2 |
7186598 | Yamauchi et al. | Mar 2007 | B2 |
7189627 | Wu et al. | Mar 2007 | B2 |
7199430 | Babcock et al. | Apr 2007 | B2 |
7202517 | Dixit et al. | Apr 2007 | B2 |
7211871 | Cho | May 2007 | B2 |
7221021 | Wu et al. | May 2007 | B2 |
7223646 | Miyashita et al. | May 2007 | B2 |
7226833 | White et al. | Jun 2007 | B2 |
7226843 | Weber et al. | Jun 2007 | B2 |
7235822 | Li | Jun 2007 | B2 |
7236045 | Tschanz et al. | Jun 2007 | B2 |
7247896 | Oh et al. | Jul 2007 | B2 |
7294877 | Rueckes et al. | Nov 2007 | B2 |
7297994 | Wieczorek et al. | Nov 2007 | B2 |
7301208 | Handa et al. | Nov 2007 | B2 |
7304350 | Misaki | Dec 2007 | B2 |
7312500 | Miyashita et al. | Dec 2007 | B2 |
7323754 | Ema et al. | Jan 2008 | B2 |
7332439 | Lindert et al. | Feb 2008 | B2 |
7348629 | Chu et al. | Mar 2008 | B2 |
7354833 | Liaw | Apr 2008 | B2 |
7427788 | Li et al. | Sep 2008 | B2 |
7442971 | Wirbeleit et al. | Oct 2008 | B2 |
7443641 | Suzuki | Oct 2008 | B2 |
7462908 | Bol et al. | Dec 2008 | B2 |
7485536 | Jin et al. | Feb 2009 | B2 |
7491988 | Tolchinsky et al. | Feb 2009 | B2 |
7494861 | Chu et al. | Feb 2009 | B2 |
7498637 | Yamaoka et al. | Mar 2009 | B2 |
7501324 | Babcock et al. | Mar 2009 | B2 |
7501849 | Perisetty | Mar 2009 | B2 |
7507999 | Kusumoto et al. | Mar 2009 | B2 |
7510932 | Oh et al. | Mar 2009 | B2 |
7514953 | Perisetty | Apr 2009 | B2 |
7521323 | Surdeanu et al. | Apr 2009 | B2 |
7531393 | Doyle et al. | May 2009 | B2 |
7538412 | Schulze et al. | May 2009 | B2 |
7564105 | Chi et al. | Jul 2009 | B2 |
7592241 | Takao | Sep 2009 | B2 |
7598142 | Ranade et al. | Oct 2009 | B2 |
7605041 | Ema et al. | Oct 2009 | B2 |
7605060 | Meunier-Beillard et al. | Oct 2009 | B2 |
7605429 | Bernstein et al. | Oct 2009 | B2 |
7608496 | Chu | Oct 2009 | B2 |
7615802 | Elpelt et al. | Nov 2009 | B2 |
7622341 | Chudzik et al. | Nov 2009 | B2 |
7642140 | Bae et al. | Jan 2010 | B2 |
7645665 | Kubo et al. | Jan 2010 | B2 |
7651920 | Siprak | Jan 2010 | B2 |
7655523 | Babcock et al. | Feb 2010 | B2 |
7667527 | Clark et al. | Feb 2010 | B2 |
7675126 | Cho | Mar 2010 | B2 |
7678638 | Chu et al. | Mar 2010 | B2 |
7681628 | Joshi et al. | Mar 2010 | B2 |
7682887 | Dokumaci et al. | Mar 2010 | B2 |
7683442 | Burr et al. | Mar 2010 | B1 |
7696000 | Liu et al. | Apr 2010 | B2 |
7704844 | Zhu et al. | Apr 2010 | B2 |
7709828 | Braithwaite et al. | May 2010 | B2 |
7723750 | Zhu et al. | May 2010 | B2 |
7750405 | Nowak | Jul 2010 | B2 |
7750670 | Goodnow et al. | Jul 2010 | B2 |
7750682 | Bernstein et al. | Jul 2010 | B2 |
7755146 | Helm et al. | Jul 2010 | B2 |
7759714 | Itoh et al. | Jul 2010 | B2 |
7795677 | Bangsaruntip et al. | Sep 2010 | B2 |
7800404 | Verma et al. | Sep 2010 | B2 |
7818702 | Mandelman et al. | Oct 2010 | B2 |
7829402 | Matocha et al. | Nov 2010 | B2 |
7867835 | Lee et al. | Jan 2011 | B2 |
7883977 | Babcock et al. | Feb 2011 | B2 |
7888747 | Hokazono | Feb 2011 | B2 |
7897495 | Ye et al. | Mar 2011 | B2 |
7906413 | Cardone et al. | Mar 2011 | B2 |
7906813 | Kato | Mar 2011 | B2 |
7919791 | Flynn et al. | Apr 2011 | B2 |
7948008 | Liu et al. | May 2011 | B2 |
7952147 | Ueno et al. | May 2011 | B2 |
7960232 | King et al. | Jun 2011 | B2 |
7960238 | Kohli et al. | Jun 2011 | B2 |
7968400 | Cai | Jun 2011 | B2 |
7968411 | Williford | Jun 2011 | B2 |
7978001 | Bertram et al. | Jul 2011 | B2 |
8004024 | Furukawa et al. | Aug 2011 | B2 |
8012827 | Yu et al. | Sep 2011 | B2 |
8039332 | Bernard et al. | Oct 2011 | B2 |
8048791 | Hargrove et al. | Nov 2011 | B2 |
8048810 | Tsai et al. | Nov 2011 | B2 |
8067279 | Sadra et al. | Nov 2011 | B2 |
8105891 | Yeh et al. | Jan 2012 | B2 |
8106424 | Schruefer | Jan 2012 | B2 |
8106481 | Rao | Jan 2012 | B2 |
8112551 | Sullam | Feb 2012 | B2 |
8119482 | Bhalla et al. | Feb 2012 | B2 |
8120069 | Hynecek | Feb 2012 | B2 |
8129246 | Babcock et al. | Mar 2012 | B2 |
8129797 | Chen et al. | Mar 2012 | B2 |
8134159 | Hokazono | Mar 2012 | B2 |
8143120 | Kerr et al. | Mar 2012 | B2 |
8143124 | Challa et al. | Mar 2012 | B2 |
8143678 | Kim et al. | Mar 2012 | B2 |
8148774 | Mori et al. | Apr 2012 | B2 |
8163619 | Yang et al. | Apr 2012 | B2 |
8173502 | Yan et al. | May 2012 | B2 |
8178430 | Kim et al. | May 2012 | B2 |
8183096 | Wirbeleit | May 2012 | B2 |
8183107 | Mathur et al. | May 2012 | B2 |
8217427 | Chuang et al. | Jul 2012 | B2 |
8236661 | Dennard et al. | Aug 2012 | B2 |
20010014495 | Yu | Aug 2001 | A1 |
20030122203 | Nishinohara et al. | Jul 2003 | A1 |
20030183856 | Wieczorek et al. | Oct 2003 | A1 |
20040075118 | Heinemann et al. | Apr 2004 | A1 |
20040084731 | Matsuda et al. | May 2004 | A1 |
20040263205 | Park | Dec 2004 | A1 |
20050097196 | Wronski et al. | May 2005 | A1 |
20050116282 | Pattanayak et al. | Jun 2005 | A1 |
20050250289 | Babcock et al. | Nov 2005 | A1 |
20060022270 | Boyd et al. | Feb 2006 | A1 |
20060049464 | Rao | Mar 2006 | A1 |
20060066388 | Tschanz et al. | Mar 2006 | A1 |
20060068555 | Zhu et al. | Mar 2006 | A1 |
20060068586 | Pain | Mar 2006 | A1 |
20060071278 | Takao | Apr 2006 | A1 |
20060154428 | Dokumaci | Jul 2006 | A1 |
20070004107 | Lee et al. | Jan 2007 | A1 |
20070040222 | Van Camp et al. | Feb 2007 | A1 |
20070158790 | Rao | Jul 2007 | A1 |
20070238253 | Tucker | Oct 2007 | A1 |
20080001171 | Tezuka et al. | Jan 2008 | A1 |
20080067589 | Ito et al. | Mar 2008 | A1 |
20080143423 | Komatsu et al. | Jun 2008 | A1 |
20080169493 | Lee et al. | Jul 2008 | A1 |
20080197439 | Goerlach et al. | Aug 2008 | A1 |
20080227250 | Ranade et al. | Sep 2008 | A1 |
20080246533 | Barrows et al. | Oct 2008 | A1 |
20080258198 | Bojarczuk et al. | Oct 2008 | A1 |
20080272409 | Sonkusale et al. | Nov 2008 | A1 |
20090057746 | Sugll et al. | Mar 2009 | A1 |
20090108350 | Cai et al. | Apr 2009 | A1 |
20090134468 | Tsuchiya et al. | May 2009 | A1 |
20090179692 | Hidaka | Jul 2009 | A1 |
20090302388 | Cai et al. | Dec 2009 | A1 |
20090311837 | Kapoor | Dec 2009 | A1 |
20090321849 | Miyamura et al. | Dec 2009 | A1 |
20100012988 | Yang et al. | Jan 2010 | A1 |
20100038724 | Anderson et al. | Feb 2010 | A1 |
20100055886 | Izumida et al. | Mar 2010 | A1 |
20100187641 | Zhu et al. | Jul 2010 | A1 |
20110073961 | Dennard et al. | Mar 2011 | A1 |
20110074498 | Thompson et al. | Mar 2011 | A1 |
20110079860 | Verhulst | Apr 2011 | A1 |
20110079861 | Shifren et al. | Apr 2011 | A1 |
20110169082 | Zhu et al. | Jul 2011 | A1 |
20110175170 | Wang et al. | Jul 2011 | A1 |
20110180880 | Chudzik et al. | Jul 2011 | A1 |
20110193164 | Zhu | Aug 2011 | A1 |
20120021594 | Gurtej et al. | Jan 2012 | A1 |
20120056275 | Cai et al. | Mar 2012 | A1 |
20120108050 | Chen et al. | May 2012 | A1 |
20120190177 | Kim et al. | Jul 2012 | A1 |
Number | Date | Country |
---|---|---|
0274278 | Jul 1988 | EP |
59193066 | Jan 1984 | JP |
4186774 | Mar 1992 | JP |
8288508 | Jan 1996 | JP |
8153873 | Jun 1996 | JP |
2004087671 | Mar 2004 | JP |
1020040024599 | Oct 2005 | KR |
2011062788 | May 2011 | WO |
Entry |
---|
Werner, P. et al., “Carbon Diffusion in Silicon”, Oct. 1998, Applied Physics Letters, vol. 73, No. 17, pp. 2465-2467. |
Yan, Ran-Hong et al., “Scaling the Si MOSFET: From Bulk to SOI to Bulk”, Jul. 1992, IEEE Transactions on Electron Devices, vol. 39, No. 7. |
Abiko, H et al., “A Channel Engineering Combined with Channel Epitaxy Optimization and TED Suppression for 0.15 μm n-n Gate CMOS Technology”, 1995 Symposium on VLSI Technology Digest of Technical Papers, 1995, pp. 23-24. |
Chau, R et al., “A 50nm Depleted-Substrate CMOS Transistor (DST)”, Electron Device Meeting 2001, IEDM Technical Digest, IEEE International, 2001, pp. 29.1.1-29.1.4. |
Ducroquet, F et al. “Fully Depleted Silicon-On-Insulator nMOSFETs with Tensile Strained High Carbon Content Si1-yCy Channel”, 2006, ECS 210th Meeting, Abstract 1033. |
Ernst, T et al.,“Nanoscaled MOSFET Transistors on Strained Si, SiGe, Ge Layers: Some Integration and Electrical Properties Features”, 2006, ECS Trans. vol. 3, Issue 7, pp. 947-961. |
Goesele, U et al., Diffusion Engineering by Carbon in Silicon, 2000, Mat. Res. Soc. Symp. vol. 610. |
Hokazono, A et al., “Steep Channel & Halo Profiles Utilizing Boron-Diffusion-Barrier Layers (Si:C) for 32 nm Node and Beyong”, 2008, 2008 Synposium on VLSI Technology Digest of Technical Papers, pp. 112-113. |
Hokazono, A et al., “Steep Channel Profiles in n/pMOS Controlled by Boron-Doped Si:C Layers for Continual Bulk-CMOS Scaling”, 2009, IEDM09-676 Symposium, pp. 29.1.1-29.1.4. |
Holland, OW and Thomas, DK “A Method to Improve Activation of Implanted Dopants in SiC”, 2001, Oak Ridge National Laboratory, Oak Ridge, TN. |
Kotaki, H., et al., “Novel Bulk Dynamic Threshold Voltage MOSFET (B-DTMOS) with Advanced Isolation (SITOS) and Gate to Shallow-Well Contact (SSS-C) Processes for Ultra Low Power Dual Gate CMOS”, 1996, IEDM 96, pp. 459-462. |
Lavéant, P. “Incorporation, Diffusion and Agglomeration of Carbon in Silicon”, 2002, Solid State Phenomena, vols. 82-84, pp. 189-194. |
Noda, K et al., “A 0.1-μm Delta-Doped MOSFET Fabricated with Post-Low-Energy Implanting Selective Epitaxy”, Apr. 1998, IEEE Transactions on Electron Devices, vol. 45, No. 4, pp. 809-814. |
Ohguro, T et al., “An 0.18-μm CMOS for Mixed Digital and Analog Aplications with Zero-Volt-Vth Epitaxial-Channel MOSFET's”, Jul. 1999, IEEE Transactions on Electron Devices, vol. 46, No. 7, pp. 1378-1383. |
Pinacho, R et al., “Carbon in Silicon: Modeling of Diffusion and Clustering Mechanisms”, Aug. 2002, Journal of Applied Physics, vol. 92, No. 3, pp. 1582-1588. |
Robertson, LS et al., “The Effect of Impurities on Diffusion and Activation of Ion Implanted Boron in Silicon”, 2000, Mat. Res. Soc. Symp. vol. 610. |
Scholz, R et al., “Carbon-Induced Undersaturation of Silicon Self-Interstitials”, Jan. 1998, Appl. Phys. Lett. 72(2), pp. 200-202. |
Scholz, RF et al., “The Contribution of Vacancies to Carbon Out-Diffusion in Silicon”, Jan. 1999,Appl. Phys. Lett., vol. 74, No. 3, pp. 392-394. |
Stolk, PA et al., “Physical Mechanisms of Transient Enhanced Dopant Diffusion in Ion-Implanted Silicon”, May 1997, J. Appl. Phys. 81(9), pp. 6031-6050. |
Thompson, S et al., “MOS Scaling: Transistor Challenges for the 21st Century”, 1998, Intel Technology Journal Q3' 1998, pp. 1-19. |
Wann, C. et al., “Channel Profile Optimization and Device Design for Low-Power High-Performance Dynamic-Threshold MOSFET”, 1996, IEDM 96, pp. 113-116. |
English Translation of JP 8153873 Submitted herewith. |
Tschanz et al., Adaptive Body Bias for Reducing Impacts of Die-to-Die and Within-Die Parameter Variations on Microprocessor Frequency and Leakage, IEEE Journal of Solid-State Circuits, vol. 37, No. 11, Nov. 2002. |