Patent Application
20250007551
The present disclosure relates to an integrated circuit (IC) device for a satellite receiver comprising at least one control circuit, a plurality of connection pins and at least two general programmable input/output (GPIO) circuits connected with the plurality of connection pins. The disclosure further relates to a satellite receiver system comprising at least one active antenna, a power source, a sense resistor and an IC device.
Circuits for receiving signals from a satellite transmitter are widely known and are used in many different application areas. One particular application area is the use of satellite communication in global navigation satellite systems (GNSS). In this, as well as in other satellite receiver circuits, a received signal strength is often low. Moreover, the actual receiver circuit, typically integrated into a chip to form an IC device, is often placed at a different location than the actual antenna, i.e., the receiver circuit is connected with an external antenna.
To prevent additional signal losses caused by the transmission of the received satellite signal from the antenna via an antenna cable to the receiver circuit, active antennas are often used for signal reception. In this case, a supply current for the active antenna may be provided via the antenna cable to the active antenna. To protect the receiver signal, which is also connected to the antenna cable, it may be desirable to check the antenna cable for faults, in particular for short circuits or open circuits. This may be achieved, for example, by measuring a current provided from a respective power source of the active antenna. If the current exceeds the upper threshold, this indicates a short circuit in the antenna cable. Inversely, if the current drops below a lower threshold value, this may indicate an open circuit or disconnection of the active antenna.
Accordingly, it is an objective of the present invention to describe an integrated circuit device for a satellite receiver and a corresponding satellite receiver system that enables the detection of faults in an antenna connection. Preferably, the proposed solution should allow for a high integration of the receiver circuit and, in particular, avoid the addition of further pins to an IC device.
According to a first aspect of the disclosure, an integrated circuit, IC, device for a satellite receiver is provided. The IC device comprises at least one digital control circuit, a plurality of connection pins, at least two general programmable input/output, GPIO, circuits connected with a first and second connection pin of the plurality of connection pins, respectively, and an antenna monitoring circuit comprising an analog-to-digital converter, ADC, circuit, wherein a signal input of the antenna monitoring circuit is connected to the first connection pin, and a reference input of the antenna monitoring circuit is connected to the second connection pin. The at least one digital control circuit is configured, in a first mode of operation, to selectively provide an analog signal received via the signal input and the reference input to the ADC circuit, to capture a digital value corresponding to the analog signal using the at least one ADC circuit, and to compare the captured digital value with at least one programmable threshold value. In addition, the at least one digital control circuit is further configured, in a second mode of operation, to disconnect at least parts of the ADC circuit from the first and the second connection pin, and capture or provide a respective digital value from or to at least one of the first pin and the second connection pin using the respective GPIO circuit.
By the provision of an antenna monitoring circuit with an integrated ADC circuit, which is configured to be at least partially disconnected from a signal input of the antenna monitoring circuit, external connection pins of an integrated circuit previously used for capturing or providing digital values may be reused to capture an analog signal using the integrated ADC circuit. In this way, the provision of further connection pins for providing an analog input signal to the IC device can be avoided. As a result, the pin count of the IC device is kept low and, in particular, the same as for IC devices without the capability of capturing an analog value, for example a voltage corresponding to a current flowing through a sense resistor connected to an active antenna cable.
Moreover, by integrating the control for the selection of an operating mode and a comparison of a captured digital value with at least one threshold value into the control circuit of the IC device, a more flexible sensing scheme can be enabled, compared with a corresponding sensing circuit implemented in a separate, analog circuit.
According to at least one implementation, the at least two GPIO circuits are configured to be operated in a first voltage domain and at least parts of the ADC circuit are configured to be operated in a second voltage domain, the second voltage domain being lower than the first voltage domain.
For example, a front-end sampling circuit of the ADC circuit may comprise at least one capacitor to electrically decouple the first voltage domain and the second voltage domain. In this case, the front-end sampling circuit may also be used to separate different domains of the IC device, for example a high voltage domain associated with the antenna signal from a low voltage domain associated with the conversion circuit and/or the control circuit.
According to at least one implementation, the front-end sampling circuit may comprise one or more switches selectively disconnecting at least parts of the ADC circuit from the first and second connection pin.
For example, the front-end sampling circuit may comprise a first sampling capacitor, a second sampling capacitor, a first switch connected between the first connection pin and a first terminal of the first sampling capacitor, a second switch connected between the first connection pin and a first terminal of the second sampling capacitor, a third switch connected between the second connection pin and the first terminal of the first sampling capacitor, and a fourth switch connected between the second connection pin and the first terminal of the second sampling capacitor.
Optionally, the ADC circuit may further comprise a conversion circuit, and the front-end sampling circuit may further comprise a first switching arrangement for selectively coupling a second terminal of the first sampling capacitor with a common reference voltage potential, in particular with a common mode voltage, or a first node of the conversion circuit, and a second switching arrangement for selectively coupling a second terminal of the second sampling capacitor with the common reference voltage potential or a second node of the conversion circuit.
Optionally, in the first mode of operation, the at least one digital control circuit is configured to, in a first state, to close the first and fourth switches and to open the second and third switches, while the second terminal of the first sampling capacitor and the second terminal of the second sampling capacitor are connected to the common reference voltage potential, and, in a second state, to close the second and third switches and to open the first and fourth switches, while the second terminal of the first sampling capacitor is connected to the first node of the conversion circuit the second terminal of the second sampling capacitor is connected to the second node of the conversion circuit. In the second mode of operation, the at least one digital control circuit is configured to open at least the first, second, third and fourth switches.
In this way, an electrical decoupling of the ADC circuit from the GPIO circuits can be combined with parts of a front-end sampling circuit of the ADC circuit, reducing the component count of the IC device compared with the use of an additional signal multiplexing circuit.
In at least one embodiment, the at least one ADC circuit is configured as a delta-sigma ADC. In this case, the antenna monitoring circuit may implement the analog circuit components of the delta-sigma ADC, whereas digital processing components of the delta-sigma ADC may be implemented by the at least one digital control circuit of the IC device.
In at least one embodiment, the at least one digital control circuit comprises a comparison unit configured to compare the captured digital value with a first, lower threshold value indicating an open circuit condition and a second, upper threshold value indicating a short circuit condition. By utilizing both a lower and an upper threshold value, different fault conditions can be detected using the same monitoring circuit.
According to a second aspect of the present disclosure, a satellite receiver system is provided. The satellite receiver system comprises at least one active antenna, a power source configured for providing an operating voltage to the active antenna, a sense resistor electrically connected between the power source and the active antenna, and an IC device according to the first aspect, wherein the first connection pin of the IC device is electrically connected to a first terminal of the sense resistor and the second connection pin of the IC device is electrically connected to a second terminal of the sense resistor.
The system according to the second aspect allows the size of a current flowing from the power source towards the at least one active antenna to be sensed, thereby enabling detection of faults of the antenna itself and/or an antenna cable.
According to at least one implementation, in the first mode of operation, the at least one digital control circuit is configured to determine a supply current provided from the power source to the active antenna based on the captured digital value indicative of a voltage drop across the sense resistor and a resistance value of the sense resistor.
According to at least one implementation, the sense resistor and the IC device are provided in a satellite receiver module, in particular on a common printed circuit board, and the at least one active antenna is provided in a separate antenna module connected to the satellite receiver module using an antenna cable. Accordingly, the system may be formed from two prefabricated modules that are connected by a single antenna cable. The satellite receiver module can monitor the cable connection between the two modules based on the sense resistor and the IC device.
According to at least one implementation, the satellite receiver module further comprises an antenna switch connected between the power source and the antenna cable, and the IC device further comprises a third GPIO circuit connected to a control terminal of the antenna switch. The at least one digital control circuit is further configured to open the antenna switch to disconnect the power source from the antenna cable, when the captured digital value exceeds an upper threshold value. In this way, damage to a power source can be avoided, for example in case of a short circuit in the antenna cable.
According to at least one implementation, the power source, and the antenna switch are provided externally to the IC device, and the third GPIO circuit is connected via a third connection pin of the plurality of connection pins to the antenna switch.
According to an alternative implementation, the power source, the antenna switch and the third GPIO circuit are integrated into the IC device.
According to at least one implementation, the satellite receiver module further comprises a direct current, DC, blocking element, in particular a capacitor, and an alternating current, AC, blocking element, in particular an inductor. The IC device further comprises a radio frequency, RF, input circuit connected to the antenna cable via the DC blocking element, and the AC blocking element is electrically connected between the antenna cable and the sense resistor. In this way, DC and AC signal components can be provided separately to the respective parts of the IC device.
According to at least one implementation, the satellite receiver module further comprises a first voltage divider and a second voltage divider. The first voltage divider comprises a first pull-up resistor, connected between the first terminal of the sense resistor and the first connection pin, and a first pull-down resistor, connected between a reference potential, in particular electrical ground, and the first connection pin. The second voltage divider comprises a second pull-up resistor, connected between the second terminal of the sense resistor and the second connection pin, and a second pull-down resistor, connected between the reference potential and the second connection pin. In this way, high external voltages can be reduced to protect the IC device.
Further details of the disclosed devices and systems are provided in the attached set of claims as well as the following, detailed description of embodiments.
Different embodiments of the invention are described with respect to the attached drawings.
In the described embodiment, the satellite receiver module 12 comprises a satellite receiver chip 22 in the form of an integrated circuit (IC). The satellite receiver module 12 further comprises a sense resistor 24, a power source 26, and an antenna switch 28, for example a MOSFET. Electrical nodes between the antenna switch 28 and a first terminal of the sense resistor 24 and between a second terminal of the sense resistor 24 and the antenna cable 16 are connected, by means of a connection circuit 30, to a first connection pin 32 and a second connection pin 34 of the satellite receiver chip 22. Moreover, the antenna switches 28 is connected to a third connection pin 36 of the satellite receiver chip 22, which controls the antenna switch 28.
The satellite receiver chip 22 may have further connection pins, such as connection pins 38 and 40 for the provision of a supply voltage Vcc and a reference potential, such as electrical ground.
In the described embodiment, the connection circuit 30 further comprises a capacitor 50 for capacitively coupling the antenna cable 16 to an RF input pin 42 of the satellite receiver chip 22. Note that the capacitor 50 blocks the antenna supply voltage VDD_ANT from reaching the RF input pin 42. Moreover, the connection circuit 30 comprises an inductor 48 for blocking the radio frequency signal received from the antenna module 14 from reaching the connection pins 32 to 36.
In the specific embodiment shown in
In operation, the active antenna module 14 may be activated by closing the antenna switch 28 under the control of a controller 52 of the satellite receiver chip 22. The controller 52 may be a multi-purpose microcontroller circuit responsible for implementing various control algorithms of the satellite receiver chip 22 or may be a logical control unit or software routine responsible only for the control of the external antenna module 14. Accordingly, the antenna current Iant will start to flow from the power source 26 via the sense resistor 24 and the inductor 48 to the LNA 20 of the antenna module 14. A voltage ΔV will drop across the sense resistor 24, which is proportional to the current flowing from the satellite receiver module 12 towards the antenna module 14. In the case that the antenna cable 16 is damaged, for example separated or short-circuited, the current provided from the power source 26 will drop below or exceed a normal supply level. This in turn will result in a corresponding reduced or increased voltage drop across the sense resistor 24.
The satellite receiver chip 22 comprises an antenna monitoring circuit 54 for detection of faults of the active antenna 14 and/or the antenna cable 16. In practice, this is achieved by sensing a voltage drop ΔV across the sense resistor 24 and comparing it with one or more threshold values. On the conceptual level shown in
Attention is drawn to the fact that the first and second connection pins 32 and 34, as well as the third connection pin 36, are also connected to respective GPIO circuits (not shown) or channels of a multi-channel GPIO controller 56 of the satellite receiver chip 22. Note that, in practice, integrated circuits often provide a number of freely programmable input output circuits or channels, which can be controlled by an integrated controller, such as the controller 52. According to the disclosed embodiment, the connection pins 32 to 36 correspond to respective channels of the multichannel GPIO controller 56.
In the case that the antenna monitoring circuit 54 is not used, the GPIO controller 56 may provide two separate digital output signals via the first connection pin 32 and the second connection pin 34, respectively. Alternatively, the GPIO controller 56 may also receive up to two digital input signals via the first connection pin 32 and/or the second connection pin 34, respectively. However, in the case that the satellite receiver chip 22 wants to measure the current flowing from the satellite receiver module 12 to the antenna module 14, the first connection pin 32 and the second connection pin 34 are connected to the antenna monitoring circuit 54 to sense the analog voltage difference between to the first connection pin 32 and the second connection pin 34.
The third connection pin 36 is configured as an output channel and provides the digital control signal ANT OFF to control the provision of the supply voltage for the antenna module 14.
In the described embodiment, the ADC circuit 58 is implemented as a delta-sigma ADC.
The front-end sampling circuit 61 selectively couples the sense signal VSENSE received from the first connection pin 32 and the reference signal VREF received from the second connection pin 34 of the antenna monitoring circuit 54 with the further components of the conversion circuit 62. It comprises four switches 64, 66, 68 and 70, which selectively provides the voltages provided via the connection pins 32 and 34 to first terminals of two sampling capacitors 72 and 74. The front-end sampling circuit 61 further comprises four further switches 76, 78, 80 and 82, which selectively connect second terminals of the two sampling capacitors 72 and 74 wither with a reference potential, in particular a common mode voltage Vcm, or corresponding nodes 92 and 94 of the conversion circuit 62. The switches 64 to 70 and 76 to 82 may be MOSFETs or similar semiconductor switching elements. The common mode voltage Vcm may be generated using a simple resistor divider circuit (not shown). Optionally the resistor divider circuit may be disabled, e.g., using a NMOS on its GND side, to disable a corresponding current, when the common mode voltage Vcm is not required.
In operation, the front-end sampling circuit 61 switches between a first state and a second state with a first switching frequency f1. In the first state a first control signal Φ1 is provided and the switches 64, 70, 76 and 82 are closed, such that the first sampling capacitor 72 is charged to a voltage difference between the sense signal VSENSE and the common mode voltage Vcm, and the second sampling capacitor 74 is charged to a voltage difference between the reference signal VREF and the common mode voltage Vcm. All other switches remain open. In the second state a second control signal Φ2 is provided and all switches are inverted such that the first and second capacitors 72 and 74 are connected via the first and second nodes 92 and 94, respectively, to an operational amplifier 84 of the conversion circuit 62. The positive and negative output signals from the operational amplifier 84 are fed back via two integration capacitors 86 and 88 to the first node 92 and the second node 94 at the negative and positive input terminals of the operational amplifier 84, respectively.
In the described embodiment, the input and output signals to and from the operational amplifier 84 are optionally chopped using corresponding chopping switches (not shown) at a second, switching frequency f2. The second, switching frequency f2 is lower than the first switching frequency f1, for example f2=⅛f1. Accordingly, the operational amplifier 84 is operated in a first orientation for a few cycles of the first and second states. Thereafter, the operational amplifier 84 is flipped upside down and is operated in a second orientation for a few cycles of the first and second states. This enables to move any input offset to a high frequency domain. The offset can then be easily removed by a decimation filter arranged downstream of the analog circuit shown in
The output signal provided by the operational amplifier 84 is also provided to a comparator 90. Depending on the result of the comparison by the comparator 90, charge is either is injected into the second node 94 and removed from the first node 92 using corresponding delta-sigma-feedback loops (not shown). That means that charge is injected into the second terminal of the sampling capacitor 74 and removed from the second terminal of the sampling capacitor 72 using corresponding capacitors and drivers (not shown), or vice versa, based on the output signal of the comparator 90. As a result, the charge on the feedback capacitors 86 and 88 is regulated continuously towards a fixed value, and the analog circuit 60 acts as a first-order delta-sigma modulator. At the same time, the comparator 90 provides a modulation output in the form of a digital, PCM output signal 96, which is fed to the digital part of the delta-sigma ADC to determine if charge is added or removed. This allows the delta-sigma ADC to determine the long term or low-frequency behavior of the analog voltage difference Vdiff provided at the input of the antenna monitoring circuit 54. For this purpose, the delta-sigma ADC further comprises a timer-based digital filter and/or a designator component, i.e., the decimator filter of the delta-sigma converter (not shown in
Attention is drawn to the fact that the analog circuit 60 shown in
Note that the front-end sampling circuit 61 can also be used to completely decouple most of the components of the antenna monitoring circuit 54, including the entire conversion circuit 62 of the ADC circuit 58 in the second voltage domain 100, from the connection pins 32 and 34 and the GPIO controller 56 by simply opening all of the switches 64, 66, 68 and 70. Accordingly, no further components are necessary to switch the satellite receiver circuit 22 from a first mode of operation, wherein the first connection pin 32 and the second connection pin 34 are used to capture an analog input signal, to a second operating mode, wherein the first connection pin 32 and the second connection pin 34 are used as normal GPIO pins.
Accordingly, the disclosed circuits and devices allow the connection pins 32 and 34 to be multiplexed for implementing different functionalities. Specifically, the disclosed antenna monitoring circuit 54 enables the controller 52 to monitor the voltage drop at the sense resistor 24 using pins already provided in a conventional chip design for a satellite receiver circuit.
| Number | Date | Country | Kind |
|---|---|---|---|
| 23182094.5 | Jun 2023 | EP | regional |
