A more complete understanding of the present disclosure thereof may be acquired by referring to the following description taken in conjunction with the accompanying drawings wherein:
While the present disclosure is susceptible to various modifications and alternative forms, specific example embodiments thereof have been shown in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific example embodiments is not intended to limit the disclosure to the particular forms disclosed herein, but on the contrary, this disclosure is to cover all modifications and equivalents as defined by the appended claims.
Referring now to the drawings, the details of specific example embodiments are schematically illustrated. Like elements in the drawings will be represented by like numbers, and similar elements will be represented by like numbers with a different lower case letter suffix.
Referring to
A digital output buffer (e.g., driver) 106 may be coupled to the node 104 and controlled with an output buffer enable 126. The digital output buffer 106 when enabled through the output buffer enable 126 will drive the node 104 to logic “1s” and “0s” based upon the digital output data 128. The digital output buffer 106 may also be used as an oscillator output when driving a frequency determining crystal 240 (
An input of a digital receiver 108 may be coupled to the node 104 (optionally through a surge limiting resistor 116) and need not be disabled when another one of the functionalities are being used at the node 104 since the input of the digital receiver 108 may be a high impedance and have a low value of capacitance. The output of the digital receiver 108 may drive a digital input data line 134 that may be coupled to other logic circuits (not shown) internal to the integrated circuit device 102. The digital receiver 108 may be a Schmidt trigger input buffer for digital input data from the node 104. The pull-up structure 114 may also be utilized for maintaining a high “1” logic level (substantially at VDD) when the node 104 is configured as a digital input with the digital receiver 108.
Primary electrostatic discharge (ESD) structures 110 and 112 may be used for suppressing high voltage transients occurring on the node 104 so as to protect the low withstand voltage circuits in the integrated circuit device 102. The surge limiting resistor 116 in combination with a secondary ESD structure 118 may be used for further protection of the more sensitive internal logic, e.g., an analog input 132 and an oscillator input 130 to the respective analog and oscillator circuits (not shown) in the integrated circuit device 102.
An analog switch 120 may couple and decouple the analog input 132 of an analog circuit (not shown), e.g., operational amplifier, comparator, analog-to-digital converter (ADC), etc., to and from the bond pad 104, respectively. The analog switch may add about 1.2 pF of additional load capacitance 122 to the crystal oscillator input 130. However, a typical external load capacitance for a crystal oscillator operating in a high speed (HS) mode may be from about 25 pF to about 35 pF, therefore, the additional analog switch capacitance (about 1.2 pF) load has negligible impact on the crystal oscillator circuit, e.g., 1.2 pF is less than 5 percent tolerance of the external load capacitance of the oscillator. The oscillator input 130 coupled to the node 104 and a digital output coupled to another node (not shown) may be used in an oscillator circuit more fully described hereinbelow.
An analog switch 142 may couple and decouple an analog output of a digital-to-analog converter (DAC) 140, to and from the bond pad 104, respectively. The analog switch 140 may add a negligible amount of additional load capacitance to the bond pad 104.
Referring now to
While embodiments of this disclosure have been depicted, described, and are defined by reference to example embodiments of the disclosure, such references do not imply a limitation on the disclosure, and no such limitation is to be inferred. The subject matter disclosed is capable of considerable modification, alteration, and equivalents in form and function, as will occur to those ordinarily skilled in the pertinent art and having the benefit of this disclosure. The depicted and described embodiments of this disclosure are examples only, and are not exhaustive of the scope of the disclosure.
This application claims priority to commonly owned U.S. Provisional patent application Ser. No. 60/807,968; filed Jul. 21, 2006; entitled “Input-Output Pads With Both Analog-Input and Crystal Oscillator Interface Capabilities” by J. Clark Rogers and Bryan Kris, and is hereby incorporated by reference herein for all purposes.
Number | Date | Country | |
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60807968 | Jul 2006 | US |