BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention, and, together with the description, serve to explain the principles of the invention.
FIG. 1 shows a high-side transistor drive circuit.
FIG. 2 is a top view of an integrated circuit for high-side transistor driver according to an embodiment of the present invention.
FIG. 3 shows a voltage distribution when 500V is applied to the floating circuit according to an embodiment of the present invention.
FIG. 4 is a top view of the integrated circuit including a capacitor for feeding the control signal from the control circuit to the floating circuit according to an embodiment of the present invention.
FIG. 5 is a cross-section view of the integrated circuit according to an embodiment of the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
FIG. 2 is a top view of an integrated circuit for a high-side driver according to an embodiment of the present invention. The integrated circuit includes a P substrate 50, an N diffusion region containing N conductivity type such as an n+ diffusion region. The N conductivity type is the donor-doped type such as using phosphorus ions or arsenic ions to be the donors. The N diffusion region forms a deep N well 60 disposed in the P substrate 50. A low voltage control circuit 300 is located outside the deep N well 60. A floating circuit 200 is located inside the deep N well 60.
FIG. 3 shows a voltage distribution when 500V is applied to the floating circuit 200. High voltage junction barriers 101a and 101b (FIG. 5) are formed for isolating the control circuit 300 and the floating circuit 200 when a voltage of 500V is applied to the floating circuit 200.
FIG. 4 is a top view of the integrated circuit including a capacitor for feeding the control signal of the control circuit 300 to the floating circuit 200 according to an embodiment of the present invention. The capacitor includes a first metal layer 125 and second metal layers 120 and 121 disposed above a portion of the deep N well 60 and the first metal layer 125 to form a capacitor. In addition, a dielectric layer 123 disposed between the first metal layer 125 and the second metal layer 120 and between the first metal layer 125 and the second metal layer 121.
FIG. 5 is a cross-sectional view of a proposed integration circuit, in which P diffusion regions containing the P conductivity type forms P regions 65 such as P-body disposed in the P substrate 50 and the deep N well 60 for isolation purpose. The P conductivity type is the acceptor-doped type such as using boron ions to be the acceptor. P regions 65 help to form depletion regions for serving as isolation structures. The control circuit 300 and the floating circuit 200 include N type Metal-Oxide-Semiconductor Field-Effect-Transistors (MOSFET) devices and P type MOSFET devices. The N type MOSFET device in the floating circuit 200 comprises a first P diffusion region containing P conductivity type, which forms a P well 70 disposed in the deep N well 60. A first N diffusion region containing the N conductivity type forms an N region 71 and is located in the P well 70. A first drain diffusion region having the N+ conductivity type, which forms a drain region 72 is disposed in the N region 71 (N-type Double Diffusion region). A first source diffusion region having the N+ conductivity type forms a source region 74. A conduction channel is developed between the source region 74 and the drain region 72. A polysilicon gate electrode 76 is disposed above oxides 77 to control the current flow in the conduction channel. A first contact diffusion region containing P+ conductivity type forms a contact region 75. The high voltage junction barriers 101a and 101b are formed for isolating the control circuit 300 and the floating circuit 200 when a voltage of 500V is applied to the floating circuit 200.
The P type MOSFET device in the floating circuit 200 comprises a second P diffusion region containing P conductivity type, which forms a P well 80 disposed in the deep N well 60. A second drain diffusion region having the P+ conductivity type forms a drain region 82 and is disposed in the P well 80. A second source diffusion region having the P+ conductivity type forms a source region 85. A conduction channel is formed between the source region 85 and the drain region 82. A polysilicon gate electrode 86 is disposed above oxides to control the current flow in the conduction channel. A second contact diffusion region containing N+ conductivity type forms a contact region 84.
The N type MOSFET device in the control circuit 300 comprises a third N diffusion region containing N conductivity type, which forms an N well 90 is disposed in the P substrate 50. A third P diffusion region containing the P conductivity type forms a P region 91 and is located in the N well 90. A third drain diffusion region having the N+ conductivity type, which forms a drain region 92 is disposed in the N well 90. A third source diffusion region having the N+ conductivity type forms a source region 94. A conduction channel is formed between the source region 94 and the drain region 92. A polysilicon gate electrode 96 is disposed above oxides to control the current flow in the conduction channel. A third contact diffusion region containing P+ conductivity type forms a contact region 95. The third P diffusion region encloses the source region 94 and the contact region 95. A silicon dioxide insulation layer 110 covers the polysilicon gates and the field oxides. The first metal layer 125 is disposed above the silicon dioxide insulation layer 110. The second metal layers 120 and 121 are disposed above the portion of the deep N well 60, which are interleaved with the first metal layer 125 to form the capacitor.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims or their equivalents.
Patent Application
20080036027
