1. Field of the Invention
The present invention relates in general to an integrated circuit, and more particularly to an integrated circuit for a high-side transistor driver.
2. Description of the Prior Art
A variety of power supplies and motor drivers utilize the bridge circuits to control a power source to the load. The bridge circuit normally has a high side transistor connected to the power source and a low side transistor connected to the ground. A common node between the high side transistor and the low-side transistor is coupled to the load. As transistors are controlled to alternately conduct, the voltage of the common node swings in between the power source and the ground. Therefore the control of a high-side transistor driver requires a charge pump circuit and/or a floating drive circuit in order to fully turn on the high-side transistor. In recent development, many floating circuits are being disclosed in U.S. Pat. No. 6,344,959 (Milazzo), U.S. Pat. No. 6,781,422 (Yang) and U.S. Pat. No. 6,836,173 (Yang).
Accordingly, an objective of the present invention is to provide a monolithic IC process to integrate low-voltage control circuits with a high-voltage floating drive circuit. Furthermore, the integration is achieved by using a typical IC process, so as to accomplish the low cost and high production yield.
A high voltage integrated circuit comprises a P substrate. An N diffusion region containing N conductivity type forms a deep N well disposed in the P substrate. Separated P diffusion regions containing the P conductivity type form P wells disposed in the P substrate and the deep N well for the isolation. The low voltage control circuit is located outside the deep N well. A floating circuit is located inside the deep N well. A high voltage junction barrier is thus formed isolating the control circuit from the floating circuit. Furthermore, a capacitor is disposed above the portion of the deep N well for feeding the control signal from the low-voltage control circuit to the floating circuit.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention, and, together with the description, serve to explain the principles of the invention.
The P type MOSFET device in the floating circuit 200 comprises a second P diffusion region containing P conductivity type, which forms a P well 80 disposed in the deep N well 60. A second drain diffusion region having the P+ conductivity type forms a drain region 82 and is disposed in the P well 80. A second source diffusion region having the P+ conductivity type forms a source region 85. A conduction channel is formed between the source region 85 and the drain region 82. A polysilicon gate electrode 86 is disposed above oxides to control the current flow in the conduction channel. A second contact diffusion region containing N+ conductivity type forms a contact region 84.
The N type MOSFET device in the control circuit 300 comprises a third N diffusion region containing N conductivity type, which forms an N well 90 is disposed in the P substrate 50. A third P diffusion region containing the P conductivity type forms a P region 91 and is located in the N well 90. A third drain diffusion region having the N+ conductivity type, which forms a drain region 92 is disposed in the N well 90. A third source diffusion region having the N+ conductivity type forms a source region 94. A conduction channel is formed between the source region 94 and the drain region 92. A polysilicon gate electrode 96 is disposed above oxides to control the current flow in the conduction channel. A third contact diffusion region containing P+ conductivity type forms a contact region 95. The third P diffusion region encloses the source region 94 and the contact region 95. A silicon dioxide insulation layer 110 covers the polysilicon gates and the field oxides. The first metal layer 125 is disposed above the silicon dioxide insulation layer 110. The second metal layers 120 and 121 are disposed above the portion of the deep N well 60, which are interleaved with the first metal layer 125 to form the capacitor.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims or their equivalents.
Number | Name | Date | Kind |
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5434445 | Ravanelli et al. | Jul 1995 | A |
5501994 | Mei | Mar 1996 | A |
5966341 | Takahashi et al. | Oct 1999 | A |
6236100 | Pernyeszi | May 2001 | B1 |
6323539 | Fujihira et al. | Nov 2001 | B1 |
6344959 | Milazzo | Feb 2002 | B1 |
6677210 | Hebert | Jan 2004 | B1 |
6781422 | Yang | Aug 2004 | B1 |
6836173 | Yang | Dec 2004 | B1 |
6864539 | Ishibashi et al. | Mar 2005 | B2 |
6887750 | Hayashi | May 2005 | B2 |
7388266 | Wu | Jun 2008 | B2 |
20040262660 | Huang | Dec 2004 | A1 |
20050156200 | Kinoshita | Jul 2005 | A1 |
Number | Date | Country |
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05-129425 | May 1993 | JP |
I297207 | May 2008 | TW |
Entry |
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Chinese Examination Report of Taiwan Application No. 095128588, dated on Jul. 14, 2009. |
Number | Date | Country | |
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20080036027 A1 | Feb 2008 | US |