The present invention relates to an integrated circuit for processing a received multi-channel radio signal, in particular to an integrated circuit for processing a broadband multi-channel radio signal for digital television broadcasting and the like.
In general, a receiver system for multi-channel radio communication includes an analog signal processing unit for selecting a desired channel from a received multi-channel radio signal, a digital signal processing unit for performing digital demodulation of a signal of the selected channel and an operation clock generating unit for generating an operation clock signal for the digital signal processing unit based on a reference clock signal supplied from a quartz oscillator or the like. The analog signal processing unit is composed of a bipolar transistor having excellent high frequency and noise characteristics. The digital signal processing unit is composed of a MOS transistor which is advantageous in terms of cost, power consumption and circuit footprint.
In such a receiver system, a harmonic (digital noise) of an operation clock signal supplied from the operation clock generating unit to the digital signal processing unit may leak to the analog signal processing unit to become interference, thereby reducing receiver sensitivity. An explanation of such inconvenience is given below by taking digital terrestrial television broadcasting for mobile terminals (one segment broadcasting) as an example.
The one segment broadcasting contains 49 channels ranging from a channel 13 (474 MHz) to a channel 62 (768 MHz) in a UHF band. Each of the channels uses 6 MHz and an occupied bandwidth of 430 kHz. When the digital signal processing unit of the receiver system is operated by an operation clock signal of 30 MHz, a harmonic of the signal leaks to the analog signal processing unit. As a result, spurious is generated in an integral multiple frequency of 30 MHz. In particular, since the 25th harmonic and a center frequency of a channel 59 are both 750 MHz, the harmonic becomes interference and reduces the receiver sensitivity to the channel.
In view of the above-mentioned problem, a capacitance value of a capacity variable diode of the operation clock generating unit is changed to slightly vary the frequency of the operation clock signal so that mutual interference between the operation clock signal and the channel to be selected is avoided (e.g., see Patent Literature 1). Further, a high-speed operation clock signal for a CPU or the like, which does not affect the channel to be selected, is generated from a low-speed reference clock signal for a time-of-day clock (e.g., see Patent Literature 2). Still further, an interference level of the spurious in the received frequency is measured by a built-in antenna so that the frequency of the operation clock signal is varied when the interference level is equal or higher than a reference value (e.g., see Patent Literature 3).
The above-described conventional receiver systems have the following drawbacks. In the receiver system according to Patent Literature 1, the frequency of the operation clock signal is varied only within a range of ±several tens ppm. Therefore, for the digital terrestrial television broadcasting, in which an occupied bandwidth per channel is high, the influence of the digital noise cannot be sufficiently removed. According to the receiver system of Patent Literature 2, when a local signal for the analog signal processing unit is generated from the low-speed reference clock signal, the frequency ratio between these signals becomes extremely high. As a result, a phase noise characteristic of the local signal is degraded and sufficient receiver sensitivity cannot be obtained. According to the receiver system of Patent Literature 3, a large-scale circuit such as a built-in antenna is required for harmonic detection, resulting in complicated control. This is disadvantageous in terms of power consumption and cost.
As the performance of the MOS transistors has dramatically been enhanced with the development of a CMOS process technology in recent years, radio signal processing by the MOS transistors is now becoming possible. This allows mounting the analog signal processing unit and the digital signal processing unit on the same CMOS substrate. Therefore, expectations are placed not only on the reduction in size, power consumption and cost of the receiver system, but also on the installation of various radio communication applications in radio communication devices such as cellular phones.
When the analog signal processing unit and the digital signal processing unit are composed of different chips, the influence of digital noise is relatively easily avoided by taking measures against it, such as optimization of component layout in a module, enhancement of a power supply and provision of an electromagnetic shield. However, when these units are provided on a single chip, it is difficult to take the same measures. Further, as the analog signal processing unit and the digital signal processing unit share the same substrate, there arises another problem of degradation of receiver sensitivity due to propagation of noise through the substrate.
With the foregoing in mind, an object of the present invention is to reduce the degradation of receiver sensitivity caused by digital noise in a multi-channel radio signal processing integrated circuit.
A means taken by the present invention to achieve the object is to provide an integrated circuit for processing a received multi-channel radio signal including: an analog signal processing unit for generating a local signal based on a reference clock signal supplied from the outside of the integrated circuit and selecting a desired channel from the multi-channel radio signal using the local signal; a digital signal processing unit for performing digital demodulation of a signal of the channel selected by the analog signal processing unit; an operation clock generating unit for generating an operation clock signal for the digital signal processing unit based on the reference clock signal; and a control unit for designating a frequency of the operation clock signal to be generated by the operation clock generating unit in response to the channel selected by the analog signal processing unit.
According to the above-mentioned means, an operation clock signal which does not interfere with the channel selected by the analog signal processing unit is generated based on the reference clock signal based on which the local signal of the analog signal processing unit is generated. Then, the digital signal processing unit is driven by the operation clock signal. Therefore, in the integrated circuit for processing the multi-channel radio signal, degradation of receiver sensitivity caused by digital noise is reduced.
In a preferable manner, the control unit designates the frequency of the operation clock signal by referring to a table in which channels selectable in the analog signal processing unit and frequencies of the operation clock signal to be designated are so associated with each other that a corresponding frequency is designated in response to a selected channel. As the frequency of the operation clock signal is designated in accordance with the information indicated in the table, the designation is performed with ease.
More specifically, the operation clock generating unit has a divider for dividing the frequency of the reference clock signal in a variable division ratio and the control unit designates the division ratio of the divider. Alternatively, the operation clock generating unit has a PLL for outputting the operation clock signal in response to the reference clock signal and the control unit designates an output frequency of the PLL. The PLL performs multiplication or fractional multiplication of the frequency of the reference clock signal to output the operation clock signal. In a preferable manner, the control unit designates the output frequency of the PLL so that a harmonic of the operation clock signal and a harmonic of phase noise in a loop band of the PLL are deviated from the channel selected by the analog signal processing unit. As a result, degradation of receiver sensitivity due to the harmonic of the PLL phase noise is reduced.
Another means taken by the present invention is to provide an integrated circuit for processing a received multi-channel radio signal including: an analog signal processing unit for generating a local signal based on a reference clock signal supplied from an external oscillator capable of changing an oscillatory frequency and selecting a desired channel from the multi-channel radio signal using the local signal; a digital signal processing unit for receiving the reference clock signal as an operation clock signal and performing digital demodulation of a signal of the channel selected by the analog signal processing unit; and a control unit for designating a frequency to be oscillated by the external oscillator in response to the channel selected by the analog signal processing unit.
According to the above-mentioned means, the digital signal processing unit is driven by the reference clock signal based on which the local signal of the analog signal processing unit is generated and the frequency of the reference clock signal is set to a certain frequency that does not interfere with the channel selected by the analog signal processing unit. Therefore, in the integrated circuit for processing the multi-channel radio signal, the degradation of receiver sensitivity caused by digital noise is reduced. Further, since there is no need of generating the operation clock signal for the digital signal processing unit within the integrated circuit, the footprint of the integrated circuit is reduced.
Another means taken by the present invention is to provide an integrated circuit for processing a received multi-channel radio signal including: a selector unit for receiving a plurality of different reference clock signals from an external oscillator and selectively outputting any one of the reference clock signals; an analog signal processing unit for generating a local signal based on any one of the plurality of reference clock signals and selecting a desired channel from the multi-channel radio signal using the local signal; a digital signal processing unit for receiving the reference clock signal output from the selector unit as an operation clock signal and performing digital demodulation of a signal of the channel selected by the analog signal processing unit; and a control unit for controlling the signal selection by the selector unit in response to the channel selected by the analog signal processing unit. The analog signal processing unit may receive the reference clock signal output from the selector unit.
According to the above-described means, a certain reference clock signal that does not interfere with the channel selected by the analog signal processing unit is selected as the operation clock signal for the digital signal processing unit from the plurality of reference clock signals including the reference clock signal based on which the local signal of the analog signal processing unit is generated. Therefore, in the integrated circuit for processing the multi-channel radio signal, the degradation of receiver sensitivity caused by digital noise is reduced. Further, since the operation clock signal for the digital signal processing unit is obtained by merely selecting any one of the plurality of reference clock signals, the circuit structure is simplified and the footprint of the integrated circuit is reduced.
According to the present invention, in a multi-channel radio signal processing integrated circuit, in particular in a 1-chip multi-channel radio signal processing integrated circuit, the degradation of receiver sensitivity caused by digital noise is reduced.
Hereinafter, best modes for carrying out the present invention are described with reference to the drawings.
More specifically, the operation clock generating unit 103 may be composed of a divider capable of changing the division ratio. As shown in
Further, the operation clock generating unit 103 may be composed of a PLL (a phase locked loop). As shown in
Next, taking one segment broadcasting as an example, the designation of the frequency of the operation clock signal CK by the control unit 104 is explained below.
More specifically, when the operation clock generating unit 103 is composed of the divider 103a as shown in
More specifically, when the operation clock generating unit 103 is composed of the PLL 103b (in particular, a multiplication PLL) as shown in
More specifically, when the operation clock generating unit 103 is composed of the PLL 103b (in particular, a fractional multiplication PLL) as shown in
As described above, in the multi-channel radio signal processing integrated circuit according to the present embodiment, the receiver sensitivity of the analog signal processing unit to the received channel is not degraded by the harmonics of the operation clock signal for the digital signal processing unit.
When the operation clock generating unit 103 is composed of the PLL, a harmonic of phase noise in a loop band of the PLL may interfere with the received channel, thereby reducing the receiver sensitivity. For example, when a 27.5 MHz operation clock signal CK is supplied from the operation clock generating unit 103 to the digital signal processing unit 102, the 19th harmonic (a frequency of 522.5 MHz) of the signal is deviated only by 500 kHz from 522 MHz which is a center frequency of a channel 21 for the one segment broadcasting. However, when the harmonic of the phase noise makes interference with the channel, the receiver sensitivity to the channel may be degraded. Therefore, when the PLL is employed as the operation clock generating unit 103, it is preferable to generate the operation clock signal CK while paying attention to the harmonic of the phase noise.
As shown in
According to the present embodiment, there is no need of providing a circuit for generating the operation clock signal for the digital signal processing unit. Therefore, as compared with the circuit of Embodiment 1, the circuit size is reduced. For waveform shaping of the reference clock signal REF, a buffer circuit may be provided.
For example, when the frequencies of the reference clock signals REF1 and REF2 are 28 MHz and 35 MHz, respectively, the harmonics of the operation clock signals CK having these frequencies and the channels for the one segment broadcasting establish the relationship as shown in
According to the present embodiment, the structure of the control unit is more simplified than the structures of the control units of Embodiments 1 and 2. Therefore, the total circuit size is reduced to a further extent. In place of the operation clock signal CK output from the selector unit 106, any one of the reference clock signals REF1 and REF2 may be applied to the analog signal processing unit 101 in a fixed manner.
In each of the above-described embodiments, the digital signal processing unit 102 may be operated by suitably switching three or more operation clock signals CK. The table 105 can be omitted. When the table 105 is omitted, the control unit 104 may be configured so that it calculates a frequency of the operation clock signal which does not make any interference with the channel selected by the analog signal processing unit 101.
The present invention is not only limited to the receiver system, but also applicable to a sender system. For the realization of the sender system, the frequency of the operation clock signal is determined so that a harmonic of the operation clock signal for the digital signal processing unit does not make interference with a channel to be sent from the analog signal processing unit.
In each of the above-described embodiments, the analog signal processing unit 101, the digital signal processing unit 102 and other components may not always be provided on the same chip.
The multi-channel radio signal processing integrated circuit of the present invention has high receiver sensitivity with respect to all channels. Therefore, it is useful for multi-channel broadcasting receivers for receiving broadband multi-channel digital television broadcasting and multi-channel radio communication devices for receiving/sending a broadband multi-channel radio communication signal.
Number | Date | Country | Kind |
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2007-036303 | Feb 2007 | JP | national |
Filing Document | Filing Date | Country | Kind | 371c Date |
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PCT/JP07/72453 | 11/20/2007 | WO | 00 | 11/6/2008 |