Claims
- 1. A microprocessor chip comprising:
- (1) a digital video decoder including
- a. a first Huffman decoder for receiving variable length encoded digital video data and expanding the data;
- b. an inverse quantizer for receiving data from the first Huffman decoder and dequantizing the data;
- c. an inverse discrete cosine transformer for receiving dequantizied data from the inverse quantizer and inverse discrete cosine transforming the data;
- d. a second Huffman decoder for receiving variable length encoded digital video data and expanding the data;
- e. a motion compensator for receiving data from (i) the second Huffman decoder, and (ii) a past frame storage and a future frame storage, and forming motion compensated image data therefrom;
- f. a summer for summing image data from the motion compensator and the inverse discrete cosine transformer; and
- g. said past frame storage and said future frame storage, both receiving inverse discrete cosine transformed data from the summer; and
- (2) an on-chip shift register latch Read Only Memory as a look-up memory for the inverse discrete cosine transformer, said shift register latch Read Only Memory comprising:
- a. a first shift register latch for receiving input data from a pull-up resistor;
- b. a second shift register latch adapted for use as a read only memory cell for storing the input data from the first shift register latch;
- c. a selector and ROM address decoder for selecting shift register latch memory cells to be read from the shift register latch Read Only Memory to the inverse discrete cosine transformer; and
- d. a Read Only Memory data output from the shift register latch Read Only Memory to the inverse discrete cosine transformer.
CROSS-REFERENCE TO RELATED APPLICATION
This is a continuation-in-part of our commonly assigned, U.S. application, Ser. No. 08/374,267, filed Jan. 18, 1995, now abandoned, for INTEGRATED CIRCUIT INCLUDING FULLY TESTABLE SMALL SCALE READ ONLY MEMORY CONSTRUCTED OF LEVEL SENSITIVE SCAN DEVICE SHIFT REGISTER LATCHES.
US Referenced Citations (10)
Non-Patent Literature Citations (3)
Entry |
IBM TDB, vol. 34, No. 7A, Dec. 1991; "Level-Sensitive Scan Design Latch-Trigger Implementation Of Microprocessor Architecture". |
IBM TDM, vol. 25, No. 3A, Aug. 1982; "Partitioning Microcode For A Microprocessor-Based Mainframe By . . . ". |
IBM TDB, vol. 21, No. 1, Jun. 1978; "Dynamic Random-Access Memory With Read-Only Memory Characteristics At Power-On Time". |
Continuation in Parts (1)
|
Number |
Date |
Country |
Parent |
374267 |
Jan 1995 |
|