Patent Application
20060119380
In integrated circuits, such as microprocessors, memories, and the like, signals may be routed for relatively long distances using transmission lines. A transmission line may be a bus, a printed circuit board trace, or other types of electrical conductors for transporting a signal. Typically, a printed circuit board trace has a characteristic impedance of between 50 and 75 ohms. In complementary metal-oxide semiconductor (CMOS) circuits, the input impedance of a gate of a CMOS transistor is usually very high. The receiving end, or far end, of the transmission line is typically connected to an input of a logic circuit, where the input impedance is higher than the characteristic impedance of the transmission line. When the impedance coupled to the far end of the transmission line is different than the impedance of the transmission line, the signal will be reflected back to the sending end. Depending on the sending end impedance, the signal may overshoot/undershoot a planned steady-state voltage for the logic state. The signal may be reflected back and forth many times between the near end and the far end, causing oscillatory behavior of the signal at both ends. This repeated overshooting and undershooting of the signal is commonly known as “ringing,” and results in reduced noise immunity and increased time for the signal to become, and remain, stable at the far end. Impedance matching is the practice of matching the impedance of the driver and/or the load to the characteristic impedance of the transmission line to reduce ringing and facilitate the most efficient transfer of signals.
As bus speeds increase above 100 MHz, impedance mismatches become a significant concern as timing margins are reduced as a result of the increased clock frequency. A number of different approaches have been used to account for impedance mismatches in electronic data systems. Some of these approaches include adding passive external elements (resistors, inductors, etc.); adjusting the drive strength of output drivers; and actively terminating signal transmission lines.
The joint electron device engineering council (JEDEC) solid-state technology association standards define input and output specifications independently of each other. Accordingly, drivers and receivers are defined independently from each other. First and second voltages for receivers are defined. A sample circuit model 10 is illustrated in
Other on-chip solutions require the use of separate test input/output (I/O) pads for determining suitable impedance matching. In one example, an external test pad is used to determine suitable pull-up circuit impedance whereas a separate additional test pad is used to determine suitable impedance matching for a pull-down circuit of the output buffer. The use of additional test pads and additional external resistors can impact power consumption, reliability, and cost.
Solutions that actively terminate transmission lines share many of the drawbacks of solutions that use external passive elements and solutions that adjust output drive strength. That is, active termination requires additional off chip elements, increases power consumption, and is susceptible to process, voltage, and temperature variations.
Therefore, it is desirable to introduce low-cost systems and methods for reducing power consumption in input/output circuits.
One embodiment of an integrated circuit die comprises first and second pads, a termination element, and a receiver. The first pad is coupled to a termination reference voltage generated external to the die. The termination element is coupled between the first pad and an input node of the receiver. The second pad is coupled to a transmission line external to the die. The transmission line is coupled to a driver output and the input node of the receiver.
One embodiment of a transceiver system for digital logic circuits comprises a printed circuit board, a package, and an integrated circuit die. The printed circuit board is configured to provide a termination reference voltage at an interface. The package is coupled to the interface and configured with a plurality of conductive links that traverse the package. A first conductive link comprises the termination reference voltage and a second conductive link comprises a data signal. The integrated circuit die is configured with a plurality of pads, a termination element, and a receiver. The pads transport input and output signals. The termination element is coupled in series between a first pad and an input node of the receiver. The first pad is coupled to the first conductive link. A second pad is coupled to the second conductive link and the input node.
Another embodiment describes a method for reducing on die power dissipation while providing on die signal termination. The method comprises receiving a termination reference voltage at a first input of an integrated circuit die, applying the first signal to a single termination element coupled in series between the first input and a receiver input to generate a common node reference voltage, receiving a second signal at a second input of the integrated circuit die, and coupling the second signal to the receiver input.
The present systems and methods for providing input/output signal termination with reduced power dissipation on an integrated circuit die, as defined in the claims, can be better understood with reference to the following drawings. The components within the drawings are not necessarily to scale relative to each other; emphasis instead is placed upon clearly illustrating the principles of the systems and methods.
The present systems and methods provide an alternative for on-die input signal termination that can result in as much as a 5 fold reduction in on die power dissipation for input signal termination. The present circuit arrangement and termination method retains the signal integrity and timing benefits associated with signal termination techniques while using significantly less power.
Present integrated circuit signal transmission systems and methods for reducing on die power dissipation while providing on die signal termination supply a termination reference from an off die source to a single termination element coupled in series with an input of the designated receiver. The single termination element provides a linear termination impedance. An on die switch enables the termination to be selectable. By matching the equivalent resistance of the termination element with the pull-down and pull-up resistors in the output stage of the driver amplifying the input data signal, the overall power dissipated in signal termination at the receiver is reduced. Accordingly, the power to signal ratio is relaxed over that in conventional integrated circuits that use a termination network to generate a common-mode voltage at the input to the receiver. The reduced current loads that result allow designers to increase the logic density on the integrated circuit and use interconnecting packages that are less expensive to manufacture.
Turning to the drawings that illustrate various embodiments of systems and methods for reducing on die power dissipation while providing on die input signal termination,
Printed circuit board 110 provides the termination reference along conductor 112 to interface 113 and the core logic supply along conductor 118 to interface 119. One or both of the termination reference and the core logic supply can be generated via one or more power supplies coupled to printed circuit board 110. Alternatively, one or both of the termination reference and the core logic supply can be generated on printed circuit board 110.
Printed circuit board 110 further provides an input data signal along conductor 114 to interface 115. The input data signal is generated by a driver external to the receiving IC 150. Printed circuit board 110 is also configured to receive a data signal from receiving IC 150 via the package 130 at interface 117. The data signal is coupled to one or more destinations on or off printed circuit board 110 via conductor 116.
Package 130 is coupled to printed circuit board 110 via a plurality of conductive connections such as solder balls 120, 122, 124, and 126. Solder ball 120 connects interface 113 with pad 131 to couple the termination reference from the printed circuit board 110 to receiving IC 150. The termination reference traverses conductor 132 and conductor 142 before it is applied via first input 152 of the receiving IC 150. Solder ball 122 connects interface 115 with pad 133 to couple the input data signal from printed circuit board 110 to receiving IC 150. The input data signal traverses conductor 134 and pad 135 in package 130 before it is coupled to second input 154 of receiving IC 150. The output data signal is coupled from output 154 via conductor 142, pad 138, and conductor 137 to pad 136. Solder ball 124 connects interface 117 with pad 136 to couple the output data signal from receiving IC 150 to printed circuit board 110 where it can be forwarded to one or more destinations on or off the printed circuit board 110. Solder ball 126 connects interface 119 with pad 139 to couple the core logic supply from the printed circuit board 110 to receiving IC 150. The core logic supply traverses conductor 140 and pad 141 in package 130 before it is coupled to one or more core logic circuits (not shown) on receiving IC 150. Components of the package 130 can be implemented with known or to be developed manufacturing techniques. The various pads 131, 133, 135, 136, 138, 139, and 141, as well as the various conductors 132, 134, 137, 140 will be configured such that they can carry current delivered to and from the receiving IC 150 with an adequate margin.
The termination reference provided at first interface 154 is coupled to a single termination element 160 via conductor 155. The input data signal provided at second interface 154 is coupled to the output of the single termination element 160 and to the input of receiver 170 via conductor 165. The output of receiver 170 is coupled to output 154 via conductor 175. Components of the receiving IC 150 can be implemented with known or to be developed integrated circuit manufacturing techniques or technologies.
Receiving IC 150 includes a first input 152, a second input 154, single termination element 160, and receiver 170. Receiver 170 is configured with an input 336, an output 337, and is coupled between the core logic supply and electrical ground. Single termination element 160 is coupled in series between a termination reference and node 334 with input 162 proximal to the termination reference and output 164 proximal to node 334. Node 334 is coupled to second input 154 and receiver input 336. Single termination element 160 can include a single resistor, one or more selectable resistors, and or one or more transistors. When the resistance of single termination element 160 is substantially equal to the resistance value of pull-up resistor 12 and pull-down resistor 13 in transmitting IC 11 the signal transmitted from driver 16 to receiver 170 can meet the termination logic standards promulgated by the JEDEC with a significant reduction in on die power dissipation.
For example, a conventional signal transmission circuit with driver pull-up and pull-down resistors having resistance values of 45 ohms and receiver pull-up and pull-down resistance values of 90 ohms with an on die voltage of 2.75 volts supplied to the receiver termination network results in a termination current of 22.92 mA with 15.28 mA being grounded in the driver pull-down resistor and 7.64 mA being grounded via the receiver. Accordingly, the receiver termination network dissipates 52.53 mW and the driver dissipates an additional 10.50 mW. When the single termination element 160 of
Switch 340 is used to controllably apply the termination reference to the receiving IC 150. Switch 340 is opened and the termination reference removed from the receiving IC 150 for test operations (e.g., leakage, tri-state, electrostatic discharge sensitivity, etc.) and for functional operations when the receiver 150 is used as an output driver. Switch 340 is closed when receiving IC 150 is designated for receiving a data signal at the second input 154.
The signal voltage levels as observed at the receiver 170 of
Any process descriptions or blocks in the flow diagrams illustrated in
When the resistance values of the pull-up and pull-down resistors associated with a driver that is supplying the data signal to the receiver closely approximate the resistance value of the termination element, the power dissipated on the integrated circuit die of the receiver is significantly reduced from conventional receivers that use a termination network with a network element coupled between the receiver input and electrical ground.
The driver termination element is part of a voltage divider applied between the reference voltage and electrical ground. The voltage divider includes a pull-down resistor coupled between the driver output and electrical ground. The voltage divider also includes a pull-up resistor coupled between the core logic supply voltage and the driver output. When the data signal of block 604 is less than half the voltage level of termination reference, the pull-down resistor assists the driver in providing an amplified data signal to the receiver that is between the common-mode voltage of the receiver and electrical ground. When the data signal of block 604 is greater than half the voltage level of the termination reference, the pull-up resistor assists the driver in providing an amplified data signal to the receiver that is between the common-mode voltage of the receiver and the core logic supply voltage. When the resistance values of the pull-up and pull-down resistors closely approximates the resistance value of the receiver termination element, the power dissipated on the integrated circuit die of the receiver is significantly reduced from conventional receivers that use a termination network with a network element coupled between the receiver input and electrical ground.
It should be emphasized that the above-described embodiments are merely examples of implementations of the systems and methods for providing input/output signal termination with reduced power dissipation on an integrated circuit die. Many variations and modifications may be made to the above-described embodiments. All such modifications and variations are intended to be included herein within the scope of this disclosure and protected by the following claims.
