Patent Application
20250194179
For the past several decades, the scaling of features in integrated circuit (IC) structures has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory or logic devices on a chip, lending to the fabrication of products with increased capacity. The drive for the ever-increasing capacity, however, is not without issue. The necessity to optimize every portion of an IC structure becomes increasingly significant.
Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings.
Disclosed herein is a fabrication method and associated IC structures, and devices including asymmetric source and drain regions (referred to herein as “asymmetric S/D regions”). The systems, methods and devices of this disclosure each have several innovative aspects, no single one of which is solely responsible for all desirable attributes disclosed herein. Details of one or more implementations of the subject matter described in this specification are set forth in the description below and the accompanying drawings.
For purposes of illustrating fabrication of nanoribbon-based transistors with asymmetric S/D regions, described herein, it might be useful to first understand phenomena that may come into play during IC fabrication. The following foundational information may be viewed as a basis from which the present disclosure may be properly explained. Such information is offered for purposes of explanation only and, accordingly, should not be construed in any way to limit the broad scope of the present disclosure and its potential applications.
Non-planar transistors such as double-gate transistors, tri-gate transistors, FinFETs, and nanowire/nanoribbon/nanosheet transistors refer to transistors having a non-planar architecture. In comparison to a planar architecture where the transistor channel has only one confinement surface, a non-planar architecture is any type of architecture where the transistor channel has more than one confinement surface. A confinement surface refers to a particular orientation of the channel surface that is confined by the gate field. Non-planar transistors potentially improve performance relative to transistors having a planar architecture, such as single-gate transistors.
Nanoribbon-based transistors may be particularly advantageous for continued scaling of metal-oxide-semiconductor (MOS) technology nodes due to the potential to form gates on all four sides of a channel material (hence, such transistors are sometimes referred to as “gate all around” transistors). As used herein, the term “nanoribbon” refers to an elongated structure of a semiconductor material having a longitudinal axis parallel to a support structure (e.g., a substrate, a die, a chip, or a wafer; also referred to herein as, simply, “support”) over which such a structure is built. Typically, a length of a such a structure (i.e., a dimension measured along the longitudinal axis, shown in the present drawings to be along the y-axis of an example x-y-z coordinate system) is greater than each of a width (i.e., a dimension measured along the x-axis of the example coordinate system shown in the present drawings) and a thickness (i.e., a dimension measured along the z-axis of the example coordinate system shown in the present drawings). In some settings, the terms “nanoribbon” or “nanosheet” have been used to describe elongated semiconductor structures that have a rectangular transverse cross-section (i.e., a cross-section in a plane perpendicular to the longitudinal axis of the structure), while the term “nanowire” has been used to describe similar elongated structures but with circular transverse cross-sections. In the present disclosure, the term “nanoribbon” is used to refer to all such nanowires, nanoribbons, and nanosheets, as well as elongated semiconductor structures with a longitudinal axis parallel to the support structures and with having transverse cross-sections of any geometry (e.g., transverse cross-sections in the shape of an oval or a polygon with rounded corners). A transistor may then be described as a “nanoribbon-based transistor” if the channel of the transistor is a portion of a nanoribbon, i.e., a portion around which a gate stack of a transistor may wrap around. The semiconductor material in the portion of the nanoribbon that forms a channel of a transistor may be referred to as a “channel material,” with source and drain (S/D) regions of a transistor provided on either side of the channel material.
As mentioned briefly above, the drive for increased capacity has led to shrinking transistor sizes. Smaller transistors can be achieved by shrinking the dimensions of one or more elements of the transistors. However, shrinking transistor sizes has led to challenges related to short channel effects. As the name suggests, short channel effects are typically greater as the length of the channel becomes shorter. Short channel effects can result in issues such as increased leakage current, drain-induced barrier lowering, velocity saturation, unintentional reduction in threshold voltage, and unintentional subthreshold conduction through the transistor, all of which can negatively impact performance and/or result in failure of the transistors. One approach for achieving smaller transistor sizes while keeping short channel effects within acceptable limits is to focus on reducing the dimensions of other elements of the transistor, such as the S/D regions. However, shrinking the size of the S/D regions can also result in yield and performance issues stemming from, e.g., poor electrical conductivity and process limitations.
Embodiments of the present disclosure are based on recognition that forming nanoribbon transistors with asymmetric source and drain regions can enable achieving smaller transistor sizes without excessive short channel effects. Conventionally, the source and drain regions of nanoribbon transistors are symmetric (e.g., have about the same widths). Shrinking the width of only one of the S/D regions can enable fabrication of a nanoribbon transistor with a larger channel length without increasing the overall width of the transistor and without the yield and performance issues associated with shrinking the size of both S/D regions. Shrinking the width of one of the S/D regions (e.g., the source region) can also, or alternatively, enable a larger width for the other S/D region and contact structure (e.g., the drain region). In some examples, shrinking the width of one of the S/D regions (e.g., the source region) and/or the corresponding S/D contact structure may not negatively impact the yield and performance as much as shrinking the other S/D region (e.g., the drain region) and/or corresponding S/D contact structure. Additionally, in one example, the narrower S/D region can be coupled with a contact structure from a side of the IC structure that is opposite the side from which the S/D regions were formed (e.g., a back side). In one such example, providing a back-side contact structure for the narrower S/D region can enable more flexibility in ensuring the S/D contact makes sufficient contact with the narrower S/D region for good current conduction. Thus, in one example, a narrower source region may be coupled with a back-side source contact structure, and a wider drain region may be coupled with a front side contact structure. In accordance with examples described herein, short channel effects may be improved due to the increased channel length made possible by the asymmetric S/D regions.
IC structures as described herein, in particular IC structures including asymmetric source and drain regions, may be implemented in one or more components associated with an IC or/and between various such components. In various embodiments, components associated with an IC include, for example, transistors, diodes, power sources, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, etc. Components associated with an IC may include those that are mounted on an IC or those connected to an IC. The IC may be either analog or digital and may be used in a number of applications, such as microprocessors, optoelectronics, logic blocks, audio amplifiers, etc., depending on the components associated with the IC. In some embodiments, IC structures as described herein may be included in a radio frequency IC (RFIC), which may, e.g., be included in any component associated with an IC of a radio frequency (RF) receiver, an RF transmitter, or an RF transceiver, e.g., as used in telecommunications within base stations (BS) or user equipment (UE). Such components may include, but are not limited to, power amplifiers, low-noise amplifiers, RF filters (including arrays of RF filters, or RF filter banks), switches, upconverters, downconverters, and duplexers. In some embodiments, IC structures as described herein may be included in memory devices or circuits. In some embodiments, IC structures as described herein may be employed as part of a chipset for executing one or more related functions in a computer.
For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without the specific details or/and that the present disclosure may be practiced with only some of the described aspects. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative implementations. The terms “substantially,” “close,” “approximately,” “near,” and “about,” generally refer to being within +/−10% of a target value, e.g., within +/−5% of a target value, based on the context of a particular value as described herein or as known in the art. Similarly, terms indicating orientation of various elements, e.g., “coplanar,” “perpendicular,” “orthogonal,” “parallel,” or any other angle between the elements, generally refer to being within +/−10% of a target value, e.g., within +/−5% of a target value, based on the context of a particular value as described herein or as known in the art.
In the following description, references are made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, embodiments that may be practiced. It is to be understood that other embodiments may be utilized, and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense. For convenience, if a collection of drawings designated with different letters are present, e.g.,
In the drawings, while some schematic illustrations of example structures of various devices and assemblies described herein may be shown with precise right angles and straight lines, this is simply for ease of illustration, and embodiments of these assemblies may be curved, rounded, or otherwise irregularly shaped as dictated by, and sometimes inevitable due to, the fabricating processes used to fabricate semiconductor device assemblies. Therefore, it is to be understood that such schematic illustrations may not reflect real-life process limitations which may cause the features to not look so “ideal” when any of the structures described herein are examined using e.g., scanning electron microscopy (SEM) images or transmission electron microscope (TEM) images. In such images of real structures, possible processing defects could also be visible, e.g., not-perfectly straight edges of materials, tapered vias or other openings, inadvertent rounding of corners or variations in thicknesses of different material layers, occasional screw, edge, or combination dislocations within the crystalline region, and/or occasional dislocation defects of single atoms or clusters of atoms. There may be other defects not listed here but that are common within the field of device fabrication. Inspection of layout and mask data and reverse engineering of parts of a device to reconstruct the circuit using e.g., optical microscopy, TEM, or SEM, and/or inspection of a cross-section of a device to detect the shape and the location of various device elements described herein using, e.g., Physical Failure Analysis (PFA) would allow determination of the presence of IC structures including asymmetric source and drain regions as described herein.
Various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. For example, the terms “oxide,” “carbide,” “nitride,” “silicide,” etc. refer to compounds containing, respectively, oxygen, carbon, nitrogen, silicon, etc.; the term “high-k dielectric” refers to a material having a higher dielectric constant than silicon oxide; the term “low-k dielectric” refers to a material having a lower dielectric constant than silicon oxide. Materials referred to herein with formulas or as compounds cover all materials that include elements of the formula or a compound, e.g., TiSi or titanium silicide may refer to any material that includes titanium and silicon, WN or tungsten nitride may refer to any material that includes tungsten and nitrogen, etc. The term “insulating” means “electrically insulating,” the term “conducting” means “electrically conducting,” unless otherwise specified. Furthermore, the term “connected” may be used to describe a direct electrical or magnetic connection between the things that are connected, without any intermediary devices, while the term “coupled” may be used to describe either a direct electrical or magnetic connection between the things that are connected, or an indirect connection through one or more passive or active intermediary devices. A first component described to be electrically coupled to a second component means that the first component is in conductive contact with the second component (i.e., that a conductive pathway is provided to route electrical signals/power between the first and second components).
Various operations may be described as multiple discrete actions or operations in turn, in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. These operations may not be performed in the order of presentation. Operations described may be performed in a different order from the described embodiment. Various additional operations may be performed, and/or described operations may be omitted in additional embodiments.
For the purposes of the present disclosure, the phrase “A and/or B” means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The term “between,” when used with reference to measurement ranges, is inclusive of the ends of the measurement ranges.
The description uses the phrases “in an embodiment” or “in embodiments,” which may each refer to one or more of the same or different embodiments. The terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous. The disclosure may use perspective-based descriptions such as “above,” “below,” “top,” “bottom,” and “side”; such descriptions are used to facilitate the discussion and are not intended to restrict the application of disclosed embodiments. The accompanying drawings are not necessarily drawn to scale. Unless otherwise specified, the use of the ordinal adjectives “first,” “second,” and “third,” etc., to describe a common object, merely indicate that different instances of like objects are being referred to and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner. Although some materials may be described in singular form, such materials may include a plurality of materials, e.g., a semiconductor material may include two or more different semiconductor materials.
Implementations of the present disclosure may be formed or carried out on any suitable support 102, such as a substrate, a die, a wafer, or a chip. The support 102 may, e.g., be the wafer 1500 of
The nanoribbon 104 may take the form of a nanowire or nanoribbon, for example. In some embodiments, an area of a transversal cross-section of the nanoribbon 104 (i.e., an area in the x-z plane of an x-y-z coordinate system shown in
In various embodiments, the semiconductor material of the nanoribbon 104 may be composed of semiconductor material systems including, for example, N-type or P-type materials systems. In some embodiments, the nanoribbon 104 may include a high mobility oxide semiconductor material, such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide. In some embodiments, the nanoribbon 104 may include a combination of semiconductor materials. In some embodiments, the nanoribbon 104 may include a monocrystalline semiconductor, such as silicon (Si) or germanium (Ge). In some embodiments, the nanoribbon 104 may include a compound semiconductor with a first sub-lattice of at least one element from group Ill of the periodic table (e.g., Al, Ga, In), and a second sub-lattice of at least one element of group V of the periodic table (e.g., P, As, Sb).
For some example N-type transistor embodiments (i.e., for the embodiments where the transistor 110 is an N-type metal-oxide-semiconductor (NMOS) transistor), the channel material of the nanoribbon 104 may include a III-V material having a relatively high electron mobility, such as, but not limited to InGaAs, InP, InSb, and InAs. For some such embodiments, the channel material of the nanoribbon 104 may be a ternary III-V alloy, such as InGaAs, GaAsSb, InAsP, or InPSb. For some InxGa1-xAs fin embodiments, In content (x) may be between 0.6 and 0.9, and may advantageously be at least 0.7 (e.g., In0.7Ga0.3As). For some example P-type transistor embodiments (i.e., for the embodiments where the transistor 110 is a P-type metal-oxide-semiconductor (PMOS) transistor), the channel material of the nanoribbon 104 may advantageously be a group IV material having a high hole mobility, such as, but not limited to Ge or a Ge-rich SiGe alloy. For some example embodiments, the channel material of the nanoribbon 104 may have a Ge content between 0.6 and 0.9, and advantageously may be at least 0.7.
In some embodiments, the channel material of the nanoribbon 104 may be a thin-film material, such as a high mobility oxide semiconductor material, such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, indium gallium zinc oxide (IGZO), gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide. In general, if the transistor formed in the nanoribbon is a thin-film transistor (TFT), the channel material of the nanoribbon 104 may include one or more of tin oxide, cobalt oxide, copper oxide, antimony oxide, ruthenium oxide, tungsten oxide, zinc oxide, gallium oxide, titanium oxide, indium oxide, titanium oxynitride, indium tin oxide, indium zinc oxide, nickel oxide, niobium oxide, copper peroxide, IGZO, indium telluride, molybdenite, molybdenum diselenide, tungsten diselenide, tungsten disulfide, N- or P-type amorphous or polycrystalline silicon, germanium, indium gallium arsenide, silicon germanium, gallium nitride, aluminum gallium nitride, indium phosphite, and black phosphorus, each of which may possibly be doped with one or more of gallium, indium, aluminum, fluorine, boron, phosphorus, arsenic, nitrogen, tantalum, tungsten, and magnesium, etc. In some embodiments, the channel material of the nanoribbon 104 may have a thickness between about 5 and 75 nanometers, including all values and ranges therein. In some embodiments, a thin-film channel material may be deposited at relatively low temperatures, which allows depositing the channel material within the thermal budgets imposed on back-end fabrication to avoid damaging other components, e.g., front-end components such as the logic devices.
A gate stack 106 including a gate electrode material 108 and, optionally, a gate insulator material 112, may wrap entirely or almost entirely around a portion of the nanoribbon 104 as shown in
The gate electrode material 108 may include one or more gate electrode materials, where the choice of the gate electrode materials may depend on whether the transistor 110 is a PMOS transistor or an NMOS transistor. For a PMOS transistor, gate electrode materials that may be used in different portions of the gate electrode material 108 may include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides (e.g., ruthenium oxide). For an NMOS transistor, gate electrode materials that may be used in different portions of the gate electrode material 108 include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide). In some embodiments, the gate electrode material 108 may include a stack of a plurality of gate electrode materials, where zero or more materials of the stack are workfunction (WF) materials and at least one material of the stack is a fill metal layer. Further materials/layers may be included next to the gate electrode material 108 for other purposes, such as to act as a diffusion barrier layer or/and an adhesion layer.
In some embodiments, the gate insulator material 112 may include one or more high-k dielectrics including any of the materials discussed herein with reference to the insulator material that may surround portions of the transistor 110. In some embodiments, an annealing process may be carried out on the gate insulator material 112 during fabrication of the transistor 110 to improve the quality of the gate insulator material 112. The gate insulator material 112 may have a thickness that may, in some embodiments, be between about 0.5 nanometers and 3 nanometers, including all values and ranges therein (e.g., between about 1 and 3 nanometers, or between about 1 and 2 nanometers). In some embodiments, the gate stack 106 may be surrounded by a gate spacer, not shown in
Turning to the S/D regions 114 of the transistor 110, in some embodiments, the S/D regions may be highly doped, e.g., with dopant concentrations of about 1021 cm-3, in order to advantageously form Ohmic contacts with the respective S/D contacts (not shown in
The S/D regions 114 of the transistor 110 may generally be formed using either an implantation/diffusion process or an etching/deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the nanoribbon 104 to form the source and drain regions. An annealing process that activates the dopants and causes them to diffuse further into the nanoribbon 104 may follow the ion implantation process. In the latter process, portions of the nanoribbon 104 may first be etched to form recesses at the locations of the future S/D regions 114. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the S/D regions 114. In some implementations, the S/D regions 114 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some implementations, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In further embodiments, the S/D regions 114 may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. And in further embodiments, one or more layers of metal and/or metal alloys may be used to form the S/D regions 114. In some embodiments, a distance between the first and second S/D regions 114 (i.e., a dimension measured along the longitudinal axis 120 of the nanoribbon 104) may be between about 5 and 40 nanometers, including all values and ranges therein (e.g., between about 22 and 35 nanometers, or between about 20 and 30 nanometers).
The IC structure 100 shown in
Turning first to
The IC structure 200A of
The channel regions 226 are between S/D regions 259-1 and 259-2, where one of the regions 259-1, 259-2 is a source region and the other of the regions 259-1, 259-2 is a drain region. In one example, the S/D regions 259-1, 259-2 are regions including a doped semiconductor material, which act as source and drain regions for a transistor. The IC structure 200A includes a first contact structure 294-1 coupled with the first S/D region 259-1 from a first side 245 of the IC structure 200A (referred to herein as a front side, which may also be a front side of a wafer in or on which the IC structure 200A is formed). The IC structure 200A further includes a second contact structure 294-2 coupled with the second S/D region 259-2 from a second side 247 of the IC structure 200A (referred to herein as a back side of the IC structure 200A, which may also be a back side of a wafer in or on which the IC structure 200A is formed). The IC structure also includes an interface material 261 between the S/D regions 259-1, 259-2 and the conductive material 280 of the respective S/D contact structures 294-1, 294-2.
As can be seen in
In one example, the extent to which the width 210-2 of the S/D region 259-2 can be reduced relative to the width 210-1 may depend on factors such as process limitations, the contact area between the S/D region 259-2 and the corresponding contact structure 294-2 to enable sufficient conduction, and desired electrical characteristics such as resistance and current conductance. In one such example, the width 210-2 is 5-60% smaller than the width 210-1. In other examples, the width 210-2 is 20-40% smaller, or 25-35% smaller than the width 210-1. In one example, the difference in width between the S/D regions 259-1, 259-2 is in a range of about 2-5 nanometers. For example, if the width 210-1 of the S/D region 259-1 is about 11 or 12 nanometers, the width of the S/D region 259-2 may be about 8 nanometers. However, other widths of S/D regions are possible (e.g., the S/D regions 259-1, 259-2 may have widths that are less than 8 nanometers or greater than 12 nanometers).
In accordance with some examples, the widths of the S/D contact structures may also be different. For example, the IC structure 200A depicted in
Thus, the example IC structure 200A illustrated in
Although the operations of the method of
In addition, the example fabricating method of
Turning to
For example, the IC structure 400A of
As shown in
The semiconductor material 432 may be any of the semiconductor/channel materials described above with reference to the nanoribbon 104 of
Thus, the material 434 may be any suitable sacrificial material that is etch-selective with respect to the semiconductor material 432. Selecting the material 434 to be a semiconductor material may be particularly advantageous because it may improve quality of the semiconductor material 432 if the semiconductor material 432 is epitaxially grown on the material 434. In some embodiments, the process may include epitaxially growing layers of the semiconductor material 432 and the material 434 (e.g., another semiconductor material) in an alternating manner. In other embodiments, alternate layers of the semiconductor material 432 and the material 434 may be provided in the process using other techniques, such as layer transfer or thin-film deposition. Although
Thus, the fin 440 may be shaped as a structure that extends away from the support 401 and may include a subfin 442 at the bottom, the subfin being a portion of the respective fin that is at least partially enclosed by an insulator material 436. In some embodiments, the subfin 442 may include the bottom layer of the semiconductor material 432, as well as an upper portion of the support 401, as is shown in
In the example illustrated in
In various embodiments, any suitable patterning techniques may be used to form the fin 440, such as, but not limited to, photolithographic or electron-beam (e-beam) patterning, possibly in conjunction with a suitable etching technique, e.g., a dry etch, such as e.g., RF reactive ion etch (RIE) or inductively coupled plasma (ICP) RIE. In some embodiments, the etch performed to form the fins 440 may include an anisotropic etch, using etchants in a form of e.g., chemically active ionized gas (i.e., plasma) using e.g., bromine (Br) and chloride (CI) based chemistries. In some embodiments, during the etch to form the fins 440, the IC structure may be heated to elevated temperatures, e.g., to temperatures between about room temperature and 200 degrees Celsius, including all values and ranges therein, to promote that byproducts of the etch are made sufficiently volatile to be removed from the surface.
After forming the fin 440, a dummy gate material may then be provided around gate regions of the fin.
Referring again to
In the example illustrated in
After forming the openings 454, the method 300 may involve additional processes before providing the S/D material in the openings 454. For example, the method 300 may involve recessing a sacrificial material at sidewalls of the openings and providing a spacer material in the recessed areas.
In addition to recessing the material 434 in the openings and providing a spacer material, in some examples, a sacrificial material can be provided at the bottom of the narrower opening.
Referring again to
In one example, after forming the S/D regions, the method can then involve the process of removing the dummy gate material, releasing the nanoribbons, and providing a gate electrode material.
Referring again to
Referring to
The method 300 may then involve forming an opening for a contact structure from the second side 447 of the IC structure 400L.
Referring again to
As can be seen in
After forming the opening 413 for the contact structure and optionally widening the opening 413, the method 300 involves a process 309 of providing a second contact structure over the semiconductor material in the second opening from the second side.
In some examples, the method 300 may involve providing another semiconductor over the S/D region prior to providing the interface material 461 and conductive material 480, such as shown in
The widths of a S/D contact structures may depend on the widths of a corresponding S/D regions. Forming a contact structure that is significantly larger than the corresponding S/D region to which the contact structure is coupled may not result in a larger contact area, and therefore may not have significant benefits, while potentially risking inadvertent conduction between the contact structure and adjacent elements. Conversely, forming a contact structure that is significantly smaller than a corresponding S/D region can result in poor conduction. In the example illustrated in
In the example illustrated in
The IC structure 4000 also includes an interconnect layer 417 over the insulator material 415. One or more interconnect layers may be formed above and below a device region 420 of the IC structure 4000. For example,
A collection of interconnect layers (e.g., the interconnect layer 422 and one or more other interconnect layers above the layer 422, which is not depicted in
The IC structure 400P and all variations of such structures described herein are examples of the IC structures 100 and 200A-200C, described above. Performing the method 300 may result in features in the final IC structures that are characteristic of the use of the method 300. For example, one such feature is illustrated in the IC structure 400P shown in
Providing asymmetric S/D regions can enable increasing the width of one of the S/D regions and/or increasing the channel length without increasing the transistor size. For example, consider an IC structure (e.g., the IC structure 400P) in which one of the S/D regions of a transistor has a narrower width than the other S/D region of the transistor. By reducing the width of one of the S/D regions (e.g., the S/D region 459-2), the width of other features can be increased, such as the channel length 425 and/or the width of the other S/D region (e.g., the S/D region 459-1), where the channel length 425 is a dimension of a channel region of a nanoribbon in a plane parallel with a support over which the IC structure is disposed (e.g., along the y-axis as shown in
IC structures including asymmetric S/D contacts as described herein (e.g., as described with reference to
The IC structures disclosed herein, e.g., the IC structures 100, 200A-200C, and 400P may be included in any suitable electronic component.
Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from the devices (e.g., the transistors) of the device region 1604 through one or more interconnect layers disposed on the device region 1604 (illustrated in
The interconnect structures 1628 may be arranged within the interconnect layers 1606-1610 to route electrical signals according to a wide variety of designs (in particular, the arrangement is not limited to the particular configuration of interconnect structures 1628 depicted in
In some embodiments, the interconnect structures 1628 may include lines 1628a and/or vias 1628b filled with an electrically conductive material such as a metal. The lines 1628a may be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of the support 102 upon which the device region 1604 is formed. For example, the lines 1628a may route electrical signals in a direction in and out of the page from the perspective of
The interconnect layers 1606-1610 may include a dielectric material 1626 disposed between the interconnect structures 1628, as shown in
A first interconnect layer 1606 may be formed above the device region 1604. In some embodiments, the first interconnect layer 1606 may include lines 1628a and/or vias 1628b, as shown. The lines 1628a of the first interconnect layer 1606 may be coupled with contacts (e.g., contacts to the S/D regions 114 of the IC structure 100) of the device region 1604.
A second interconnect layer 1608 may be formed above the first interconnect layer 1606. In some embodiments, the second interconnect layer 1608 may include vias 1628b to couple the lines 1628a of the second interconnect layer 1608 with the lines 1628a of the first interconnect layer 1606. Although the lines 1628a and the vias 1628b are structurally delineated with a line within each interconnect layer (e.g., within the second interconnect layer 1608) for the sake of clarity, the lines 1628a and the vias 1628b may be structurally and/or materially contiguous (e.g., simultaneously filled during a dual-damascene process) in some embodiments.
A third interconnect layer 1610 (and additional interconnect layers, as desired) may be formed in succession on the second interconnect layer 1608 according to similar techniques and configurations described in connection with the second interconnect layer 1608 or the first interconnect layer 1606. In some embodiments, the interconnect layers that are “higher up” in the metallization stack 1619 in the IC device 1600 (i.e., farther away from the device region 1604) may be thicker.
The IC device 1600 may include a solder resist material 1634 (e.g., polyimide or similar material) and one or more conductive contacts 1636 formed on the interconnect layers 1606-1610. In
The package substrate 1652 may be formed of a dielectric material (e.g., a ceramic, a buildup film, an epoxy film having filler particles therein, glass, an organic material, an inorganic material, combinations of organic and inorganic materials, embedded portions formed of different materials, etc.), and may have conductive pathways extending through the dielectric material between the face 1672 and the face 1674, or between different locations on the face 1672, and/or between different locations on the face 1674. These conductive pathways may take the form of any of the interconnects 1628 discussed above with reference to
The package substrate 1652 may include conductive contacts 1663 that are coupled to conductive pathways (not shown) through the package substrate 1652, allowing circuitry within the dies 1656 and/or the interposer 1657 to electrically couple to various ones of the conductive contacts 1664 (or to devices included in the package substrate 1652, not shown).
The IC package 1650 may include an interposer 1657 coupled to the package substrate 1652 via conductive contacts 1661 of the interposer 1657, first-level interconnects 1665, and the conductive contacts 1663 of the package substrate 1652. The first-level interconnects 1665 illustrated in
The IC package 1650 may include one or more dies 1656 coupled to the interposer 1657 via conductive contacts 1654 of the dies 1656, first-level interconnects 1658, and conductive contacts 1660 of the interposer 1657. The conductive contacts 1660 may be coupled to conductive pathways (not shown) through the interposer 1657, allowing circuitry within the dies 1656 to electrically couple to various ones of the conductive contacts 1661 (or to other devices included in the interposer 1657, not shown). The first-level interconnects 1658 illustrated in
In some embodiments, an underfill material 1666 may be disposed between the package substrate 1652 and the interposer 1657 around the first-level interconnects 1665, and a mold compound 1668 may be disposed around the dies 1656 and the interposer 1657 and in contact with the package substrate 1652. In some embodiments, the underfill material 1666 may be the same as the mold compound 1668. Example materials that may be used for the underfill material 1666 and the mold compound 1668 are epoxy mold materials, as suitable. Second-level interconnects 1670 may be coupled to the conductive contacts 1664. The second-level interconnects 1670 illustrated in
The dies 1656 may take the form of any of the embodiments of the die 1502 discussed herein (e.g., may include any of the embodiments of the IC device 1600). In embodiments in which the IC package 1650 includes multiple dies 1656, the IC package 1650 may be referred to as a multi-chip package (MCP). The dies 1656 may include circuitry to perform any desired functionality. For example, or more of the dies 1656 may be logic dies (e.g., silicon-based dies), and one or more of the dies 1656 may be memory dies (e.g., high-bandwidth memory).
Although the IC package 1650 illustrated in
In some embodiments, the circuit board 1702 may be a PCB including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 1702. In other embodiments, the circuit board 1702 may be a non-PCB substrate.
The IC device assembly 1700 illustrated in
The package-on-interposer structure 1736 may include an IC package 1720 coupled to a package interposer 1704 by coupling components 1718. The coupling components 1718 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 1716. Although a single IC package 1720 is shown in
In some embodiments, the package interposer 1704 may be formed as a PCB, including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. In some embodiments, the package interposer 1704 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, an epoxy resin with inorganic fillers, a ceramic material, or a polymer material such as polyimide. In some embodiments, the package interposer 1704 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The package interposer 1704 may include metal lines 1710 and vias 1708, including but not limited to through-silicon vias (TSVs) 1706. The package interposer 1704 may further include embedded devices 1714, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as RF devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the package interposer 1704. The package-on-interposer structure 1736 may take the form of any of the package-on-interposer structures known in the art.
The IC device assembly 1700 may include an IC package 1724 coupled to the first face 1740 of the circuit board 1702 by coupling components 1722. The coupling components 1722 may take the form of any of the embodiments discussed above with reference to the coupling components 1716, and the IC package 1724 may take the form of any of the embodiments discussed above with reference to the IC package 1720.
The IC device assembly 1700 illustrated in
Additionally, in various embodiments, the electrical device 1800 may not include one or more of the components illustrated in
The electrical device 1800 may include a processing device 1802 (e.g., one or more processing devices). As used herein, the term “processing device” or “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processing device 1802 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices. The electrical device 1800 may include a memory 1804, which may itself include one or more memory devices such as volatile memory (e.g., dynamic RAM (DRAM)), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive. In some embodiments, the memory 1804 may include memory that shares a die with the processing device 1802. This memory may be used as cache memory and may include embedded dynamic RAM (eDRAM) or spin transfer torque magnetic RAM (STT-MRAM).
In some embodiments, the electrical device 1800 may include a communication chip 1812 (e.g., one or more communication chips). For example, the communication chip 1812 may be configured for managing wireless communications for the transfer of data to and from the electrical device 1800. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
The communication chip 1812 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultra mobile broadband (UMB) project (also referred to as “3GPP2”), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 802.16 standards. The communication chip 1812 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 1812 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 1812 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication chip 1812 may operate in accordance with other wireless protocols in other embodiments. The electrical device 1800 may include an antenna 1822 to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).
In some embodiments, the communication chip 1812 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip 1812 may include multiple communication chips. For instance, a first communication chip 1812 may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication chip 1812 may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication chip 1812 may be dedicated to wireless communications, and a second communication chip 1812 may be dedicated to wired communications.
The electrical device 1800 may include battery/power circuitry 1814. The battery/power circuitry 1814 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the electrical device 1800 to an energy source separate from the electrical device 1800 (e.g., AC line power).
The electrical device 1800 may include a display device 1806 (or corresponding interface circuitry, as discussed above). The display device 1806 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.
The electrical device 1800 may include an audio output device 1808 (or corresponding interface circuitry, as discussed above). The audio output device 1808 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds.
The electrical device 1800 may include an audio input device 1824 (or corresponding interface circuitry, as discussed above). The audio input device 1824 may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).
The electrical device 1800 may include a GPS device 1818 (or corresponding interface circuitry, as discussed above). The GPS device 1818 may be in communication with a satellite-based system and may receive a location of the electrical device 1800, as known in the art.
The electrical device 1800 may include an other output device 1810 (or corresponding interface circuitry, as discussed above). Examples of the other output device 1810 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.
The electrical device 1800 may include an other input device 1820 (or corresponding interface circuitry, as discussed above). Examples of the other input device 1820 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.
The electrical device 1800 may have any desired form factor, such as a handheld or mobile electrical device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra mobile personal computer, etc.), a desktop electrical device, a server device or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable electrical device. In some embodiments, the electrical device 1800 may be any other electronic device that processes data.
The following paragraphs provide various examples of the embodiments disclosed herein.
Example 1 provides an IC structure including a first region and a second region of a transistor, where one of the first region and the second region is a source region of the transistor, and another of the first region and the second region is a drain region of the transistor. The IC structure includes a first contact structure (e.g., drain contact structure) coupled to the first region (e.g., drain region) from a first side (e.g., front side) of the IC structure, and a second contact structure (e.g., source contact structure) coupled to the second region (e.g., source region) from a second side (e.g., back side) of the IC structure, where the first region has a first width (e.g., width of the drain region) and the second region has a second width (e.g., width of the source region) that is smaller than the first width.
Example 2 provides an IC structure in accordance with example 1, where the second region is the source region of the transistor.
Example 3 provides an IC structure in accordance with examples 1 or 2, where the second contact structure has a third width that is larger than the second width.
Example 4 provides an IC structure in accordance with any one of examples 1-3, where the second contact structure has a third width, and the first contact structure has a fourth width that is larger than the third width.
Example 5 provides an IC structure in accordance with any one of examples 1-4 where the second contact structure includes a conductive material, the second region includes a first semiconductor material, and the IC structure further includes a second semiconductor material (e.g., grown with a low temperature epitaxial deposition technique) between the conductive material and the first semiconductor material.
Example 6 provides an IC structure in accordance with example 5, further including an interface material between the second semiconductor material and the conductive material.
Example 7 provides an IC structure in accordance with examples 5 or 6, where the second semiconductor material has at least one different material property than the first semiconductor material, including one or more of: a different material composition and a different crystal direction.
Example 8 provides an IC structure in accordance with any one of examples 1-7 where the first contact structure includes a liner of a liner material on sidewalls of the first contact structure, and the second contact structure lacks a liner of the liner material on sidewalls of the second contact structure.
Example 9 provides an IC structure in accordance with any one of examples 1-8, where the second width is 5-60% smaller than the first width.
Example 10 provides an IC structure including a transistor over a support, the transistor including a channel region, a source region, and a drain region, a source contact structure coupled with the source region, and a drain contact structure coupled with the drain region, where the drain region has a first width in a plane substantially parallel to the support, the source region has a second width in the plane, and wherein the first width is different than the second width.
Example 11 provides an IC structure in accordance with example 10, where the source contact structure has a third width that is larger than the second width.
Example 12 provides an IC structure of claim 10 or 11, where the source contact structure has a third width, and the drain contact structure has a fourth width that is smaller than the third width.
Example 13 provides an IC structure in accordance with any one of examples 10-12, where the source contact structure includes a conductive material, the source region includes a first semiconductor material, and the IC structure includes a second semiconductor material between the conductive material and the first semiconductor material, wherein the second semiconductor material is in contact with the first semiconductor material.
Example 14 provides an IC structure in accordance with examples 13, further including an interface material between the second semiconductor material and the conductive material, where the interface material is in contact with the second semiconductor material.
Example 15 provides an IC structure in accordance with examples 13 or 14, where the second semiconductor material has at least one different material property than the first semiconductor material.
Example 16 provides an IC structure in accordance with any one of examples 10-15, further including a liner on sidewalls of the drain contact structure, where a liner is absent from sidewalls of the source contact structure.
Example 17 provides an IC structure of any one of examples 1-16, where the second width is 25-35% smaller than the first width.
Example 18 provides an IC structure according to any one of examples 1-17, where the IC structure includes or is a part of a central processing unit.
Example 19 provides an IC structure according to any one of examples 1-18, where the IC structure includes or is a part of a memory device.
Example 20 provides an IC structure according to any one of examples 1-19, where the IC structure includes or is a part of a logic circuit.
Example 21 provides an IC structure or IC device according to any one of examples 1-20, where the IC structure or IC device includes or is a part of input/output circuitry.
Example 22 provides an IC structure or IC device according to any one of examples 1-21, where the IC structure or IC device includes or is a part of a field programmable gate array transceiver.
Example 23 provides an IC structure or IC device according to any one of examples 1-22, where the IC structure or IC device includes or is a part of a field programmable gate array logic.
Example 24 provides an IC structure or IC device according to any one of examples 1-23, where the IC structure or IC device includes or is a part of a power delivery circuitry.
Example 25 provides an IC package that includes an IC die including an IC structure or IC device according to any one of examples 1-24; and a further IC component, coupled to the IC die.
Example 26 provides an IC package according to example 25 where the further IC component includes a package substrate.
Example 27 provides an IC package according to example 25, where the further IC component includes an interposer.
Example 28 provides an IC package according to example 25, where the further IC component includes a further IC die.
Example 29 provides a computing device that includes a carrier substrate and an IC structure or IC device coupled to the carrier substrate, where the IC structure or device is an IC structure or device according to any one of examples 1-24, or the IC structure or device is included in the IC package according to any one of examples 25-28.
Example 30 provides a computing device according to example 29, where the computing device is a wearable or handheld computing device.
Example 31 provides a computing device according to examples 29 or 30, where the computing device further includes one or more communication chips.
Example 32 provides a computing device according to any one of examples 29-31, where the computing device further includes an antenna.
Example 33 provides a computing device according to any one of examples 29-32, where the carrier substrate is a motherboard.
Example 34 provides a method of fabricating an IC structure, the method including providing a stack of nanoribbons over a support, forming a first opening in the stack of nanoribbons, wherein the first opening has a first width in a plane substantially parallel to the support, forming a second opening in the stack of nanoribbons, wherein the second opening has a second width in the plane, and wherein the second width is smaller than the first width, providing a semiconductor material in the first opening and the second opening, providing a first contact structure to couple with the semiconductor material in the first opening, and providing a second contact structure to couple with the semiconductor material in the second opening, wherein one of the first contact structure and the second contact structure is a source contact structure, and another of the first contract structure and the second contact structure is a drain contact structure.
Example 35 provides a method according to example 34, where the first opening and the second opening are formed at a first side of the IC structure, and providing the second contact structure includes flipping over the IC structure to expose a second side of the IC structure, forming a third opening from the second side to expose the semiconductor material in the second opening, and filling the third opening with a conductive material.
Example 36 provides a method according to examples 34 or 35, wherein prior to filling the third opening with a conductive material, the method includes widening the third opening.
Example 37 provides a method according to any one of examples 34-36, where the IC structure is an IC structure according to any one of the preceding examples.
The above description of illustrated implementations of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific implementations of, and examples for, the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize. These modifications may be made to the disclosure in light of the above detailed description.
