INTEGRATED CIRCUIT TO ENCODE DATA

Abstract

An integrated circuit configurable to encode data according to a number of coding schemes and to generate cyclic redundancy codes, includes a number of identical specific hardware cells, and each cell includes four outputs for binary signals, four inputs for binary signals, a buffer to delay by one clock period a binary value received on an input and to output a one-clock period delayed binary value, binary adders to perform XOR operations, configurable multiplexers connecting the outputs, the inputs, the buffer and the adders to each other according to several configurable paths, and controllable switch matrices external to each cell and able to electrically connect and disconnect inputs to or from outputs of another cell.

Description

FIELD OF THE INVENTION

The present invention relates to integrated circuit to encode data.

BACKGROUND OF THE INVENTION

There exist integrated configurable circuits to encode data according to any one of a plurality of coding schemes and/or to generate cycle redundancy codes. Typically, the code scheme comprises block, convolutional and turbo codes.

Ideally such a circuit should be very flexible, that is able to be configured to execute many different coding schemes and/or to generate many different cyclic redundancy codes. This circuit should also excel in the efficient execution (power, chip area, flexibility) of these schemes. However, flexibility and execution efficiency are antagonized. For example, more flexible is the circuit, slower is the execution speed. In contrast, faster is the circuit, lesser is the flexibility. Attempts to build circuits which are pretty flexible while remaining pretty fast have been disclosed. For example, U.S. Pat. No. 6,807,155 in the name of Subramanian discloses to rank functions which are common to different telecommunication processing standards according to their computational intensity. Then the design of the telecommunication processing is based on the function ranking to speed up the execution while remaining pretty flexible.

SUMMARY OF THE INVENTION

Accordingly, it is an object of the invention to provide an integrated circuit which is more flexible than dedicated hardware integrated processors while being faster than non-dedicated hardware processors and less power-hungry.

The invention provides an integrated circuit configurable to encode data according to any one of the coding schemes chosen in a predetermined plurality of coding schemes and to generate cyclic redundancy codes, said predetermined plurality of coding schemes comprising block, convolutional and turbo codes, wherein the integrated circuit comprises:

a) a plurality of specific hardware cells, each cell comprising:

• • outputs S_ij, FO_ij, BO_ij and TO_ij for binary signals,
  • inputs E_ij, BI_ij, FI_ij and TI_ij for binary signals,
  • a buffer to delay by one clock period a binary value received on input E_ij and to output a one-clock period delayed binary value E*,
  • binary adders to perform XOR operations,
  • configurable multiplexers BM, FM, MM and TM connecting the outputs, the inputs, the buffer and the adders to each other according to several configurable paths, the characteristic equations of the cell being:

TO _ij =S _ij =Ctm.TI _ij +!Ctm.OutputMux4

OutputMux4=Cmm0.Cmm1.E*+!Cmm0.Cmm1.(E*XOR BI_ij)+Cmm0.!Cmm1.E+!Cmm0.!Cmm1.(E_ij XOR FI_ij)

BO _ij =Cbm.(S_ij XOR BI₄)+!Cbm.BI_ij

or

BO _ij =Cbm0.Cbm1.(S_ij XOR BI_ij)+!Cbm0.Cbm1.BI_ij+!Cbm0.Cbm1.S_ij

FO _ij =Cfm.(S_ij XOR FI_ij)+!Cfm.FI_ij

• • • where:
    • S_ij, FO_ij, BO_ij and TO_ij are the binary signals output on outputs S_ij, FO_ij, BO_ij and TO_ij, respectively,
    • E_ij, BI_ij, FI_ij and TI_ij are the binary signals received on inputs E_ij, BI_ij, FI_ij and TI_ij, respectively,
    • “!” is the NOT operation,
    • “*” is the output of the buffer,
    • “XOR” is the XOR operation,
    • “+” is the OR operation,
    • “.” is the AND operation,
    • Cbm, Cbm0, Cbm1, Cfm, Cmm0, Cmm1 and Ctm are respective binary values that represent the configuration of each multiplexer,

b) controllable switch matrices external to each cell and able:

• • to electrically connect and, alternatively, to electrically disconnect input E_ij to/from at least the output S_ij of another cell and to electrically connect and, alternately, to electrically disconnect input E_ij to/from an external binary data source,
  • to electrically connect and, alternately, to electrically disconnect at least input FI_ij to/from at least the output FO_ij of another cell,
  • to connect and, alternately, to disconnect input BI_ij to/from at least the output BO_ij of another cell.

The invention also provides an integrated circuit configurable to encode data according to any one of the coding schemes chosen in a predetermined plurality of coding schemes and to generate cyclic redundancy codes, said predetermined plurality of coding schemes comprising block and convolutional codes, wherein the integrated circuit comprises:

a) a plurality of specific hardware cells, each cell comprising:

• • outputs S_ij, FO_ij, and BO_ij for binary signals,
  • inputs E_ij, BI_ij, and FI_ij for binary signals,
  • a buffer to delay by one clock period a binary value received on input E_ij and to output a one-clock period delayed binary value E*,
  • binary adders to perform XOR operations,
  • configurable multiplexers connecting the outputs, the inputs, the buffer and the adders to each other according to several configurable paths, the characteristic equations of the cell being:

S_ij=OutputMux4

OutputMux4=Cmm0.Cmm1.E*+!Cmm0.Cmm1.(E*XOR+BI_ij)+Cmm0.!Cmm1.E+!Cmm0.!Cmm1.(E_ij XOR FI_ij)

BO _ij =Cbm.(S_ij XOR BI_ij)+!Cbm.BI_ij

or

BO _ij =Cbm0.Cbm1.(S_ij XOR BI_ij)+!Cbm0.Cbm1.BI_ij+!Cbm0.Cbm1.S_ij

FO _ij =Cfm.(S_ij XOR FI_ij)+!Cfm.FI_ij

• • • where:
    • S_ij, FO_ij and BO_ij are the binary signals output on outputs S_ij, FO_ij and BO_ij, respectively,
    • E_ij, BI_ij and FI_ij are the binary signals received on inputs E_ij, BI_ij and FI_ij, respectively,
    • “!” is the NOT operation,
    • “*” is the output of the buffer,
    • “XOR” is the XOR operation,
    • “+” is the OR operation,
    • “.” is the AND operation,
    • Cbm, Cbm0, Cbm1, Cfm, Cmm0, and Cmm1 are respective binary values that represent the configuration of each multiplexer,

b) controllable switch matrices external to each cell and able:

• • to electrically connect and, alternatively, to electrically disconnect input E_ij to/from at least the output S_ij of another cell and to electrically connect and, alternately, to electrically disconnect input E_ij to/from an external binary data source,
  • to electrically connect and, alternately, to electrically disconnect at least input FI_ij to/from at least the output FO_ij of another cell,
  • to connect and, alternately, to disconnect input BI_ij to/from at least the output BO_ij of another cell.

The above integrated circuits are more flexible than any dedicated hardware processor because cells and connections between cells can be configured to implement a great number of coding schemes and CRC (Cyclic Redundancy Code) scheme. The above integrated circuit is also faster than any general purpose hardware processor like DSP (Digital Signal Processor), because it comprises specific hardware cells able to execute operations as fast as dedicated hardware processors.

Finally, because specific cells are identical to each other, the implementation on the die of a chip of such an integrated circuit can be done with a great efficiency. Furthermore, the configuration of these cells as well as the configuration of the connections between cells is also made easier.

The embodiments of the above integrated circuits may comprise one or several of the following features:

• • the integrated circuit comprises a plurality of clusters CL_j, each cluster CL_j comprising:
    • inputs E_j, FI_j and BI_j,
    • outputs S_j, BO_j and FO_j,
    • a succession of at least two cells C_ij successively electrically connected to each other, the first cell of the succession having its inputs E_ij and F_ij and its output BO_ij directly connected to inputs E_j, FI_j and BO_j, respectively,
    • the last cell of the succession having its input BI_ij and its outputs S_ij and FO_ij directly connected to input BI_ij, output S_j and output FO_j, respectively of another cell outside this cluster, and
    • any cell other than the last cell having its input BI_ij and its outputs S_ij and FO_ij connected, without any configuration possibility, to output BO_ij and inputs E_ij and FI_ij of the following cell of the succession, respectively, and
  • the switch matrix is only able to configure the electrical connections between cluster inputs and outputs without being able to configure the electrical connections between cells within a cluster,
  • the outputs S_j, FO_j and the input BI_j of at least one cluster are connected to inputs E_j, FI_j and output BO_j of another cluster without configuration possibility, respectively,
  • the integrated circuit comprises between five to ten clusters and each cluster is composed of five cells,
  • each cluster has at least one cell having the following characteristic equation:

BO _ij =Cbm0.Cbm1.(S_ij XOR BI_ij)+!Cbm0.Cbm1.BI_ij+!Cbm0.Cbm1.S_ij

• • the inputs TI_ij of the succession of cells of a cluster, are directly connected to respective outputs TO_ij of the succession of cells of another cluster without any configuration possibility.

The above embodiments of the integrated circuit present the following advantages:

• • using cluster reduces the size of the switch matrices,
  • connecting a cluster to another cluster without configuration possibility also reduces the size of the switch matrices,
  • using between five to ten clusters of five cells constitutes an optimum implementation of the integrated circuit to achieve the greatest possible flexibility while still maintaining the number of cells as small as possible,
  • having only one cell in each cluster that corresponds to the characteristic equation

BO _ij =Cbm0.Cbm1.(S_ij XOR BI_ij)+!Cbm0.Cbm1.BI_ij+!Cbm0.Cbm1.S_ij

• •  is enough to configure the integrated circuit to generate CRC codes,
  • connecting outputs TO_ij to inputs TI_ij+2 without any configuration possibility simplifies the connections between adjacent clusters while still maintaining a high degree of flexibility.

These and other aspects of the invention will be apparent from the following description, drawings and claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1 and 2 are schematic diagram of a first cell and a second cell used in the implementation of an integrated circuit,

FIG. 3 is a schematic diagram of a cluster built from cells of FIGS. 1 and 2,

FIG. 4 is an example schematic diagram of an integrated circuit built from the cluster of FIG. 3,

FIG. 4A is a schematic illustration of a switch matrix implemented within the circuit of FIG. 4,

FIG. 5 is an illustration of a first configuration of the circuit of FIG. 4 to generate a CRC code,

FIG. 6 is a schematic diagram of a convolutional encoder,

FIG. 7 is a schematic diagram of the configuration of the integrated circuit of FIG. 4 to implement the convolutional encoder of FIG. 6,

FIG. 8 is a schematic diagram of another conventional encoder,

FIG. 9 is a schematic diagram of the configuration of the integrated circuit of FIG. 4 to implement the convolutional encoder of FIG. 8,

FIG. 10 is a schematic diagram of another convolutional encoder with inter-branch connections,

FIG. 11 is a schematic diagram of the configuration of the integrated circuit of FIG. 4 to implement the convolutional encoder of FIG. 10,

FIG. 12A is a schematic diagram of a turbo coder,

FIG. 12B is a schematic diagram of the configuration of the integrated circuit of FIG. 4 to implement the convolutional turbo coder,

FIG. 13A is a schematic diagram of a randomization or scrambling circuit, and

FIG. 13B is a schematic diagram of the integrated circuit of FIG. 4 configured to implement the randomization or scrambling circuit of FIG. 13A.

DETAILED DESCRIPTION

FIG. 1 shows a hardware specific cell C_ij that can be used to realize an integrated circuit which can be configured to perform the following operations:

• • CRC generation that complies with anyone of the following standards: GSM (Global System for Mobile Communication), UMTS (Universal Mobile Telecommunication System), DMB (Digital Multimedia Broadcasting), DAB (Digital Audio Broadcasting), CDMA 2000 (Code Division Multiple Access 2000), WPAN (Wireless Personal Area Network), WLAN (Wireless Local Area Network), WMAN (Wireless Metropolitan Area Network),
  • Convolutional encoding operations that comply with any one of the following standards: GSM, UMTS, DMB, CDMA 2000, iDEN (Integrated Digital Enhanced Network), PHS (Personal Handy-phone System), PDC (Personal Digital Cellular), WPAN, WLAN, WMAN, DVB (Digital Video Broadcasting), and
  • Turbo encoding operations that comply with any one of the following standards: UMTS, SDMB (Satellite Digital Multimedia Broadcasting), CDMA 2000, WMAN, and
  • Randomization and scrambling operations that comply with any one of the following standards: UMTS, CDMA 2000, WMAN, WLAN, DMB, DAB, DVB.

The integrated circuit can also run chips spreading process.

Cell C_ij includes:

• • four binary inputs E_ij, BI_ij and TI_ij,
  • four binary outputs S_ij, FO_ij, BO_ij, TO_ij,
  • one buffer BU_i directly connected to input E_ij and that outputs a value E*,
  • four adders A_1i, A_2i, A_3i and A_4i, and
  • four multiplexers MM, TM, BM and FM.

Buffer BU_i is able to delay the binary value received on input E_ij by one clock period to output a binary value E*. The output of buffer BU_i is directly connected to a first input of multiplexer MM and to a first input of adder A_1i. A second input of adder A_1i is directly connected to input BI_ij. The output of adder A_1i is directly connected to a second input of multiplexer MM. Adder A_1i provides on its output the result of an XOR operation between its inputs.

Input E_ij is directly connected to a third input of multiplexer MM and to a first input of adder A_3i. A second input of adder A₃₁ is directly connected to input FI_ij. The output of adder A_3i is directly connected to a fourth input of multiplexer MM.

Multiplexer MM has an output connected to a first input of multiplexer TM. Multiplexer MM is able to directly connect any one of its inputs to the output depending on a configuration bit value stored in a cell configuration bit register. Thus, once a selected input is connected to the output, the multiplexer behave like if the selected input was directly wired to the output. This is also true for any of the multiplexers used in cell E_ij.

A second input of multiplexer TM is directly connected to input T_ij. The output of multiplexer TM is directly connected to output S_ij.

The output of multiplexer BM is directly connected to output BO_ij. A first and a second input of multiplexer BM are directly connected to input BI_ij and an output of adder A_2i, respectively.

Adder A_2i has a first and a second input directly connected to the output of multiplexer TM and to input BI_ij, respectively.

An output of multiplexer FM is directly connected to output FO_ij. Multiplexer FM has a first and a second input directly connected to input FI_ij and to an output of adder A_4i respectively.

Adder A_4i has a first and second input directly connected to the output of multiplexer TM and to input FI_ij, respectively.

Output TO_ij is directly connected at the output of multiplexer TM.

Accordingly, cell C_ij has the following characteristic equations:

TO _ij =S _ij =Ctm.TI _ij +!Ctm.OutputMux4   (1)

OutputMux4=Cmm0.Cmm1.E*+!Cmm0.Cmm1.(E.*XOR BI_ij)+Cmm0.!Cmm1.E_ij+!Cmm0.!Cmm1.(E_{ij XOR FIij})   (2)

BO _ij =Cbm.(S_ij XOR BI_ij)+!Cbm.BI_ij   (3)

FO _ij =Cfm.(S_ij XOR FI_ij)+!Cfm.FI_ij   (4)

where:

• • symbol “!” corresponds to the NOT operation
  • symbol “*” refers to the output of buffer BU_i,
  • symbol “XOR” corresponds to the XOR operation,
  • symbol “+” corresponds to the OR operation,
  • symbol “.” corresponds to the AND operation,
  • Cmm0 and Cmm1 are binary values that depend on the configuration of multiplexer MM,
  • Ctm, Cbm and Cfm are binary values that depend on the configuration of multiplexer TM, BM and FM, respectively.

More precisely, the value of binary values Cmm0 and Cmm1 are defined by the following table where the first column recites which input is directly connected to the output of multiplexer MM and the second and third columns recite the values of Cmm0 and Cmm1, respectively.

	TABLE 1
	Input	Cmm0	Cmm1
	E*	1	1
	2nd Input	1	0
	3rd Input	0	1
	4th Input	0	0

Ctm is equal to “1” when multiplexer TM is configured to directly connect input TI_ij to output S_ij and equal to “0” when multiplexer TM is configured to directly connect the output of multiplexer MM to output S_ij.

Cbm is equal to “1” when multiplexer BM is configured to directly connect the output of adder A_2i to output BO_ij. Otherwise, Cbm is equal to “0” when multiplexer BM is configured to directly connect input BI_ij to output BO_ij.

Cfm is equal to “1” when multiplexer FM is configured to directly connect the output of adder A_4i to output FO_ij. Otherwise, Cfm is equal to “0” when multiplexer FM is configured to directly connect input to output FO_ij.

FIG. 2 shows a specific hardware cell Ce_i,j which is identical to cell C_i,j except that multiplexer BM has a third input directly connected to output TO_ij and S_ij. Accordingly, the characteristic equations of cell Ce_ij are identical to equations (1) to (4) except that equation (3) is replaced by the following characteristic equation:

BO _ij =Cbm0.Cbm1.(S_ij XOR BI_ij)+!Cbm0.Cbm1.BI_ij+!Cbm0.Cbm1.S_ij   (5)

where Cbm0 and Cbm1 are binary values which depend on the configuration of multiplexer BM.

More precisely, the values of Cbm0 and Cbm1 are defined according to the following table where the first column recites which input of multiplexer BM is directly connected to output BO_ij, and the second and third columns recite the corresponding value of Cbm0 and Cbm1.

	TABLE 2
	Cbm0	Cbm1
	1st input	1	1
	BIij	1	0
	Sij	0	1

FIG. 3 shows a cluster CL_j which is formed by the connection in series of five cells C_0,j, C_1,j, C_2,j, C_3,j and Ce_4,j. In the following specification, the first index “i” of the cell name C_i,j indicates the position of the cell within a cluster and index “j” indicates the cluster in which is situated the cell C_ij or Ce_ij.

Cluster CL_j has four inputs E_j, FI_j, BI_j and AI_j as well as three outputs S_j, FO_j, and BO_j.

Inputs E_j and FI_j and output BO_j are directly connected to input E_0j, FI_0j and output BO_0j of cell C_0,j, respectively. Outputs S_j, and input BI_j are directly connected to outputs S_4j, and input BI_4j of cell Ce_4,j, respectively.

Each cluster CL_J includes an additional adder A_5J which has a first and a second inputs directly connected to output FO_4,j and input AI_J, respectively. The output of adder A_5J is directly connected to output FO_J of cluster CL_J.

Within a cluster, except for the last cell Ce_4,j, each cell CI_ij is directly connected to the following cell in the following way:

• • outputs S_ij and FO_ij are directly connected to inputs E_i+1,j and FI_i+1,j of the following cell C_i+1,j, and
  • input BI_ij is directly connected to output BO_i+1,j of the following cell C_i+1,j.

The above connections between cells within a cluster are etched within the die of the integrated circuit. Thus, they cannot be modified or configured latter on.

Cluster CL_j has also five inputs TI_i,j which are directly connected to the respective corresponding input TI_i,j of the corresponding cells. Cluster CL_j has also five outputs TO_i,j which are directly connected to the respective corresponding output TO_i,j of the corresponding cell.

FIG. 4 shows some parts of an integrated circuit 2 which is etched on the die of a chip.

Circuit 2 includes nine clusters CL₀ to CL₈ which are arranged on the surface of the die to form two columns and five rows. More precisely, clusters CL₀, CL₂, CL₄, CL₆ and CL₅ form the first column whereas clusters CL₁, CL₃, CL₅ and CL₇ form the second column.

The inputs and outputs of each cluster are connected to each other through configurable connections. The connections between clusters can be configured through the use of switch matrices. For example, circuit 2 includes five switch matrices.

A first switch matrix SE can electrically connect and, alternately, disconnect input E_j to/from any output S_k where “k” is different from “j” or, alternately, to an external binary source ExtE_i.

A second switch matrix FOFI can electrically connect and, alternatively, disconnect output FO_j to/from any input FI_k, where “k” is different from “j”.

A third matrix BIBO can electrically connect and, alternatively disconnect any input BI_j to/from any output BO_k, where “k” is different from “j”.

A fourth switch matrix BOAI can electrically connect and, alternately, disconnect input AI_j to any outputs BO_k where “k” is different from “j”.

In circuit 2, when an input of a cluster is not connected to an output of another cluster, this input is electrically connected to ground that corresponds to a binary value equal to “0”.

FIG. 4A shows switch matrix FOFI. Matrix FOFI is built from a great number of individual switches FOFI_nm. Each switch FOFI_nm can electrically connect respective output FO_n to a respective input FI_m and, alternatively, electrically disconnect this output FO_n from input FI_m. The matrix can be configured to make a one-to-one connection between an input and output or a one-to-many connections between output FO_n and inputs FI. Typically, the switch matrix is realized using multiplexers.

In FIG. 4A, a vertical line is only electrically connected to a horizontal line if the corresponding switch FOFI_nm is conducting.

Matrices SE, BIBO and BOAI are built in a similar way as the one illustrated in FIG. 4A.

For simplicity, in circuit 2, connections between two clusters on the same line are not configurable. For example, these connections are not implemented through a switch matrix. For example, outputs S₀, FO₀ and input BI₀ are directly connected to inputs E₁, FI₁ and output BO₁, without any configuration possibility.

For simplicity, only some switches of the switch matrices have been illustrated in FIG. 4.

More precisely, FIG. 4 shows four switches SE₁₂, SE₃₄, SE₅₆, SE₇₈ connected between output S_j of the last cluster of the previous row and input E_j+1 of the first cluster of the following row.

FIG. 4 shows also four switches BIBO₁₂, BIBO₃₄, BIBO₅₆, BIBO₇₈ connected between input BI_j of the last cluster of the previous row and input BO_j+1 of the first cluster of the following row.

Finally, FIG. 4 shows four switches FOFI₁₂, FOFI₃₄, FOFI₅₆, and FOFI₇₈ connected between the output of adder A_5j and input FI_j+1.

Switches of BOAI matrix have not being shown.

In circuit 2, outputs TO_ij of cluster CL_j are only connected to corresponding respective inputs TI_i,j+2 of the following cluster CL_j+2 in the same column.

Circuit 2 has also nine cluster configuration registers RC_j. Each cluster configuration register RC_j contains the value of Ctm, Cmm0, Cmm1, Cbm and Cfm that determine the configuration of each cell C_i,j of cluster CL_j as well as the value of Ctm, Cmm0, Cmm1, Cbm0, Cbm1 and Cfm that determine the configuration of cell Ce_i,j of cluster CL_j. Thus, the configuration of each cell of each cluster can be amended by modifying the values stored in each one of these registers CR_j.

Circuit 2 has also four switch matrix configuration registers SR₁ to SR₄. These registers determine the configuration of the connections between the different clusters CL_j of circuit 2. More precisely, each register SR contains binary information that determines if a given switch of the switch matrix is open or closed. Accordingly, those registers are used to configure the connections between clusters.

Circuit 2 has also an output stage 4 which is connected to every outputs of every cluster. Output stage 4 is designed to format the output of clusters CL_j in order to transmit the result of the computation of circuit 2 on a eight-bit width parallel bus 6. For example, output stage 4 includes a multiplexer 10 that is connected to every outputs of each cluster. Nine outputs of multiplexer 10 are connected to respective inputs of a packager 12. Packager 12 is able to output the received bits one after the other in a FIFO (First In First Out) buffer 14 which can send the received data on bus 6.

FIG. 5 shows the configuration of circuit 2 to compute a CRC code as specified in standard WLAN or standard 802.11. More precisely, the configuration shown in FIG. 5 implements the generation and the check sequence of a CCITT CRC-16 bit generated with the following polynomial: x¹⁶+x¹²+x⁵+1.

As show in this configuration example, only four cells C_1,0 to Ce_4,0 of cluster CL₀ are used. In order to bypass cell C_0,0, multiplexers MM and TM are configured to directly connect input E_0,0 to output S_0,0. Thus, any cell within a cluster can be bypassed.

To implement the terms x¹⁶+x¹²+x⁵+1 of the above polynomial, the multiplexers MM and TM of cells C_1,0, C_1,1, C_3,2 and Ce_4,3 are configured to directly connect the output of adder A_1i to output S₃. The other cells which are not bypassed are only configured to implement a delay of one clock period.

In this configuration, the clusters CL₀ to CL₃ are series connected. More precisely, output S_j is connected to input E_j+1 of the following cluster and input BI_j is directly connected to output BO_j+1 of the following cluster CL_j+1.

In this embodiment, only four clusters are used.

In this configuration the data are input through input E₀ and the CRC code is read from output S₃.

Note that cell Ce_4,3 is configured so that output S₃ is directly connected to output BO₄₃ through multiplexer BM. Thus, multiplexer BM provides the source of the feedback branch.

FIG. 6 shows a convolutional encoder with a rate of ½ which complies with UMTS standards. Cells D represent delay line of one clock period. This convolutional encoder is a well-known encoder that will not be described in further details. The results of the convolutional encoder are output through pins G₀ and G₁.

FIG. 7 shows the configuration of circuit 2 to implement the convolutional encoder of FIG. 6. Only four clusters CL₀ to CL₃ are used. Outputs S₀ and FO₀ are directly connected to inputs E₁ and FI₁. Similarly, outputs S₂ and FO₂ are directly connected to inputs E₃ and FI₃, respectively.

Inputs E₀ and E₂ receive the binary stream to be encoded.

Outputs FO₁ and FO₃ correspond to outputs G₀ and G₁ of FIG. 6.

Outputs S₁ and S₃ are not used. In the configuration of FIG. 7, cell Ce_4,0 and Ce_4,2 are bypassed. Switches SE₀₁ and SE₂₃ are conducting. Switches FOFI₀₁ and FOFI₂₃ are also conducting. Every other switch of the matrices is non-conducting. Adders A_5j are not used.

FIG. 8 shows a convolutional encoder having a rate of ⅙. This convolutional encoder is defined in the standards concerning CDMA 2000. It will thus not be described in further details. Cells Pⁱ are delay lines of one clock period. The result of the convolution is output through outputs c(6k), c(6k+1), c(6k+2), c(6k+3), c(6k+4) and c(6k+5).

FIG. 9 illustrates the configuration of circuit 2 to implement the convolutional encoder of FIG. 8. This implementation only needs six clusters CL₀ to CL₅.

In this configuration, cells Ce_4,0, Ce_4,2 and Ce_4,4 are bypassed.

Inputs E₀, E₂ and E₄ receive the same binary input stream.

Outputs FO₁, FO₃ and FO₅ correspond to outputs c(6k+1), c(6k+3) and c(6k+5) of the convolutional encoder of FIG. 8, respectively.

Outputs BO₀, BO₂ and BO₄ correspond to outputs c(6k), c(6k+2), c(6k+4) of the convolutional encoder of FIG. 8, respectively.

Outputs S₁, S₃ and S₅ are not used.

Inputs FI₀, FI₂ and FI₄ and inputs BI₁, BI₃ and BI₅ are connected to ground.

In this configuration, it should be noted that outputs c(6k), c(6k+2), c(6k+4) are computed by using feedback branches of the clusters whereas output c(6k+1), c(6k+3) and c(6k+5) are computed by using forward branches of the same clusters. Thus, only six clusters are needed instead of twelve clusters if only forward branches were used.

FIG. 10 shows a convolutional encoder with interbranch connections. The illustrated convolutional encoder is described in more details in the standard WLAN 802.11g or DSSS 22 and 33 Mbit/s. Cells with symbol Z⁻¹ are delay lines of one clock period. This encoder receives input signal b_2j and b_2j+1 and outputs three binary streams y₀, y₁ and y₂.

An interbranch connection is a connection through a adder between two different forward branches, for example.

FIG. 11 shows the configuration of circuit 2 to implement the convolutional encoder of FIG. 10. In this configuration, only clusters CL₁, CL₃, CL₅, CL₇ and CL₈ are used. The cells of clusters CL₀, CL₂, CL₄ and CL₈ are bypassed.

In this embodiment, the switch matrix BOAI is used to connect output BO₁, to input AI₃, output BO₃ to input AI₅ and output BO₈ to input AI₇.

Inputs E₃, E₈ receive binary stream b_2j. Inputs E₁, E₅, and E₇ receive binary stream b_2j+1.

Binary stream y₀, y₁ and y₂ correspond to outputs FO₃, FO₇ and FO₅, respectively.

FIG. 12A shows a turbo-coder which complies with the following transmission technology:

• • WMAN-SCa,
  • WMAN-OFDM,
  • WMAN-OFDMA.

This turbo-coder is well known and will not be described in further details hereinafter. This turbo-coder has two inputs A and B and one output Y.

FIG. 12B shows the configuration of circuit 2 to implement the turbo-coder of FIG. 12A. In the illustrated configuration, it has been assumed that circuit 2 has simplified switch matrices which does not allow to configure the connections between two successive clusters in the same row.

As illustrated in FIG. 12B, the simplification of the switch matrix does not prevent from configuring circuit 2 to implement the turbo-coder of FIG. 12A.

In this configuration, inputs E₀ and FI₀ correspond to inputs A and B of FIG. 12A. Outputs FO₃ corresponds to output Y of FIG. 12A.

Outputs BO₀, S₁, FO₁, S₃ are not used.

FIG. 13A shows a scrambler which is defined in the UMTS standards for HS-DSCH or commonly called HSDPA (High Speed Downlink Packet Access). Thus, this scrambler will not be described in further details. It has a bit stream input b_R and a bit stream output d_k. Cells with symbol pⁱ are delay lines of one clock period.

FIG. 13B shows the configuration of circuit 2 to implement the scrambler of FIG. 13A.

Only five clusters CL₀ to CL₄ are used. Input E₀ receives the bit stream b_k. Output FO₀ outputs the bit stream corresponding to bit stream d_k of FIG. 13A. Output S₀ and S₄ are not used.

Many other embodiments are possible. For example, inputs TI_ij and outputs TO_ij can be omitted if coding schemes requiring such transversal connections are not required. In another embodiment, adder A_5j can also be omitted.

Circuit 2 has been disclosed in the specific case where it comprises nine clusters of five cells. However, such an integrated circuit can also be built using only five to ten clusters. This range of number of clusters corresponds to configurations which are both flexible and fast in executing any calculation of code.

The size of the switch matrices can be reduced if cluster CL_j can only be connected to the following cluster CL_j+1. This also reduces the size of the corresponding configuration registers SR₁ to SR₄. It is also possible to reduce the size of the switch matrices by having only one output to be connected to only one input of another cluster.

Cell Ce_i,j can be omitted if it is not necessary to implement the generation of CRC codes.

The additional adders A_5j connected between outputs FO_4j and output FO_j can be replaced by an adder connected between output S_4j and output S_j.

In the present specification and claims the word “a” or “an” preceding an element does not exclude the presence of a plurality of such elements. Further, the word “comprising” does not exclude the presence of other elements or steps than those listed.

The inclusion of reference signs in parentheses in the claims is intended to aid understanding and is not intended to be limiting.

From reading the present disclosure, other modifications will be apparent to persons skilled in the art. Such modifications may involve other features which are already known in the art of encoding data and which may be used instead of or in addition to features already described herein.

Claims

1. An integrated circuit configurable to encode data according to one of a predetermined plurality of coding schemes comprising block, convolutional and turbo codes and to generate cyclic redundancy codes, said integrated circuit comprising: a) a plurality of specific hardware cells, each cell comprising: outputs Sij, FOij, BOij and TOij for binary signals,inputs Eij, BIij, FIij and TIij for binary signals,a buffer to delay by one clock period a binary value received on input Eij and to output a one-clock period delayed binary value E*,binary adders to perform XOR operations,configurable multiplexers connecting the outputs, the inputs, the buffer and the adders to each other according to several configurable paths, the characteristic equations of the cell being: TOij=Sij=Ctm.TIij+!Ctm.OutputMux4OutputMux4=Cmm0.Cmm1.E*+!Cmm0.Cmm1.(E*XOR BIij)+Cmm0.!Cmm1.E+!Cmm0.!Cmm1.(Eij XOR FIij)BOij=Cbm.(Sij XOR BIij)+!Cbm.BIij orBOij=Cbm0.Cbm1.(Sij XOR BIij)+!Cbm0.Cbm1.BIij+!Cbm0.Cbm1.Sij FOij=Cfm.(Sij XOR FIij)+!Cfm.FIij where:Sij, FOij, BOij and TOij are the binary signals output on outputs Sij, FOij, BOij and TOij, respectively,Eij, BIij, FIij and TIij are the binary signals received on inputs Eij, BIij, FIij and TIij, respectively,“!” is the NOT operation,“*” is the output of the buffer,“XOR” is the XOR operation,“+” is the OR operation,“.” is the AND operation,Cbm, Cbm0, Cbm1, Cfm, Cmm0, Cmm1 and Ctm are respective binary values that represent the configuration of each multiplexer,b) controllable switch matrices external to each cell and able: to electrically connect and, alternatively, to electrically disconnect input Eij to/from at least the output Sij of another cell and to electrically connect and, alternately, to electrically disconnect input Eij to/from an external binary data source,to electrically connect and, alternately, to electrically disconnect at least input FIij to/from at least the output FOij of another cell,to connect and, alternately, to disconnect input BIij to/from at least the output BOij of another cell.

2. An integrated circuit configurable to encode data according to one of a predetermined plurality of coding schemes comprising block, convolutional and turbo codes and to generate cyclic redundancy codes, said integrated circuit comprising: a) a plurality of specific hardware cells, each cell comprising: outputs Sij, FOij, and BOij for binary signals,inputs Eij, BIij, and FIij for binary signals,a buffer to delay by one clock period a binary value received on input Eij and to output a one-clock period delayed binary value E*,binary adders to perform XOR operations,configurable multiplexers connecting the outputs, the inputs, the buffer and the adders to each other according to several configurable paths, the characteristic equations of the cell being: Sij=!Ctm.OutputMux4OutputMux4=Cmm0.Cmm1.E*+!Cmm0.Cmm1.(E*XOR BIij)+Cmm0.!Cmm1.E+!Cmm0.!Cmm1.(Eij XOR FIij)BOij=Cbm.(Sij XOR BIij)+!Cbm.BIij orBOij=Cbm0.Cbm1.(Sij XOR BIij)+!Cbm0.Cbm1.BIij+!Cbm0.Cbm1.Sij FOij=Cfm.(Sij XOR FIij)+!Cfm.FIij where:Sij, FOij and BOij are the binary signals output on outputs Sij, FOij and BOij, respectively,Eij, BIij and FIij are the binary signals received on inputs Eij, BIij and FIij, respectively,“!” is the NOT operation,“*” is the output of the buffer,“XOR” is the XOR operation,“+” is the OR operation,“.” is the AND operation,Cbm, Cbm0, Cbm1, Cfm, Cmm0, and Cmm1 are respective binary values that represent the configuration of each multiplexer,b) controllable switch matrices external to each cell and able: to electrically connect and, alternatively, to electrically disconnect input Eij to/from at least the output Sij of another cell and to electrically connect and, alternately, to electrically disconnect input Eij to/from an external binary data source,to electrically connect and, alternately, to electrically disconnect at least input FIij to/from at least the output FOij of another cell,to connect and, alternately, to disconnect input BIij to/from at least the output BOij of another cell.

3. The integrated circuit according to claim 2, wherein the integrated circuit comprises a plurality of clusters CLj, each cluster CLj comprising: inputs Ej, FIj and BIj,outputs Sj, BOj and FOj,a succession of at least two cells Cij successively electrically connected to each other, the first cell of the succession having its inputs Eij and FIij and its output BOij directly connected to inputs Ej, FIj and output BOj without configuration possibility, respectively, the last cell of the succession having its input BIij and its outputs Sij and FOij connected, without configuration possibility to input BIj, outputs Sj and FOj, respectively, andany cell other than the last cell having its input BIij and its outputs Sij and FOij connected, without any configuration possibility, to output BOij and inputs Eij and FIij of the following cell of the succession, respectively, andwherein the switch matrix is only able to configure the electrical connections between cluster inputs and outputs without being able to configure the electrical connections between cells within a cluster.

4. The integrated circuit according to claim 3, wherein the outputs Sj, FOj and the input BIj of at least one cluster are connected to inputs Ej, FIj and output BOj of another cluster without configuration possibility, respectively.

5. The integrated circuit according to claim 3, wherein the integrated circuit comprises between five to ten clusters and each cluster is composed of five cells.

6. The integrated circuit according to claim 3, wherein each cluster has at least one cell having the following characteristic equation: BOij=Cbm0.Cbm1.(Sij XOR BIij)+!Cbm0.Cbm1.BIij+!Cbm0.Cbm1.Sij

7. The integrated circuit according to claim 3, wherein the inputs TIij of the succession of cells of a cluster, are directly connected to respective outputs TOij of the succession of cells of another cluster without any configuration possibility.

8. The integrated circuit according to claim 3, wherein a cluster CLj comprises an input AIj and an adder having an first input directly connected to input AIj, a second input and an output, the second input and the output of the adder being: either connected to output FOij of the last cell and to output FOj, respectively,or connected to output Sij of the last cell and to output Sj, respectively.

9. A hardware cell optimized for use in an integrated circuit encoder comprising: a first multiplexer/adder circuit having an input section coupled to first, second, third, and fourth binary inputs, and an output coupled to a first binary output;a second multiplexer/adder circuit having an input section coupled to the second binary input, and an output coupled to a second binary output;a third multiplexer/adder circuit having an input section coupled to the third binary input, and an output coupled to a third binary output; anda buffer having an input coupled to the first binary input and an output coupled to the input section of the first multiplexer/adder circuit.

10. The hardware cell of claim 9 wherein the first multiplexer/adder circuit comprises: a four-input multiplexer;a two-input multiplexer having an input coupled to an output of the four-input multiplexer;a first two-input adder having an output coupled to an input of the four-input multiplexer; anda second two-input adder having an output coupled another input of the four-input multiplexer.

11. The hardware cell of claim 9 wherein the second multiplexer/adder circuit comprises: a two-input multiplexer; anda two-input adder having an output coupled to an input of the two-input multiplexer.

12. The hardware cell of claim 9 wherein the second multiplexer/adder circuit comprises: a three-input multiplexer; anda two-input adder having an output coupled to an input of the two-input multiplexer.

13. The hardware cell of claim 9 wherein the third multiplexer/adder circuit comprises: a two-input multiplexer; anda two-input adder having an output coupled to an input of the two-input multiplexer.

14. An integrated circuit encoder comprising: a plurality of hardware cells in electrical communication each comprising a first multiplexer/adder circuit having an input section coupled to first, second, third, and fourth binary inputs, and an output coupled to a first binary output; a second multiplexer/adder circuit having an input section coupled to the second binary input, and an output coupled to a second binary output; a third multiplexer/adder circuit having an input section coupled to the third binary input, and an output coupled to a third binary output; and a buffer having an input coupled to the first binary input and an output coupled to the input section of the first multiplexer/adder circuit; anda programmable switch matrix coupled to the plurality of hardware cells.

15. The integrated circuit encoder of claim 14 wherein the switch matrix is only able to configure electrical connections between inputs and outputs of a cluster of hardware cells without being able to configure the electrical connections between hardware cells within a cluster of hardware cells.

16. The integrated circuit encoder of claim 14 configured to provide convolutional encoding operations that comply with any one of the following standards: GSM, UMTS, DMB, CDMA 2000, iDEN (Integrated Digital Enhanced Network), PHS (Personal Handy-phone System), PDC (Personal Digital Cellular), WPAN, WLAN, WMAN, or DVB (Digital Video Broadcasting).

17. The integrated circuit encoder of claim 14 configured to provide turbo encoding operations that comply with any one of the following standards: UMTS, SDMB (Satellite Digital Multimedia Broadcasting), CDMA 2000, or WMAN.

18. The integrated circuit encoder of claim 14 configured to provide randomization and scrambling operations that comply with any one of the following standards: UMTS, CDMA 2000, WMAN, WLAN, DMB, DAB, or DVB.

19. The integrated circuit encoder of claim 14 configured to provide a spreading process.

20. The integrated circuit encoder of claim 14 wherein the first multiplexer comprises a four-input multiplexer.