Patent Application
20060218424
This invention relates to integrated circuits, and more particularly, to methods and apparatus for autonomously reducing power consumption for integrated circuits.
High-speed operation of integrated circuits generally leads to high power consumption. One goal in designing an integrated circuit is to reduce power consumption, especially for portable electronic devices. Because the power consumed by an integrated circuit is proportional to the clock frequency and the applied voltage of the integrated circuit, the conventional approaches for reducing power consumption have focused on clock and voltage scaling. These conventional approaches include a) reducing the operating voltage of the integrated circuit, b) reducing the clock frequency of the integrated circuit, and c) shutting off the clock to the integrated circuit.
In these conventional approaches, various algorithms are used to determine when to initiate power saving controls. In general these algorithms are software based and execute on a processor that resides on-chip or off-chip.
These conventional approaches generally require that the integrated circuit designer make provisions in the design to allow the software to monitor activities (variables) and thereby to control power management functions. However, as integrated circuits become more complex and more flexible/programmable, it is difficult for the integrated circuit designers to anticipate the applications for their chip and thus to anticipate what signals or variables should be monitored for power management. Furthermore, while in use, because of the complexity and the large-scale integration of the circuit, the “visibility” of the operation of individual blocks or cores is limited. Thereby, it becomes difficult for the designers or users to decide when and which sections of the integrated circuit should be disabled or voltage or frequency of which should be scaled for power saving.
Moreover, the conventional approaches typically rely on a centralized decision mechanism for power management having the power management software run on one processor to control the power consumption of large system blocks and peripherals. These conventional techniques often fail to monitor activity and functionality of individual blocks or cores and thereby fail to manage power consumption at a block or core level. In these conventional approaches, if one core of a large system block is functioning, the system may have to keep the whole system block working. Therefore, the power saved by these conventional approaches is limited.
Accordingly, there is a need for a new approach to locally and dynamically manage power consumption of individual blocks or cores of an integrated circuit. SUMMARY
The present invention is directed to addressing the above need by way of an autonomous on-chip power management system, which has power management circuitry distributed in an integrated circuit. An integrated circuit generally employs a multi-core or block data processing structure on a semiconductor chip. The term “core” designates pre-packaged design modules that a designer of an integrated circuit employs, usually without any changes. The distributed power management circuitry is able to monitor activities of cores or other functional blocks, providing greater visibility of the operation of cores or functional blocks, and thereby is able to manage power consumption of individual cores or functional blocks locally. The dynamic localized power management can be performed faster than centralized mechanism used in the prior art approaches, thus enabling more real-time applications of power management. The power management system of the present invention is also able to determine an optimal setting in real-time for a particular integrated circuit design to achieve most effective power saving. It achieves this without any change to the operating system of the device, and without any change to the software application it supports. Hence, it is labeled as “autonomous power management system”.
According to one aspect of the present invention, the power management system of the present invention includes power management circuitry connected to a functional block, which includes a core, a group of cores, or a part of a core, for managing the power consumption of the functional block. The power management circuitry is preferably implemented in the form of circuit blocks distributed among the multiple cores of the integrated circuit.
The power management circuitry may include fixed logic circuits, or alternatively, include at least partially reprogrammable or reconfigurable logic circuits, to observe signals transmitted in the integrated circuit, and based on certain conditions in the observed signals, to set the functional block to a power saving mode. The power management circuitry including at least partially reprogrammable or reconfigurable logic circuits provides the user with the ability of dynamically changing the predetermined conditions under which the functional block should be set to the power saving mode. The reconfigurable circuits also enable the user to fix functional errors in the power management circuitry, as well as functional errors in the integrated circuit, after the integrated circuit has been fabricated.
Functional blocks generally include sequential logic circuits and/or combinational logic circuits. The power management circuitry, according to one aspect of the present invention, is adapted to reduce the clock speed of a system clock associated with the sequential logic circuits of a functional block, and/or to gate off the inputs to the combinational logic circuits of the functional block, and thereby to reduce power consumption of said functional block.
In one preferred embodiment, the power management circuitry includes a controller that is configured to monitor signals associated with a particular functional block, for example signals at the inputs and/or outputs of the functional block or signals remote to the functional clock but related to the function of the functional block, or other signals, for detecting a predetermined condition associated with the signals. The controller is configured to “anticipate” what the state that the block will be, for example, a normal-operational or a power saving mode (partially-operational or non-operational mode), from monitoring the signals at the input and/or outputs of the functional block. In response to the detection of the predetermined condition, the controller sets the functional block to a power saving mode. In response to the detection of another predetermined condition (hereinafter referred as reactivating condition) under which the functional block should be in normal operational mode, the controller sets the functional block to the normal operational mode.
In one preferred embodiment, the power management circuitry includes registers for specifying and storing data indicative of the predetermined condition. For example, the power management circuitry may include two registers for storing numerical values, such as values representative of digital or analog signals. In one preferred form, one register stores a high digital value and the other stores a low digital value, where the “predetermined condition” is defined as being present when a monitored value is between the high and low digital values. This situation may be reversed in other embodiments, that is, the predetermined condition is that the monitored signal is outside the range defined by the upper and lower digital values. In one preferred form, the registers are user-settable so that a user can modify the definition of the “predetermined condition” to be a desired range.
The power management circuitry may further include a counter connected to the controller, which includes a register for specifying additional information representative of the defined predetermined condition. For example, the register of the counter can be set to specify a predetermined duration, and in use, the counter counts the time that the monitored signals are outside the range defined by the low and high numerical values. In this case, the predetermined condition may be defined to occur when the signals at the inputs and/or outputs are outside the range defined by the low and high numerical values for the predetermined duration.
According to another aspect of the present invention, the power management circuitry includes a clock control circuit coupled to the controller and a system clock of the functional block. In general, the system clock generates a clock signal to drive the functional block. The clock control circuit is adapted to decrease the speed of the clock signal or disable the clock signal to the functional block in response to instructions from the controller (in other words, the clock rate is lowered or set to be zero), and thereby to set the functional block to a power saving mode.
According to a further aspect of the present invention, the power management circuitry further includes an input control circuit coupled to the inputs of the functional block. The input control circuit is connected to and controlled by the controller. The input control circuit is adapted to disable the input signals to the functional block in response to the detected predetermined condition, and in response to the detected reactivating condition, to enable the input signals to the functional block.
In response to the reactivating conditions in the signals at the inputs and/or outputs of the functional block, the power management circuitry should reactivate the functional block by enabling the clock signal and the input signals. One key issue in reactivation of the functional block is that data may be lost during the reactivation because of the delayed response of the power management circuitry and the functional block. The present invention includes several forms to resolve such issues. According to one preferred form of the invention, data loss is avoided by driving the power management circuitry with a clock signal, which has a faster clock speed than the clock signal of the system clock, or alternatively, is a phase-shifted version of the clock signal of the system clock. According to another preferred form, the controller monitors a signal that is associated to the functional block but is remote from the functional block. In these embodiments, the controller is able to detect the reactivating condition in the monitored signals in a relatively early time frame and enables the clock signal and the input signals to the functional block correspondingly earlier, so that the functional block is able to capture the signals at the inputs without losing any data.
In a further preferred embodiment, the power management circuitry includes a pipeline connected between the input of the functional block and the controller, and a multiplexer connecting the input and an output of the pipeline to the functional block. The multiplexer is configured to select signals from either the input or the output of the pipeline to be passed through the multiplexer to the functional block.
The user designed integrated circuit may have a pipeline coupled at the input of the functional block. In this case, the input signals passing through the pipeline may be delayed by the pipeline with “n” cycles, where “n” is the number of pipeline registers of the pipeline. The power management circuitry, which monitors the input signal before they enter the pipeline has “n” cycles to reactivate the functional block without losing any data.
As described above, a customer designed integrated circuit generally includes multiple cores or functional blocks. As disclosed in the related patent application, an on-chip reconfigurable wrapper can be coupled to the cores and to reconfigure the functionality of the cores. In one preferred embodiment of the present invention, the power management circuitry as described above is implemented in the reconfigurable wrapper for managing power consumption of a functional block.
FIG.2 shows a diagram of power management circuitry associated with a functional block according to one preferred embodiment of the present invention;
FIG.3 shows a diagram of power management circuitry associated with a functional block according to another preferred embodiment of the present invention;
FIG.5 shows a diagram of the power management circuitry associated with a functional block according to a further preferred embodiment of the present invention;;
FIG.6 shows a data flow diagram of the embodiment in FIG.5 according to the present invention;
FIG.7 shows a diagram of the power management circuitry associated with a functional block according to another preferred embodiment of the present invention;
Various embodiments of the present invention will be described with reference to the accompanying drawings. It is to be noted that the same or similar reference numerals are applied to the same or similar parts and elements throughout the drawings, and the description of the same or similar parts and elements will be omitted or simplified.
As shown in
The functional block generally includes sequential logic circuits and/or combinational logic circuits. The sequential logic circuits are associated with a clock signal. As shown in
According to one preferred form of the present invention, the power management circuitry is configured with fixed logic circuits. According to another preferred form of the present invention, the power management circuitry includes at least partially reprogrammable logic circuits.
In one form, the power management circuitry is configured to monitor “enabling signals”, the value of which decides whether a functional block is in a “don't care” situation. For example, if a functional block outputs its result through an AND gate, another input signal of such AND gate will be an “enabling signal” to the functional block, and if the “enabling signal” is “0”, the output of the AND gate will be “0”, no matter what the result of the functional block would be. When the “enabling signal” is “0”, the functional block is in a “don't care” situation, and should be set to a power saving mode. Alternatively, the power management circuitry can be configured such that only when the “enabling signal” remains being “0” for a certain time period, the functional block is set to a power saving mode.
The “enabling signal” currently being “0” or being “0” for a certain duration is one type of predetermined conditions in the monitored signals under which the power management circuitry sets the associated functional block to a power saving mode. Such predetermined conditions can be other forms, for example, activities at the input and/or output of a functional block, such as the monitored value being below a predetermined certain value or over a predetermined certain value, instructions from a higher level control mechanism to set the functional block to a power saving mode, etc.
Exemplary power management circuitry embodying the invention is illustrated in detail in
As shown in
The counter 104 is connected to the controller 102. The counter 104 preferably includes a loadable register 116 used to specify a counter value, which can be used as another predetermined condition. The monitored input signals are transmitted through the pipeline 108 and the controller 102 to the counter 104. The counter 104 can be used to count time period for which an input signal is in the predetermined condition as set by the controller 102. When the time period reaches the specified count value stored in the counter 104, the counter 104 triggers the controller 102 to send a control signal to the clock control circuit 106. In other forms, the counter 104 can be configured to count other values, for example, to count the number of times that a pattern occurs in the monitored signals.
The clock control circuit 106 may be configured to slow down the speed of the clock or to disable the clock signal 204 to the functional block 200. For example, the clock control circuit 106 can be configured to switch the clock signal from a higher clock rate to a lower clock rate in a power saving mode. For another example, the clock control circuit 106 may include an AND gate, where the system clock 204 is connected to one input of the AND gate and the controller 102 is connected to another input of the AND gate. When in a power saving mode as determined by the controller 102, the controller 102 sends a logic low signal (i.e., “0”) to the AND gate to disable the clock signal to the functional block 200.
The input control circuit 107 is configured to disable input signals to the functional block 200. For example, the input control circuit 107 may include a plurality of AND gates each having an input coupled to an input interconnect of the functional block and the other input coupled to the controller 102, and an output coupled to the input pins of the functional block 200. In response to a logic low signal generated by the controller 102, the AND gates disable the associated input signal to the functional block 200.
As described above, in one preferred form, the registers in the controller 102 and the counter 104 are reprogrammable, and thereby, the predetermined conditions, which are specified in these registers can be modified as desired by a user. Either the controller 102 or the counter 104 can be configured to be used as a comparator to determine whether the input signals meet the predetermined condition. Alternatively, as described in the following exemplary embodiment, the controller 102 and counter 104 can be configured to be used as a whole to set multiple conditions, and only when the input signals meet the multiple conditions, the controller 102 sends control signals to the clock control circuit 106 and the input control circuit 107 to set the functional block 200 to the power saving mode.
FIG.3 illustrates an exemplary embodiment of the power management circuitry which can be used in audio devices, such as MP3 players, in accordance with the present invention. As shown in
The power management circuitry 100 is also adapted to reactivate the clock signal 204 and the input signals to the functional block 200 when the controller 102 detects another predetermined condition (hereinafter referred as reactivating condition) under which the functional block should be reactivated to a normal operational mode. The reactivating condition can be an instruction signal for reactivating a particular functional block, occurrence of a signal that is not in the predetermined condition under which the functional clock 200 should be in the power saving mode, or other forms. For example, if the output of the functional block is coupled to an AND gate with an “enabling signal”, the reactivating condition can be that the “enabling signal” has a value of “1”. Upon detection of the reactivating condition, the controller 102 sends a control signal to the clock control circuit 106 and the input control circuit 107 to activate the clock and the input to the functional block 200. For example, if the clock control circuit 106 is an AND gate as described above, the controller 102 may send a logic high signal, i.e. “1”, to the AND gate to enable the clock signal to the functional block 200.
A key issue in reactivating the functional block 200 is how to reactivate the functional block on time without losing any data.
In
FIG.5 illustrates another exemplary embodiment of the power management 100, which is used with a customer designed circuit including a user defined functional block 200, a system clock 204, an input data bus 202, and a pipeline 210 at the input of the functional block 200. The input signals from the interconnect 226 pass through the pipeline 210 and enter into the functional block 200. The functional block 200 and the pipeline 210 are both driven by the system clock 204. The power management circuitry 100 for the functional block 200 is similar to the power management circuitries shown in FIGS.2 and 3, except that the reactivating mechanism used in this situation (the input signals are pipelined into the functional block) may be slightly different, which is described in detail below and together with the timing diagram in
FIG.6 illustrates the timing diagram showing the clock signals and data transitions in the monitored input data bus 202 of the functional block 200, where the input data is pipelined before enters into the functional block 200. The original system clock 220, which has the same clock rate as the system clock 204, is used only for purpose of illustrating the timing of the system and is not a real clock signal used in the power management circuitry 100 or the functional block 200. As shown in the example in
In a preferred embodiment, the power management circuitry 100 may include a pipeline, which receives the input signals from the interconnect 226 and which can be used to delay the input signals to the functional block 200. As shown in
In a further preferred form, the monitor signal may be remote to the functional block, and the reactivating condition associated with the monitored signal may be detected in an earlier time frame, so that the power control circuitry has enough time to reactivate the functional block. For example, as shown in
FIG.7 illustrates another embodiment of the present invention, in which the power management circuitry 100 is adaptive. In other words, the power management circuitry 100 is able to automatically adjust its logic or stored condition values, for example, the count value and the low and high numerical values, to achieve an optimal mode for power management for the functional block. For example, to be adaptive, the controller 102 is connected to the system clock 204 by an interconnect 228 to receive the clock signal from the system clock 204 for counting the number of cycles that the functional block 200 has been in the power saving mode, and based on this information, the controller 102 calculates the amount of energy saved. Then the controller 102 adjusts the logics or parameters of the stored predetermined conditions to achieve the optimal situation for power saving for the functional block.
As described above, the power management circuitry 100 can be configured with fixed logic circuits, or with at least partially reprogrammable logic circuits. The techniques for constructing reprogrammable logic circuits are described in detail below and also disclosed in the related patent application.
The core 20 is used in a simple instance of a “system on a chip,” or SoC. The SoC communicates with the core 20 via inputs 21 and outputs 24. The core 20 includes input leads 22 and output leads 23. Certain of the input leads and/or output leads are selected, based on a user's design arrangement, to be coupled to the wrapper 30 for selectively making certain parts or functions of the core 20 easy to observe and control. In one embodiment shown in the diagram in
The wrapper 30 includes a functionally reconfigurable module (FRM) 40 that is coupled to the input cell set 31 and the output cell set 34. The FRM 40 may be implemented with, for example, a field programmable array, and some control circuitry, where the functionality of the field programmable array is determined by the contents of a configuration memory that is part of the field programmable array. The FRM 40 also includes an input 41 (for example, a multi-lead bus) and an output 42, which, when daisy-chained through a set of wrappers in an SoC, enables all of the FRMs in the SoC to be configured through the connections between the wrappers. Thus, in accord with the principles disclosed herein, a flexible SoC is created with a REFAB (reconfigurable fabric), which is a set of wrappers each comprising a collection of input cells, output cells, and an FRM. The FRM includes field programmable logic and memory that configures the logic and the interconnections within the FRM.
It may be noted that the input cell set 31 and the output cell set 34 may be embedded within the FRM 40, but for purpose of illustration, FIG.8 shows the embodiment that has the input cells 31 and output cells 34 disposed outside the FRM 40.
In one preferred form, output cells within a wrapper are constructed as shown for cell 34-i. That is, a cell comprises a two-input multiplexer 32 that has one input connected to an output lead of the associated core. That same output lead of the core is also connected to the FRM of the wrapper, that is, the FRM 40-1 in
Alternatively, the output cells within a wrapper may be constructed as shown for the cell 34-f. As shown in
Input cells within a wrapper are constructed as shown for the cell 31 -j with, for example, a two-input multiplexer 35. The outer input lead 21-j of the wrapper is connected to one input of the multiplexer 35 and to the associated FRM. A second input to the multiplexer 35 is received from the FRM, and the output of the multiplexer 35 is connected to the input lead 22-j of the associated core. As with the cell 34-i, configuration bits within the FRM control the state of the multiplexer 35.
To illustrate different output cell designs,
In one preferred form, the power management circuitry 100 is an independent circuit that is coupled to the functional block 200 and is configured with reprogrammable logic circuits as described above. Alternatively, the power management circuitry 100 is a part of a reconfigurable wrapper that is coupled to the functional block 200 not only to manage power consumption of the functional block 200, but also to modify the inputs and/or outputs of the functional block 200, and thereby to change the functionality of the functional block 200.
While the claimed invention has been described in detail and with reference to specific embodiments thereof, it will be apparent to one of ordinary skill in the art that various changes and modifications can be made to the claimed invention without departing from the spirit and scope thereof. Thus, for example those skilled in the art will recognize, or be able to ascertain, using no more than routine experimentation, numerous equivalents to the specific substances and procedures described herein. Such equivalents are considered to be within the scope of this invention, and are covered by the following claims.
Appendices that aid in understanding of the present invention are further incorporated within the present specification. Appendix A is a U.S. Patent Application Publication (Pub. No.: US 2004/0212393), which has been incorporated in this application by reference. Appendices B and C include Verilog HDL programs that implement the exemplary modules shown in the figures. In these two Appendices, Appendix B, which includes Verilog HDL codes together with a diagram of an exemplary module and pointers between the codes and the diagram, is a top level module containing registers, counter, and controller. Appendix C implements a shift register in a pipeline, which is incorporated in the program in Appendix B.
