Patent Application
20090122633
Increased performance in modern electronic devices has been achieved using several methods such as operating the devices at increased clock speeds, widening busses that transfer data, and the like. The improvement in performance has usually come at the cost of increased power consumption. Increased power consumption may result in excessive heat generation which, in turn, may be harmful to device components and performance.
So that the manner in which the above recited features of the present invention can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.
In the following, reference is made to embodiments of the invention. However, it should be understood that the invention is not limited to specific described embodiments. Instead, any combination of the following features and elements, whether related to different embodiments or not, is contemplated to implement and practice the invention. Furthermore, in various embodiments the invention provides numerous advantages over the prior art. However, although embodiments of the invention may achieve advantages over other possible solutions and/or over the prior art, whether or not a particular advantage is achieved by a given embodiment is not limiting of the invention. Thus, the following aspects, features, embodiments and advantages are merely illustrative and are not considered elements or limitations of the appended claims except where explicitly recited in a claim(s). Likewise, reference to “the invention” shall not be construed as a generalization of any inventive subject matter disclosed herein and shall not be considered to be an element or limitation of the appended claims except where explicitly recited in a claim(s).
Embodiments of the invention may generally be used with any type of memory. In one embodiment, the memory may be a circuit included on a device with other types of circuits. For example, the memory may be integrated into a processor device, memory controller device, or other type of integrated circuit device. Devices into which the memory is integrated may include system-on-a-chip (SOC) devices. In another embodiment, the memory may be provided as a memory device which is used with a separate memory controller device or processor device.
Whether the memory is integrated into a device with other circuits or is provided as a separate device, the memory may be used as part of a larger computer system. The computer system may include a motherboard, central processor, memory controller, the memory, a hard drive, graphics processor, peripherals, and any other devices which may be found in a computer system. The computer system may be part of a personal computer, a server computer, or a smaller system such as an embedded system, personal digital assistant (PDA), or mobile phone.
In some cases, a device including the memory may be packaged together with other devices, typically referred to as a multi-chip package. Devices within the multi-chip package may be connected via wire bonds or other types of connections to a circuit board with one or more layers of interconnections. The devices and the circuit board may be enclosed within a packaging material such as a molded encapsulant or a ceramic packaging material. Such packages may include any other types of devices, including other devices with the same type of memory, other devices with different types of memory, and/or other devices including processors and/or memory controllers. Also, in some cases, the memory may be included in a device mounted on a memory module. The memory module may include other devices including memories, a buffer chip device, and/or a controller chip device. The memory module may also be included in a larger system such as the systems described above.
In some cases, embodiments of the invention may be used with multiple types of memory or with a memory which is included on a device with multiple other types of memory. The memory types may include volatile memory and non-volatile memory. Volatile memories may include static random access memory (SRAM), pseudo-static random access memory (PSRAM), and dynamic random access memory (DRAM). DRAM types may include single data rate (SDR) DRAM, double data rate (DDR) DRAM, low power (LP) DDR DRAM, and any other types of DRAM. Nonvolatile memory types may include magnetic RAM (MRAM), flash memory, resistive RAM (RRAM), ferroelectric RAM (FeRAM), phase-change RAM (PRAM), electrically erasable programmable read-only memory (EEPROM), laser programmable fuses, electrically programmable fuses (e-fuses), and any other types of nonvolatile memory.
The supply circuit 110 may be connected to a power input 111 of the integrated circuit 101. The power input 111 may comprise terminals for connecting to a power supply of an external circuitry, such as a circuit system, a memory module, a multi chip module, or a computer system. In this way, the power input 111 may receive a circuit supply current 151, which may comprise one or more currents to the integrated circuit 101 and one or more currents from the integrated circuit 101. The terminals of the power input 111 may include a ground voltage terminal and a supply voltage terminal. The power input 111 may furthermore comprise more supply voltage terminals in order to, for example, provide different supply voltages in respect to a common ground potential to the integrated circuit 101, and/or to distribute a supply current to the integrated circuit 101 to more than one terminal. This may serve the purpose of a balanced distribution of a circuit supply current and/or the balancing of supply and ground potentials at different locations of the integrated circuit 101.
The supply circuit 110 may provide a supply current 152 to the main circuit 140. The supply current 152 may comprise one or more currents to the main circuit 140 and one or more currents from the main circuit 140. The supply circuit 110 may comprise circuitry to provide and/or regulate the supply current 152 based on the circuit supply current 151 received from the power input 111. In some embodiment, the supply circuit 110 may comprise any combination of a linear voltage regulator, a step-up converter, a step-down converter, a switching voltage regulator, a voltage pump, one or more power generators, operational amplifiers, voltage references, driver transistors, and related functional elements.
The main circuit 140 may comprise an integrated circuit, such as a memory circuit, a signal circuit, a central processing unit circuit, a signal processing unit, a logic circuit, an analogue circuit, and/or combinations thereof. In case the main circuit 140 comprises a memory circuit, the main circuit 140 may comprise sub-circuits such as a memory cell array, line decoders and column decoders, multiplexers, signal line drive circuits, and the like. The main circuit 140 may be operated in one or more operation modes, for example, enabled mode, active mode, disabled mode, hibernation mode, sleep mode, suspend mode, power safe mode, standby mode, and/or one or more different operation modes. The main circuit 140 may require and/or consume different median supply currents in its different operation modes. As an example, the main circuit 140 may require a maximal operation current in a normal operation mode, whereas a substantially lower supply current may be required by the main circuit 140 being in a disabled and/or power safe mode.
The sensing circuit 120 may sense the supply current 152, or the constituent partial currents thereof, being supplied by the supply circuit 110 to the main circuit 140. In one embodiment, the sensing circuit 120 may comprise a shunt, such as a resistor, a diode, a transistor, a field effect transistor (FET), an n-channel field effect transistor (NFET), or an FET providing a weak inversion. The shunt may furthermore comprise a semiconductor and/or a conductor. The shunt may convert a current into a voltage, which may, in turn, be converted into a digital value, for example, by means of an analog-to-digital converter (ADC). For example, in the case of a ohmic shunt, the voltage drop V along the shunt R may be linearly proportional to the current/flowing through the shunt, i.e.
V=R×I. (1)
In the case of a diode or transistor shunt, the voltage drop V along the shunt R may be proportional to a threshold voltage Vth and a dynamic compression In(I/Is) according to
V=Vth×In(I/Is). (2)
The sensing circuit 120 may in such a way sense the supply current 152 and convert it to a measured result 153, which may comprise an analog signal or a digital value.
In some embodiments, the measured result 153 of the supply current 152 may be fed back to a control circuit 130. The control circuit 130 may control the supply circuit 110 based on the measured result 153.
In one embodiment, the control circuit 130 may send a respective control signal 154 to the supply circuit 110. In this way, for example, the control circuit 130 may enable or disable individual power generators of the supply circuit 110, such as to enable only a required minimum number of power generators of the supply circuit 110 to provide the required current 152, leaving a remainder of power generators of the supply circuit 110 disabled and/or unused. Such disabled power generators of the supply circuit 110 may then be excluded from consuming unnecessary power. The supply circuit 110 may, however, comprise an excess number of individual power generators to allow for a sufficient and reliable power supply under conditions and/or operation modes of peak power consumption, or to allow for process variations during manufacturing or operation of the integrated circuit 101.
Power generators, such as voltage regulators, step-down converters, or step-up converters, convert an input current at an input voltage to an output current at an output voltage. Although modern switching voltage regulation schemes may attain a high efficiency, a fraction of the input power may be lost as heat during voltage conversion. In the case of a linear power regulator, the input voltage may exceed the required output voltage for an identical input and output current. The voltage difference between the input voltage and the output voltage, multiplied by the current may be, in such a case, lost as thermal heat within a shunt, such as a resistor, a diode, or a transistor.
According to the embodiment illustrated in
According to the embodiment illustrated in
According to the embodiment illustrated in
The switch element 135 may comprise any one of the group of a fuse, an e-fuse, an electronically settable fuse, a programmable read only memory (PROM) cell, a flash-RAM cell, a transistor with a consumable gate and/or channel. The state of a switch element 135 may control the supply circuit 110.
According to an embodiment, the switch element 135 may directly determine a state of one power generator of the supply circuit 110. In this way, for example, a switch element 135 may store the state of a respective power generator of the supply circuit 110. In the case the switch is in an open-state, the respective power generator may be set to an enabled state, hence outputting power. In the case the switch is in an open-state, the respective power generator may be set to an enabled state, hence outputting power. In the case the switch is in a closed-state, the respective power generator may be set to a disabled state, hence not outputting and conserving power. In alternative embodiments, the opposite may be true, for example, the power generator may be enabled by a closed switch and disabled by an open switch. The switch element 135 may be a non-volatile and stable switch element, i.e. the state of the switch element 135 may be retained even if the power supply to the integrated circuit 103 is switched off.
In this way, the integrated circuit 103 may be powered up and may be put into a specific operation mode, the supply current 152 in the respective mode may be sensed by means of the sensing circuit 120 and the measured result may be accessed from the outside by means of the control circuit 134 and the port 136. The state of the supply circuit 110 may be determined based on the measured result and the sensed current. Subsequently, for example, by means of instructing the control circuit 134 accordingly, the switch element 135 may be set. The setting of the switch element 135 may be effected directly, as high voltage pulses, for example to a gate of a transistor, may be necessary to program the switch element 135.
In some embodiment, the integrated circuit 103 may control the supply circuit 110 directly powering up, i.e. without sensing the supply current 152. This may further increase the device efficiency of the integrated circuit 103. A plurality of switch elements 135 may account for various operation modes of the integrated circuit 103 and may allow for a respective control of the supply circuit 110 by the control circuit 134. In this way, a required number of power generators may be enabled automatically when the integrated circuit 103 is powered up. At the same time, the power generators of the supply circuit 110, which are not required, may be automatically disabled through a respective setting of the switch element 135. Accordingly the integrated circuit 103 then generates only the necessary power for supplying a supply current to the main circuit 140.
A sensing circuit 230 may sense the indicator current Iind 220. The sensing circuit 230 may comprise a shunt, which is connected to a common reference potential, such as a ground potential 231. The sensing circuit 230 may further comprise a shunt, such as a resistor, a diode, and/or a transistor, such that the indicator current Iind 220 may be converted into a indicator voltage Vind 221. For example, in the case that the shunt of the sensing circuit 230 comprises a resistor, the indicator current Iind 220 may be converted lineally into a indicator voltage Vind 221 according to Eq. (1), which is proportionate to the indicator current. For another example, in the case that the shunt of the sensing circuit 230 comprises a diode or a transistor, the indicator current Iind 220 may be converted into a indicator voltage Vind 221 according to Eq. (2). Further examples for a conversion of the indicator current Iind 220 into a indicator voltage Vind 221 include a logarithmic conversion, an exponential conversion, and/or other conversions according to the respective IV-curve characteristics of the respective shunt element.
A further circuit 240 may convert the indicator voltage Vind 221 at the sensing circuit 230 into a measured result or may simply forward the indicator voltage Vind 221, for example as an analog signal, to the control circuit 250. The further circuit 240 may in such respective cases comprise a conversion circuit, such as an analog-to-digital converter (ADC) for providing a digital measured result by means of converting the analog indicator voltage Vind 221 at the sensing circuit 230 into its digital representation. Such analog-to-digital conversion may also be carried out by the control circuit 250, the respective conversion circuit then becoming part of the control circuit 250.
By means of providing the measured result or the analog value signal to the control circuit 250, this control circuit 250 may determine, on the basis of the indicator voltage Vind 221, a number of required power generators 200. In one embodiment, the control circuit 250 may set the respective modes of the power generators 200 via a control line 260 and, in this way, may disable or enable single power generators 200. In this way, the control circuit 250 may set only a required number of power generators 200 to an enabled mode, such that they each provide a partial supply current which sum up to a required supply current Isup 210. By means of enabling only a required number of power generators 200, the power consumption being dissipated by each power generator 200 which is not required may be eliminated.
The supply current Isup 210 may represent the actual current which is to be supplied to a main circuit of an integrated circuit. During operation of such a main circuit or in a specific operation mode of such a main circuit, a maximum supply current Isup* may be required. Simultaneously, each power generator 200 may further be able to provide only a limited maximum partial supply current isup*. A number n of required power generators 200 for supplying the maximum supply current Isup* may than be represented by the next integer number following the fraction:
Isup*/isup* (3)
If the respective integrated circuit comprises N power generators 200, the remainder N-n of the power generators 200 may be disabled. The integrated circuit may comprise a number N power generators 200 such that N is always equal or greater than n for all operation modes and/or under all operation conditions, to allow for a reliable and uninterrupted power supply to the main circuit of the integrated circuit. According to an embodiment, the integer n may be increased by one or more, in order to account for a spare capacity of the supply circuit and in order to handle power consumption peaks within one operation mode in a reliable and efficient manner.
The actual number n may furthermore be dependent on an operation mode of the integrated circuit and may vary during testing, powering up, and/or operation of the integrated circuit. Since the indicator current Iind 220 may be in a relation to the supply current Isup 210, examples may be given for a supply current Isup to be of the order of 10 mA, an indicator current Iind to be of the order of 10 μA, a shunt resistance to be of the order of 100 kΩ, and a resulting indicator voltage Vind to be of the order of 1 V. A current which may be consumed by one of the voltage generators when enabled but not supplying a partial supply current may be of the order of 0.1 mA, 0.5 mA, or 1 mA. Such a quiescent current may be saved and suppressed, if the power generator 200 which is not required is disabled. It is to be noted, that such a current may be saved per disabled power generator 200, and, hence, the overall power saving may be substantial.
According to this embodiment, also a communication circuit 280 may receive the measured result from the further circuit 240, and may store the measured result in a register and/or may transmit the measured result to an external circuitry, such as to a circuit system or computer system. The communication circuit 280 may furthermore communicate with the control circuit 251 in order to determine and/or influence the controlling of the power generators 200. In this way, the controlling of the power generators 200 by the controlling circuit 251 may be supervised, verified, broadcast, determined, and/or influenced by an external circuitry or system, such as an operation system, by means of the communication circuit 280.
Furthermore, a chip control circuit 270 may be coupled to the control circuit 251 in order to determine and/or influence the controlling of the voltage generators 200. Such a chip control circuit 270 may control the main circuit of the integrated circuit and/or an operation mode of such a main circuit. Since the chip control circuit 270 may determine or set an operation mode of the main circuit and the operation mode of the main circuit may affect the required supply current Isup 210, an updated controlling of the power generators 200 may have been rendered necessary. By means of the coupling of the control circuit 251 to the chip control circuit 270 a respective communication and/or signaling may be carried out, such as a transmission of a power mode or operation mode from the chip control circuit 270 to the control circuit 251. In this way, the control circuit 251 may enable or disable respective numbers of power generators according to an operation mode of the main circuit, the operation mode being set by the chip control circuit 270. Situations in which an updated controlling may be necessary may include transitions from a power save mode to an active operation mode, a transition from a sleep mode to a normal mode, or vice versa.
The active cascode 302 comprises a further operational amplifier 303 and a further output transistor 304. The operational amplifier 303 of the active cascode 302 may act as a comparator and may compare the voltage at the power output driver transistor 306 to the voltage at the sensing transistor 305, and may accordingly drive the output transistor 304 of the active cascode 302. In this way, the active cascode 302 provides a partial indicator current iind at an indicator terminal 314 being proportional to the partial supply current isup at the supply terminal 313.
The ratio of the partial supply current isup at the supply terminal 313 and the partial indicator current iind at the terminal 314 may be given by a ratio of respective transistor widths W1 and W2 as
i
ind
=i
sup(W2/W1), (4)
W1 being the transistor width of the driver transistor 306 and W2 being the transistor width of the sensing transistor 305.
Taking into account the respective transistor widths W1 and W2, the indicator voltage may be deducted from
Vind=Isup×R×(W2/W1) (2a)
or
Vind=Vth×In(W2/W1+I/Is), (2b)
respectively, depending on whether a linear resistive shunt [Eq. (2a)] or a diode-like shunt [Eq. (2b)], is employed as a current-voltage-conversion element.
The active cascode 302 may furthermore regulate the drain-source voltage of the sensor transistor 305 to the value of the output voltage at the supply output 313. This may provide an optimized matching of the current mirror. The driver transistor 306 may be furthermore part of a linear voltage regulator. In this way, an output voltage Vo at the supply terminal 313 may be less than an input voltage Vi at the terminals 311 and 312, the output voltage being regulated on the basis of a supplied reference voltage 310. The voltage differential in such a regulator configuration then may determine the amount of power being dissipated as heat within the regulator or power generator and, in general, lost. This power may be calculated from the voltage differential to be
P=(isup+iind)×(Vi−Vo). (5)
Such a determination and setting of enabled and disabled modes of power generators may be executed continuously to allow for take into account changes and variations of the supply current and/or changes of an operation mode of the main circuit. Hence, the process may be led back from stage 403 to stage 401. Furthermore, the integrated circuit may continuously supervise the supplied current and may adapt the actually required power generators in this way. An optimized number of enabled power generators may hence be attained, and the integrated circuit may generate only the actually required current and, in this way, may minimize the required power supply and/or minimize the generation of excess heat. According to this embodiment, the actual power consumption of an integrated circuit or a main circuit thereof may be measured in real time and the required number of generators may be adapted dynamically.
According to this embodiment, the actually required supply current for the integrated circuit is sensed at a powering up 410 of the integrated circuit. Such a powering up 410 may be conducted when the integrated circuit is switched on, connected to a supply voltage, activated by an external circuit system, and/or by resuming the integrated circuit and the circuit system from a suspended mode. In this way, the integrated circuit may be operated with a minimum of required power generators. Furthermore, the actually required current and the required number of power generators may be determined upon each powering up 410 of the integrated circuit. In this way, variations in operation parameters, such as operation temperature, operation mode, and/or other parameters may determine a proper setting of the respective enabled and disabled modes of the power generators, since such variations may affect the actually required supply current.
The integrated circuit is optionally tested during a pretest stage 501. Such a pretest stage 501 may include optical or mechanical testing and inspection which may not require an actual connection to the integrated circuit. Furthermore the pretest stage 501 may comprise a connection to testing equipment and/or to electrical connections which may allow a powering up of the circuit in powering up stage 502.
Having powered up the integrated circuit, the actually provided supply current to the integrated circuit in the powered up state may be sensed during stage 503. Such a sensing may be carried out by means of internal sensing circuits of the integrated circuit and/or external sensing circuits of respective test equipment. An internally sensed current may be transmitted to test equipment by means of a conversion circuit and/or communication circuit.
Subsequently, the number of the required power generators is determined in stage 504. Accordingly a required number of power generators are enabled, whereas the remainder of the power generators, which are comprised by the integrated circuit, may be disabled in stage 505. Such an enabling and/or disabling of the power generators 505 may comprise a setting of switch elements of the integrated circuit and/or writing a value into a register of the integrated circuit. Such a register value may represent the respective enabled mode or disabled mode of each power generator. For example a binary number of M bits length may directly set the enabled/disabled modes of M power generators, the mth bit being “0”, for example, disabling the mth power generator and the mth bit being “1” enabling the mth power generator. A setting of a switch element may include a blowing of a fuse element, an application of a voltage pulse, a destruction of a conductor, or a destruction of a transistor gate. After an optional post-test stage 506, the integrated circuit may be released in stage 507.
According to this embodiment, a plurality of integrated circuits may be manufactured in an identical manner. However, process variations may result in a varying actual supply current of the integrated circuit. Such an actual supply current may be determined by the method according to this embodiment, this, for example, during a front-end test stage and/or a back-end test stage. Accordingly each integrated circuit may be manufactured comprising a minimum or excess number of power generators and then be tested and set such that only an actually required number of power generators is enabled, whereas the remainder of the power generators is disabled. In this way, the power consumption and the generation of excess heat within each integrated circuit may be minimized, since excess power generation within unrequired power generators is suppressed. This may provide an integrated circuit with an increased performance, an increased reliability, an improved buffer capacity of the circuit's supply circuit, an optimized power consumption, an enhanced lifetime, a broader applicability, for example, in mobile applications, and/or an enhanced environmental friendliness. Such applications may then provide an improved reliability and/or an enhanced battery run time.
The preceding description only describes exemplary embodiments of the invention. The features disclosed therein and the claims and the drawings can, therefore, be important for the realization of the invention in its various embodiments, both individually and in any combination. While the forgoing is directed to the embodiments of the present invention, other and further embodiments of this invention may be devised without departing from the basic scope of the invention, the scope of the present invention being determined by the claims that follow.
