1. Field of the Invention
This invention relates to the field of integrated circuits. More particularly, this invention relates to integrated circuits which use power gating so as to reduce power consumption of the integrated circuit.
2. Description of the Prior Art
Power gating is a known and effective technique for mitigating leakage power over long idle periods in integrated circuit designs. Functional state may be restored through a reset or otherwise after power up. A disadvantage that limits the usefulness of such power gating is that powering up after the power gating can have a large energy cost. There are a number of reasons for this large energy cost including the large power grid capacitance that must be slowly recharged, gated logic suffering crowbar currents until the virtual rail voltages reach approximately the transistor threshold voltages, and that logic values will be re-evaluated on power up drawing more dynamic power than after a functional mode clock event as switching activity is normally reduced by design during functional mode clocking.
Viewed from one aspect the present invention provides an integrated circuit comprising:
a main power rail;
a virtual main power rail connected to said main power rail by one or more first operational mode transistors and one or more first retention mode transistors;
a ground power rail;
a virtual ground power rail connected to said ground power rail by one or more second operational mode transistors and one or more second retention mode transistors;
combinatorial logic circuitry connected between said virtual main power rail and said virtual ground power rail;
signal value storage circuitry connected between one of:
power control circuitry coupled to and configured to control said one or more first operational mode transistors, said one or more first retention mode transistors, said one or more second operational mode transistors and said one or more second retention mode transistors such that:
The present technique serves to keep the voltage difference across the combinatorial logic circuitry higher than if full power gating is used such that there are reduced or no crowbar currents and reduced or no re-evaluation when the operational mode is re-entered. Furthermore, the amount of current required to recharge the power grid is also reduced. The leakage during the retention mode will be higher than during the power off mode, but the advantage of reduced energy cost on power up after retention mode is such that retention mode is worthwhile even if only used for short periods of time. This contrasts with the power off mode in which if the power off mode is only used for a short period of time, then the energy cost on power up may exceed the energy saved due to reduced leakage during a short duration in which the integrated circuit is in the power off mode. The configuration of the one or more first retention mode transistors and the one or more second retention mode transistors are such that when these are in their low impedance state they provide a low power voltage difference insufficient to support data processing operations across the combinatorial logic and a retention voltage difference greater than the low power voltage difference and sufficient to support signal value retention across the signal value storage circuitry. The combinatorial logic draws its power from the virtual rails. The signal value storage circuitry draws its power between one of the main power rail and the ground power rail and the corresponding other virtual rail. In this way, the retention voltage difference across the signal value storage circuitry is higher than the voltage difference across the combinatorial logic circuitry. The signal value storage circuitry is thus able to retain signal values while the combinatorial logic circuitry is placed into a lower leakage state, but one which nevertheless reduces crowbar currents on power up and reduces the amount of energy needed to recharge the virtual rails.
A reliable way of achieving the required voltage drop across the one or more first retention mode transistors and the one or more second retention mode transistors during the retention mode is to arrange these to serve as controllable diodes, i.e. using N-type field effect transistors as the one or more first operational mode transistors connected to the virtual main power rail and using P-type field effect transistors as the one or more second retention mode transistors connected to the virtual ground power rail.
A good balance between reducing leakage in the combinatorial logic circuitry during the retention mode whilst permitting signal value retention within the signal value storage circuitry may be achieved in embodiments in which a voltage difference between said main power rail and said ground power rail is Vop Volts when Vop/3 is greater than or equal to (Vop−(Vtn+Vtp)).
The integration of the retention mode with the operational mode and the power off mode may be facilitated in embodiments in which a reset mode is provided during which the power control circuitry places into a high impedance state the one or more retention mode transistors which are supplying power to the signal value storage circuitry (which is placed in to a low power state) such that signal values are not retained within the signal value storage circuitry during the reset mode. Thus, the reset mode can place the integrated circuit into a substantially known state from which it may be powered up in a manner which can reduce energy cost by exploiting the known state in which the integrated circuit emerges from the reset mode to reduce switching and other energy consuming effects.
In order to support the higher power requirements during the operational mode, the operational mode transistors may be configured to have a greater drive strength than the retention mode transistors.
In order that any signals passed from the combinatorial logic circuitry to the signal value storage circuitry during the retention mode do not compromise signal value storage within the signal value storage circuitry, some embodiments may include an isolation gate located in such a signal path and switched to output a predetermined signal value when in the retention mode.
As discussed above, one way of controlling the voltage drop across the retention mode transistors is to configure these to serve as controllable diodes.
Another technique which may be used in combination with the above and which may also be applied to the operational mode transistors is to pulse width modulate the gate voltages applied to these transistors so as to control their average drive strength and voltage drop.
One example of such a use is if the voltage difference between the main power rail and the ground power rail is reduced due to voltage scaling, then the gate voltages of the retention mode transistors may be pulse width modulated so as to provide a reduced voltage drop thereby permitting appropriate voltage differences to be maintained across the combinatorial logic circuitry and the signal value storage circuitry during the retention mode.
As previously mentioned, the retention mode can be considered to provide an intermediate state between the operational mode and the power off mode. The power off mode will provide greater power savings if it is maintained for a sufficient period. It is difficult to predict how long an integrated circuit may remain idle. One simple and effective way of controlling the entry into the power off mode is that the power control circuitry should first switch the integrated circuit into the retention mode and then switch from the retention mode to the power off mode after a predetermined number of clock cycles have elapsed without any trigger to return to the operational mode.
Viewed from another aspect the present invention provides an integrated circuit comprising:
main power rail means for providing a main power voltage;
virtual main power rail means for providing a virtual main power voltage and connected to said main power rail means by one or more first operational mode transistor means for selectively conducting and one or more first retention mode transistor means for selectively conducting;
ground power rail means for providing a ground power voltage;
virtual ground power rail means for providing a virtual ground power voltage and connected to said ground power rail means by one or more second operational mode transistor means for selectively conducting and one or more second retention mode transistor means for selectively conducting;
combinatorial logic means for performing processing operations and connected between said virtual main power rail means and said virtual ground power rail means;
signal value storage means for storing a signal value and connected between one of:
power control means for controlling power and coupled to and configured to control said one or more first operational mode transistor means, said one or more first retention mode transistor means, said one or more second operational mode transistor means and said one or more second retention mode transistor means such that:
Viewed from a further aspect the present invention provides a method of operating an integrated circuit having:
a main power rail;
a virtual main power rail connected to said main power rail by one or more first operational mode transistors and one or more first retention mode transistors;
a ground power rail;
a virtual ground power rail connected to said ground power rail by one or more second operational mode transistors and one or more second retention mode transistors;
combinatorial logic circuitry connected between said virtual main power rail and said virtual ground power rail;
signal value storage circuitry connected between one of:
It will be appreciated that an integrated circuit of the form discussed above may be formed using a standard cell library to control a computer to form layout data for controlling manufacture of that integrated circuit. The standard cell library will include standard cells of the type needed to produce the various power rail connections, operational mode transistors, retention mode transistors, combinatorial logic circuitry connected to the virtual rails, and signal value storage circuitry connected to one virtual rail and one of the main power rail or ground power rail. An aspect of the present invention is a computer readable storage medium storing in non-transitory form such a standard cell library adapted to provide an integrated circuit as described above.
The above, and other objects, features and advantages of this invention will be apparent from the following detailed description of illustrative embodiments which is to be read in connection with the accompanying drawings.
The signal value storage circuitry 16 serves to store one or more signal values under control of the clock signal clk. An isolation gate 18 in the form of an AND gate is disposed in the signal path between a signal output from the combinatorial logic circuitry 14 and an input to the signal value storage circuitry 16. This isolation gate 18 is controlled by an isolation signal niso generated by a power controller 20 when the system is in a retention mode of operation to block the signal path and to output a predetermined signal value and so reduce the likelihood of any signal values stored within the signal value storage circuitry 16 being perturbed by a signal received from the combinatorial logic circuitry 14 when this is in its retention mode state and there is a likelihood that signal value is output therefrom may inappropriately change.
The virtual main power rail 8 is connected via a first operational mode transistor 22 and a first retention mode transistor 24 to the main power rail 6. The first operational mode transistor 22 is a P-type field effect transistor. The first retention mode transistor 24 is an N-type field effect transistor. The drive strength of the first operational mode transistor 22 is greater than the drive strength of the first retention mode transistor 24 (this may be achieved by varying the transistor dimensions). The use of an N-type field effect transistor to serve as the first retention mode transistor 24 has the effect that when the first retention mode transistor 24 is in its low impedance state there is a voltage drop approximately equivalent to the threshold voltage Vtn of the first retention mode transistor 24 established between the main power rail 6 and the virtual power rail 8. In this state of operation (retention mode), the first operational mode transistor 22 is switched into its high impedance state. The switching of the various power control transistors illustrated in
The virtual ground power rail 10 is connected to the ground power rail 12 via a second operational mode transistor 26 and a second retention mode transistor 28. The second operational mode transistor 26 is an N-type field effect transistor. The second retention mode transistor 28 is a P-type field effect transistor. The use of a P-type field effect transistor as the second retention mode transistor 28 serves to provide a diode type voltage drop of Vpt across the second retention mode transistor 28 when operating in the retention mode with the second retention mode transistor 28 in its low impedance state and the second operational mode transistor 26 in its high impedance state. The drive strength of the second operational mode transistor 26 is greater than that of the second retention mode transistor 28.
If the voltage difference between the ground power rail 12 and the main power rail 6 is Vop, then the threshold voltages Ven, Vep of the first retention mode transistor 24 and the second retention mode transistor 28 may be chosen such that Vop/3 is greater than or equal to (Vop−(Vtn+Vtp)). Thus, during the retention mode the voltage between the virtual main power rail 8 and the virtual ground power rail 10 may be maintained at a level that is less than or equal to a third of the operational voltage Vop used during operational mode.
As the signal value storage circuitry is connected in this example embodiment between the main power rail 6 and the virtual power rail 10 then the voltage difference across the signal value storage circuitry 16 during the retention mode will be Vop−Vtp. This is a retention voltage difference and is greater than the voltage difference across the combinatorial logic circuitry 14 during the retention mode which is lower and may be considered to be a low power voltage difference. The leakage current through the combinatorial logic circuitry 14 during the retention mode will be lower due the smaller magnitude of the low power voltage difference, but should be sufficient to avoid large crowbar currents when the combinatorial logic is powered up as many signal levels will be maintained and to avoid an excessive energy consumption in recharging the virtual main power rail 8 and the virtual ground power rail 10. The retention voltage difference across the signal value storage circuitry 16 during the retention mode is sufficient to ensure that signal values within the signal value storage circuitry 16 are properly retained such that upon exiting the retention mode no data has been lost and processing may resume.
The low power voltage difference across the combinatorial logic circuitry 14 may be sufficient for many signal values within the combinatorial logic circuitry 14 to be retained, but if some of these signal values do change then they will be re-evaluated when the combinatorial logic circuitry 14 is powered up and the operational mode is resumed. The isolation gate 18 serves to ensure that the signal value storage circuitry 16 is protected from any changes in signal outputs from the combinatorial logic circuitry 14 that do occur during the retention mode.
It will be appreciated that in
It will further be appreciated that in this example embodiment the signal value storage circuitry is illustrated as drawing its power supply from the main power rail 6 and the virtual ground power rail 10. In other embodiments it is equally possible that the signal value storage circuitry 16 could draw its power from the virtual main power rail 8 and the ground power rail 12.
During the retention mode, the combinatorial logic circuitry 14 and the signal value storage circuitry 16 are not clocked. The isolation gate 18 is in its high impedance state and blocks the signal path between the combinatorial logic circuitry 14 and the signal value storage circuitry 16. The signal value storage circuitry 16 retains signal values during the retention mode.
The power controller 20 produces the gate signals supplied to the first operational mode transistor 22, the first retention mode transistor 24, the second operational mode transistor 26 and the second retention mode transistor 28. It is possible that these gate signals may be pulsed width modulated in order to provide a level of impedance through the respective transistors which is intermediate between their high impedance state and their low impedance state. This may be useful, for example, if the voltage difference between the main power rail 6 and the ground power rail 12 is increased (e.g. due to voltage scaling) and it is desired to produce more voltage drop across the first retention mode transistor 24 and the second retention mode transistor 28 during the retention mode. Another possibility is pulse width modulating the gate voltages of at least one of the first operational mode transistor 22 and the second operational mode transistor 26 to provide a reduced voltage difference between the main power rail 6 and the ground power rail 12 as part of voltage scaling.
In a reset mode of operation the second retention mode transistor 28 may be switched to its high impedance state thereby isolating the signal value storage circuitry 16 from the ground power rail 12 and resetting the signal value storage circuitry 16 such that it no longer retains any previously held signal values. This places the circuitry into a known state from which it may be powered up at reduced energy cost.
If the determination at step 30 is that the system is not in operational mode, then step 38 determines whether or not the system is the retention mode. If the system is in the retention mode, then step 40 switches off the operational mode header and footer transistors 22, 26 and switches on the retention mode header and footer transistors 24, 28. Step 42 asserts the isolation signal to the isolation gate 18 such that the signal path between the combinatorial logic circuitry 14 and the signal value storage circuitry 16 is blocked. At step 44 the clock signals to the combinatorial logic circuitry 14 and the signal value storage circuitry 16 are blocked such that these are not clocked. The combinatorial logic circuitry accordingly does not perform any processing operations, but the signal value storage circuitry 16 will continue to retain any previously held signal values.
If the determination at step 38 is that the system is not the retention mode, then the system is in the power off mode and processing proceeds to step 46 where all of the operational and retention mode header and footer transistors 22, 24, 26, 28 are switched off Step 48 then serves to block the clocking of the combinatorial logic circuitry and of the signal value saving circuitry as well as asserting the reset signal as appropriate to ensure that the circuitry will emerge from the power off state in a known condition in which any previously stored signal values have been overwritten.
Although illustrative embodiments of the invention have been described in detail herein with reference to the accompanying drawings, it is to be understood that the invention is not limited to those precise embodiments, and that various changes and modifications can be effected therein by one skilled in the art without departing from the scope and spirit of the invention as defined by the appended claims.
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Number | Date | Country | |
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20120326772 A1 | Dec 2012 | US |