The present disclosure is related to integrated circuits and power management in integrated circuits.
Battery powered electronic devices incorporating integrated circuits such as System-On-Chip (SOC) integrated circuits incorporate various power modes for saving power during times when the electronic device is idle. For example, electronic devices such as mobile telecommunication devices are normally kept powered on at all times in order to receive incoming phone calls and thus may go for many minutes or hours without usage. An operating software or other similar software on the device may monitor activity of the device and/or employ timers such that various idle states result in the device switching into reduced power modes.
Integrated circuit technology has developed various techniques for reducing power consumption by the integrated circuit, therefore saving power consumption for an electronic device overall. On such technique employs an architecture having “power islands” where some functions may be isolated from others. For example, a CPU may be located on its own power island so that other surrounding power islands may be placed in sleep modes, or shutdown, without effecting the CPU.
As would be understood, at least one power island must be “always-on,” that is, powered-on so that when the integrated circuit switches to a waking state, normally based on some detected event, a context may be provided to restore the operating system, and/or other software and logic, to their respective operating states prior to entering the sleep mode and, at least temporarily, halting operations. In order to accomplish this task, context information must be stored during the sleep state and must be retrievable at the wake-up event. The storage and access control of such information, and also its restoration requires power, which is a limitation on how “deep” of a sleep (“deep sleep”) an integrated circuit may enter without having to entertain a complete reboot, thereby losing any operational context prior to the sleep state.
Therefore, it would be desirable to have a way to maintain context information and place as many power islands into sleep mode as possible.
An embodiment herein disclosed provides a method comprising determining that a minimum operation level of an integrated circuit has been reached and that a sleep mode is therefore allowable; storing minimum operation context information to a random access memory (RAM) in response to determining that the minimum operation level has been reached; switching to a sleep mode code in the RAM; and transferring memory control from a primary memory controller to a secondary memory controller wherein the secondary memory controller only controls the RAM.
The method may include storing the sleep mode code and a wakeup code to the RAM in response to determining that the minimum operation level has been reached, where the wakeup code is operative to restore a minimum operation context using the minimum operation context information stored in the RAM. The method may also include placing a plurality of integrated circuit power islands into a powered off mode and leaving a secondary memory controller power island in a normal power mode. The secondary memory controller power island may also be placed in a low power mode wherein the applied power is lowered and clocks are turned off or reduced. A wakeup event may restore the clocks.
In another embodiment herein disclosed, a method includes receiving a hardware interrupt in an integrated circuit, when the integrated circuit is in a sleep mode; receiving a request to wakeup the integrated circuit in response to receiving the hardware interrupt; accessing, by the secondary memory controller, a wakeup code, the wakeup code stored in a RAM and for restoring a minimum operation context of the integrated circuit; executing the wakeup code and restoring a minimum operation context of the integrated circuit; and transferring memory control from the secondary memory controller to a primary memory controller.
The method may also include, prior to transferring memory control from the secondary memory controller to a primary memory controller, restoring power to a primary memory controller power island of the integrated circuit; and restoring a full operation context of the integrated circuit using a full operation context information stored in the RAM.
The embodiments also include an integrated circuit with a random access memory (RAM); a primary memory controller operatively coupled to the RAM and to other memory of the integrated circuit, where the primary memory controller is located on a memory controller island of a plurality of circuit islands; a secondary memory controller operatively coupled to the RAM and located on a secondary memory controller island, the secondary memory controller dedicated to control of the RAM upon transfer of control from the primary memory controller, and operative to provide access to a minimum operation context information from the RAM during a wakeup operation; and logic operative to transfer control from the primary memory controller to the secondary memory controller for entering a sleep mode of the integrated circuit which includes placing the memory controller island into sleep mode.
The integrated circuit of the embodiments may also include a processor operatively coupled to the RAM, the primary memory controller and the secondary memory controller, and operative to determine that a minimum operation level of an integrated circuit has been reached and that a sleep mode is therefore allowable; store minimum operation context information to the RAM in response to determining that the minimum operation level has been reached; switch to a sleep mode code in the RAM; and hand memory control from the primary memory controller to the secondary memory controller.
Turning now to the drawings wherein like numerals represent like components,
The secondary memory controller island 109 includes the secondary memory controller 112, an energy controller 110, and a display controller 111. The secondary memory controller 112 is operatively coupled to an on-die random access memory (RAM) 115 and may control the on-die random access memory 115 for occasions when the integrated circuit 100 enters into a sleep mode. The on-die random access memory (RAM) 115 further includes a sleep mode code 116 and a wake up code 117 as will also be described further herein. The sleep mode code 116 and wakeup code 117 may only be present in RAM 115 when needed to enter sleep mode. Lastly, as shown in
It is to be understood that
The various circuit islands illustrated in
The secondary memory controller 112 provides, among other advantages, a benefit in that it may be smaller and less complex than the primary memory controller 104. For example, by having access only to static RAM, such as on-die RAM 115, and not dynamic RAM such as DDR RAM 125, the secondary memory controller 112 need not include complex DDR interface logic. Further, a reduced number of clients are allowed access to the secondary memory controller 112, (i.e. no access by DSC, video, audio, etc.) resulting in even less complexity and size. Thus, the smaller size of the secondary memory controller 112, versus the size of the primary memory controller 104, provides an advantage in lower current leakage in a suspend mode, and lower power consumption in active mode, when compared to that of the primary memory controller 104.
An external memory such as the DDR RAM 125 may be controlled and placed in a self-refresh mode, when various circuit islands of integrated circuit 100 are in a sleep mode, in order to save additional power. Likewise, various logic of, for example, the input/output module 101, may also be powered off at various times in order to conserve power. For example, in some embodiments, a USB physical port and/or other ports, may be controlled to advantageously be turned off at opportune times, thereby conserving power.
In order for the integrated circuit 100 to determine when to enter a standby 209 or suspend state 205 from the normal operating state 203, the integrated circuit must have a triggering event. For example, an operating system executing on the CPU of CPU island 113 may monitor activity of the integrated circuit 100, and, if activity is low, take appropriate action to enter a suspend state 205 thereby saving power. Likewise, a wake up event of the integrated circuit 100 may trigger the CPU of CPU island 113 to enter the transitory slow state 207, and, ultimately, the normal operation state 203, thereby waking from the sleep mode or suspend state 205. Various events may trigger the integrated circuit 100 wake up such as an input occurring at the input/output module 101. Various other events would be understood by one of ordinary skill.
As shown in 307, the OS executing on the CPU of CPU island 113, may store a sleep mode code and a wake up code in response to determining that the minimum operation level has been reached. The sleep mode code and wake up code will be stored on the on-die RAM 115, as shown in
In 613, the secondary memory controller 112 returns control to the primary memory controller 104. This may be initiated by the CPU, or, in some embodiments, via the energy controller 110, automatically. The primary memory controller 104 may then take the DDR RAM 125 and other memory out of self refresh mode as shown in 615. Finally, as shown in 617, control is handed back to the operating system.
Initially, the operating system is running on the CPU and is the software on CPU 113. The software or operating system must decide that it is acceptable for the integrated circuit 100 to enter into a sleep mode. Once this happens, a context save may be made, for example, to the DDR RAM 125. This is illustrated in
The sleep mode code 116, now running as the software on the CPU 113, may send a message 713 to the energy controller 110, which in turn sends message 714 to the primary memory controller 104, to instruct the primary memory controller 104 to transfer control to the secondary memory controller. In response to message 714, the primary memory controller may also place a memory, such as DDR RAM 125, into a self-refresh mode. The DDR RAM 125 stores the full context of the integrated circuit 100, and the entire OS image, in the example illustrated by
In some embodiments, the sleep mode code 116 may cause the CPU, as shown by signal 715, to prepare to run the remainder of the sleep mode code from the CPU cache, due to the forthcoming change of memory to the self-refresh mode. However, using the CPU cache is not necessary in most embodiments, as the sleep mode code may be run entirely from the SRAM 115. At this point, the sleep mode code may send message 717 to the energy controller 110 instructing it to initiate the switch to the secondary memory controller 109. Handshaking 719 may occur between the primary memory controller 104 and the energy controller 110, prior to transitioning to the secondary memory controller 112. The primary memory controller 104 may then place the DDR RAM 125 in a self-refresh mode by a signal 721. The sleep mode code 116 executing on the CPU, may poll the secondary memory controller for activity by a message 723. When the secondary memory controller is active, it may respond via the energy controller 110 and message 725. The sleep mode code 116 running on the CPU 113 may communicate further with the energy controller 110 via various messages, such as, but not limited to, message 727, which may program the energy controller 110 such that various indexes correspond to various power modes of the circuit islands of integrated circuit 100. The sleep mode code 116 may send a message to the memory controller 114, such as message 729, to set it up so that a CPU reset vector points to the wakeup code 117. If possible, the sleep mode code may send message 731 to the secondary memory controller 112, to power down various portions of the random access memory, if possible. The software may then perform clock management via clock management messages 733 to the energy controller 110, and instruct the energy controller 110 to power down the primary memory controller 103 via message 735. In response, the energy controller 110 may send message 737 to the primary memory controller 103, causing it to be power gated. Further, the energy controller 110 may power gate the CPU 113 as shown by signal 739, and may turn off clocking to the secondary memory controller island 109 via signal 741.
As shown by signal 811, the CPU 113 may transfer to, or “jump to,” the wakeup code 117 stored in the RAM 115. The wakeup code 117 running on the CPU 113 from the SRAM 115, may now send the instruction 813 to the energy controller 110 instructing it to wakeup the primary memory controller 104 via the primary memory controller island 103 and message 815. The wakeup code 117, running on the CPU 113, may retrieve context information via operation 817, the context information being stored on the on-die RAM 115, and place it into the CPU cache. However, for most embodiments the wakeup code 117 will be run entirely from the on-die RAM 115. The CPU may then run the code from the on-die RAM 115, or the cache in some embodiments, while the transfer from the secondary memory controller 112 to the primary memory controller 104 is occurring. The wakeup code 117 may send instruction 819 to the energy controller 110 requesting a transition back to the primary memory controller 104. Handshaking 821 may then occur between the primary memory controller 104 and the energy controller 110. Further, the primary memory controller 104 may take the DDR RAM 125 out of self-refresh mode via instruction 823. The wakeup code 117, running on the CPU 113, may then poll the energy controller 110, as shown by message 825, to check whether the primary memory controller 104 is active. The energy controller 110 may send a response message 827 to the CPU indicating that the primary memory controller 104 has now become active again. The CPU 113 may then jump to the restoration code, that is, the overall context information, stored in the DDR RAM 125 as shown by 829. The CPU may then perform various cleanup operations such as CPU reset vector remapping (to undo the set up from message 729 which set the CPU reset vector to point to the wakeup code 117), as shown by signal 831, and restoring clock frequencies via signal 833. Lastly, the operating system takes over as shown by 835, and the wakeup event is handled by the operating system as shown by signal 837.
In accordance with the various embodiments herein disclosed, the operating system, running for example on the CPU of CPU island 113, performs the sleep mode and wakeup mode operations transparently. That is, the operating system has no awareness of the operations taking place during the sleep mode and wakeup mode operations. The operating system only has awareness that a sleep event and wakeup event have occurred. In accordance with the embodiments, although various circuit islands of the integrated circuit 100 are placed into a sleep mode or suspended, including the primary memory controller circuit island 103, the full operating context of the integrated circuit 100 is restored upon a wakeup event. Various applications of the various embodiments may occur to one in ordinary skill. For example, an audio application via audio processor 107 on the primary memory controller island 103 may be operating. In such a scenario, the CPU island 113 may be shut down with no adverse effects to the audio thereby providing a low power audio playback mode. Various other possibilities will be apparent to those of ordinary skill.
In the exemplary embodiments herein described, the sleep mode code 116 and wakeup code 117 were exemplified as software codes stored in on-die RAM 115. However, other embodiments may include logic operative to perform the sleep mode and wakeup mode operations herein disclosed and remain in accordance with the embodiments. Further other embodiments may include a combination of software code such as sleep mode code 116 and wakeup code 117, stored in the on-die RAM 115, in combination with various logic located on the integrated circuit 100. For example, such logic may be included on the secondary memory controller island 109 along with the secondary memory controller 112. For the exemplary embodiments disclosed herein, and with respect to the integrated circuit 100 example illustrated in
As used herein, the term CPU or “processor” may refer to one or more dedicated or non-dedicated: microprocessors, microcontrollers, sequencers, microsequencers, digital signal processors, processing engines, hardware accelerators (e.g., GPUs), application specific circuits (ASICs), state machines, programmable logic arrays, and/or any single or collection of circuit components that is or are capable of processing data or information, and any combination of the above. Similarly, “memory” may refer to any suitable volatile or non-volatile memory, memory device, chip or circuit, or any storage device, chip or circuit such as, but not limited to, system memory, frame buffer memory, flash memory, random access memory (RAM), read only memory (ROM), a register, a latch, or any combination of the above. For the avoidance of doubt “logic” may refer to any electric circuitry or circuit components (whether on one or more circuits or integrated circuits) such as but not limited to processors (capable of executing executable instructions), transistors, electronic circuitry, memory, combination logic circuit, or any combination of the above that is capable of providing a desired operation(s) or function(s). The term “integrated circuit” may be used interchangeably to designate both a circuit in its totality (e.g., a chip) and a partial section of the same. A “signal” may refer to any suitable data, information or indicator. Additionally, as will be appreciated by those of ordinary skill in the art, the operation, design, and organization, of a “module” or processor can be described in a hardware description language such as Verilog™, VHDL, or other suitable hardware description languages, such hardware description language code or instructions being capable of being stored on a computer readable medium.
The above detailed description and the examples described therein have been presented for the purposes of illustration and description only and not for limitation. For example, the operations described may be done in any suitable manner. The method steps may be done in any suitable order still providing the described operation end results. It is therefore contemplated that the present embodiments cover any and all modifications, variations or equivalents that fall within the spirit and scope of the basic underlying principles disclosed above and claimed herein.