Patent Application
20150116013
This application claims the benefit of Korean Patent Application No. 10-2013-0131615 filed on Oct. 31, 2013, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference.
The present disclosure relates to an integrated circuit capable of controlling a power supply.
In general, electronic apparatuses use a power supply for a supply of driving power in order to implement operations thereof.
Such a power supply mainly uses a power factor correction apparatus and a direct current to direct current (DC/DC) converter.
The power factor correction apparatus serves to allow a power factor, a performance index related to a phase difference between a voltage and a current of input power and distortion of the current, to be close to 100%.
In the case in which the power factor is 100%, the voltage and the current have the same phase and the current is not distorted. Accordingly, a load is operated as a pure resistive load, such that only active power is used.
In this case, a power supply only needs to supply active power to actually be used, and does not need to supply reactive power which will not be used. Therefore, there is no waste in the supplying of power, resulting in an increase in efficiency.
Accordingly, a general power supply may achieve a high power factor by using a power factor correction apparatus.
A DC/DC converter may switch DC power input to an electronic apparatus to provide DC power having a voltage level appropriate for the driving thereof.
The power supply described above needs to sense an input voltage.
An aspect of the present disclosure may provide an integrated circuit capable of sensing an input voltage using an HV pin and a drain pin.
An aspect of the present disclosure may also provide an integrated circuit capable of reducing manufacturing costs by omitting a separate voltage sensing pin.
According to an aspect of the present disclosure, an integrated circuit controlling a power supply may include: an HV pin obtaining startup power; a voltage dividing unit connected to the HV pin; and an input voltage detecting unit detecting an input voltage through voltage distribution by the voltage dividing unit.
The voltage dividing unit may include a plurality of resistors connected to each other in series.
The integrated circuit may further include a VDD pin transferring the startup power obtained by the HV pin to a capacitor.
The integrated circuit may further include: a startup switch interrupting a connection between the HV pin and the VDD pin; and a startup controlling unit controlling the startup switch.
The integrated circuit may further include a detecting switch interrupting a connection between the HV pin and the voltage dividing unit.
The startup switch may include a junction gate field-effect transistor (JFET); and the detecting switch may include the JFET.
According to another aspect of the present disclosure, an integrated circuit controlling a power supply may include: a drain pin obtaining startup power; a voltage dividing unit connected to the drain pin; and an input voltage detecting unit detecting an input voltage through voltage distribution by the voltage dividing unit.
The voltage dividing unit may include a plurality of resistors connected to each other in series.
The integrated circuit may further include a VDD pin transferring the startup power obtained by the drain pin to a capacitor.
The integrated circuit may further include: a startup switch interrupting a connection between the drain pin and the VDD pin; and a startup controlling unit controlling the startup switch.
The above and other aspects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:
Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.
The disclosure may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
Throughout the drawings, the same or like reference numerals will be used to designate the same or like elements.
A configuration of a power supply will hereinafter be described based on a flyback converter for convenience of explanation in the present specification.
However, it will be appreciated by those skilled in the art that a configuration according to an exemplary embodiment of the present disclosure may be applied to a forward converter, a half-bridge converter, a full-bridge converter, a push-full converter, a resonance type converter, or the like.
Referring to
The power input unit Vs may supply input power. The input power may be alternating current (AC) power.
The rectifying unit 10 may receive the AC power and rectify the received AC power to transfer the rectified AC power to the transformer T1.
The transformer T1 may have a primary winding Np and a secondary winding Ns, inductively coupled to the primary winding. Here, a region in which the primary winding Np is located may be defined as a primary side region and a region in which the secondary winding Ns is located may be defined as a secondary side region.
The switching element S1 may interrupt a primary current I1 flowing in the primary winding Np of the transformer.
The switching element S1 according to the exemplary embodiment of the present disclosure may be formed of one of an insulated gate bipolar transistor (IGBT), a metal oxide semiconductor field-effect transistor (MOS-FET) and a bipolar junction transistor (BJT).
Meanwhile, a rectifying diode D10 and a capacitor C10 for stabilizing power induced from the secondary winding Np may be located on the secondary side.
The rectifying diode may rectify a secondary current of the transformer T1.
The capacitor may stabilize power transferred from the rectifying diode.
Meanwhile, the flyback converter may further include an auxiliary winding NA. The auxiliary winding NA may be inductively coupled to the transformer T1. Therefore, in the case in which the power is induced to the primary winding Np and the secondary winding Ns, the power may also be induced to the auxiliary winding NA.
The power induced to the auxiliary winding NA may be provided to the integrated circuit 100 via the rectifying diode D10 and the stabilizing capacitor C10. For example, one terminal of the rectifying diode D10 may be coupled to a VDD pin of the integrated circuit, and the VDD pin may obtain the power induced from the auxiliary winding NA.
Meanwhile, the integrated circuit 100 may include an HV pin. The HV pin may charge the capacitor C10 connected to the VDD pin at the time of a startup. That is, since a case in which the integrated circuit is initially operated corresponds to an under voltage lock out (UVLO) situation, the capacitor C10 connected to the VDD pin may be charged and perform a startup operation.
Meanwhile, the integrated circuit 100 may include a startup switch S2 interrupting a connection between the HV pin and the VDD pin. In addition, the integrated circuit 100 may include a startup controlling unit 30 controlling the startup switch. For example, the startup controlling unit 30 may turn the startup switch S2 on at the time of the startup and turn the startup switch S2 off after the startup.
Meanwhile, in order for the integrated circuit 100 to control the flyback converter, the integrated circuit 100 may need to obtain input voltage information. Therefore, the integrated circuit may include a separate pin 40 for obtaining the input voltage information.
Referring to
The integrated circuit 100 may include a voltage sensing unit 20 for detecting the input voltage information and may detect the input voltage by the pin 40.
However, in this case, since the separate pin 40 for sensing the input voltage is required, manufacturing costs of the integrated circuit may be significantly increased.
In addition to the method described above, there is provided a method of sensing the input voltage information by a separate auxiliary winding without using the separate pin. However, in the case of the method of sensing the input voltage information using the auxiliary winding as described above, since a turn-on time in a burst mode is short, it may be difficult to accurately sense the input voltage information.
Referring to
The power input unit Vs may supply input power. The input power may be alternating current (AC) power.
The rectifying unit 10 may receive the AC power and rectify the received AC power to transfer the rectified AC power to the transformer T1.
The transformer T1 may have a primary winding Np and a secondary winding Ns, inductively coupled to the primary winding. Here, a region in which the primary winding Np is located may be defined as a primary side region and a region in which the secondary winding Ns is located may be defined as a secondary side region.
The switching element S1 may interrupt a primary current I1 flowing in the primary winding Np of the transformer.
The switching element S1 according to this exemplary embodiment of the present disclosure may be formed of one of an insulated gate bipolar transistor (IGBT), a metal oxide semiconductor field-effect transistor (MOS-FET) and a bipolar junction transistor (BJT).
Meanwhile, a rectifying diode D10 and a capacitor D10 for stabilizing power introduced from the secondary winding Np may be located on the secondary side.
The rectifying diode may rectify a secondary current of the transformer T1.
The capacitor element may stabilize power transferred from the rectifying diode.
Meanwhile, the flyback converter may further include an auxiliary winding NA. The auxiliary winding NA may be inductively coupled to the transformer T1. Therefore, in the case in which the power is induced to the primary winding Np and the secondary winding Ns, the power may also be induced to the auxiliary winding NA.
The power induced to the auxiliary winding NA may be provided to the integrated circuit 200 via the rectifying diode D10 and the stabilizing capacitor C10. For example, one terminal of the rectifying diode D10 may be coupled to a VDD pin of the integrated circuit, wherein the VDD pin may obtain the power induced from the auxiliary winding NA.
Meanwhile, the integrated circuit 200 may include an HV pin. The HV pin may charge the capacitor C10 connected to the VDD pin at the time of a startup. That is, since a case in which the IC is initially operated corresponds to an under voltage lock out (UVLO) situation, the capacitor C10 connected to the VDD pin may be charged and perform a startup operation.
Meanwhile, the integrated circuit 200 may include a startup switch S20 interrupting a connection between the HV pin and the VDD pin. In addition, the integrated circuit 200 may include a startup controlling unit 230 controlling the startup switch. For example, the startup controlling unit 230 may turn the startup switch S20 on at the time of the startup and turn the startup switch S20 off after the startup.
The startup switch S20 may include a junction gate field-effect transistor (JFET).
That is, the HV pin may obtain startup power. The power may be transferred to the VDD pin via the startup switch S20. The VDD pin may transfer the startup power obtained from the HV pin to the capacitor C10.
The integrated circuit 200 according to the exemplary embodiment of the present disclosure may obtain the input voltage information through the HV pin.
Referring to
Meanwhile, the integrated circuit 200 may further include an input voltage detecting unit 222. The input voltage detecting unit 222 may detect the input voltage information through voltage distribution by the voltage dividing unit.
Referring to
Voltage Detection Value=Vin*R2/(Rstart+R1+R2)
That is, the integrated circuit according to the exemplary embodiment of the present disclosure may obtain information of an input voltage Vin through the voltage detection value.
According to the exemplary embodiment of the present disclosure, the input voltage may be sensed by using the HV pin. Accordingly, a separate voltage sensing pin may be omitted, resulting in a reduction in manufacturing costs.
Since the power input unit Vs, the rectifying unit 10, the transformer T1, the auxiliary winding NA, the rectifying diode D10, and the stabilizing capacitor C10 have been described above, detailed descriptions thereof will be omitted.
Meanwhile, the integrated circuit 300 may include a switching element S1 therein. The switching element S1 may interrupt a primary current I1 flowing in the primary winding Np of the transformer, as described above.
The switching element S1 according to this exemplary embodiment of the present disclosure may be formed of one of an insulated gate bipolar transistor (IGBT), a metal oxide semiconductor field-effect transistor (MOS-FET) and a bipolar junction transistor (BJT).
The integrated circuit 300 according to the exemplary embodiment of the present disclosure may include a drain pin. The drain pin may be connected to one terminal of the primary winding Np of the transformer T1.
The integrated circuit 300 according the exemplary embodiment of the present disclosure may obtain input voltage information through the drain pin.
Referring to
Meanwhile, the integrated circuit 300 may further include an input voltage detecting unit 222. The input voltage detecting unit 222 may detect the input voltage information through voltage distribution by the voltage dividing unit.
Referring to
Therefore, the measured value of the point A and the measured value of the point B may be added and may be then divided by 2 to thereby produce the input voltage Vin.
Meanwhile, a relationship between the detection value obtained by the input voltage detecting unit 222 and the input voltage may be expressed by the following Equation:
Voltage Detection Value=(A+B)/2*R2/(Rstart+R1+R2)
That is, the integrated circuit according to the exemplary embodiment of the present disclosure may obtain information of the input voltage Vin through the voltage detection value.
According to the exemplary embodiment of the present disclosure, the input voltage may be sensed by using the drain pin. Accordingly, a separate voltage sensing pin may be omitted, resulting in a reduction in manufacturing costs.
Since the components of the integrated circuit except for a detecting switch S30 have been described in detail in the above-described embodiment of
The detecting switch S30 may interrupt a connection between the HV pin and the voltage dividing unit 220.
The detecting switch S30 may include a junction gate field-effect transistor (JFET).
The detecting switch S30 may be turned off at the time of the startup and may be turned on when the startup is terminated. An input voltage detecting unit 222 may not perform the voltage detection at the time of the startup and detect the input voltage when the startup is terminated.
According to this exemplary embodiment of the present disclosure, a leakage current at the time of the startup may be decreased.
Such a method may also be applied to the integrated circuit of
According to the present exemplary embodiment, a voltage dividing unit 220 may be connected between a startup switch S20 and a ground terminal GND.
In the case in which the startup switch S20 is formed of a JFET, since voltage is detected at a rear stage of the startup switch S20, values of resistors R1 and R2 may be decreased.
Such a method may also be applied to the integrated circuit of
As set forth above, according to exemplary embodiments of the present disclosure, an integrated circuit capable of sensing input voltage using an HV pin and a drain pin may be provided.
In addition, according to exemplary embodiments of the present disclosure, an integrated circuit capable of reducing manufacturing costs by omitting a separate voltage sensing pin may be provided.
While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations could be made without departing from the spirit and scope of the present disclosure as defined by the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2013-0131615 | Oct 2013 | KR | national |
