Patent Application
20140049330
This application claims priority under 35 U.S.C. §119 or 365 to European Patent Application No. EP12180373.8 filed Aug. 14, 2012. The entire teachings of the above application are incorporated herein by reference.
For many years oscillators in which the frequency is dependent on LC resonance have been known. Although it would be possible to vary or control the frequency of such an oscillator by varying the inductance of the resonant circuit, this is not convenient where the circuitry forming the oscillator is integrated.
In one aspect there is disclosed an integrated circuit device having an LC tank circuit for frequency setting, and a switched capacitor circuit for tuning the resonant frequency of the LC tank, characterized in that the switched capacitor circuit has plural sets of parallel branches, each set comprising a first branch and a second branch, the first and second branches each connecting between a first node and a second node, each branch containing a respective capacitor in series with a switch, the switched capacitor circuit being configured such that, in use, the switch of the first branch is on when the switch of the second branch is off and vice versa.
The integrated circuit device is, in an embodiment, a differential oscillator.
In another embodiment it is a single-ended oscillator. In yet another embodiment it is an LC filter.
In a further aspect there is disclosed an integrated circuit device having an RC circuit, and a switched capacitor circuit for controlling the time constant of the RC circuit, characterized in that the switched capacitor circuit has plural sets of parallel branches, each set comprising a first branch and a second branch, the first and second branches each connecting between a first node and a second node, each branch containing a respective capacitor in series with a switch, the switched capacitor circuit being configured such that, in use, the switch of the first branch is on when the switch of the second branch is off and vice versa.
Each set may comprise a pair of branches, and in each pair the capacitor of the second branch may have a capacitance that differs from that of the capacitor of the first branch by an amount defined as a step size, and in one pair the step size is less than the other step sizes.
In that one pair the step size may be a capacitance equal to or less than the capacitance of a capacitor having the minimum feature size of the process by which the integrated circuit was formed.
The capacitor of each first branch may have identical capacitance.
In each set the second branch capacitor may have a capacitance that differs from that of the first branch capacitor by an amount defined as a step size, wherein the step size of each stage is different.
In each set the second branch capacitor may have a capacitance that differs from that of the first branch capacitor by an amount defined as a step size, and in one set the step size may be less than the other step sizes. Then the step size of each remaining set may be a multiple of two times that step size.
There is also disclosed a method of tuning the resonant frequency of an integrated LC tank circuit for frequency determination, the method adjusting a capacitance of the LC tank by selecting a respective first or a respective second branch in each of plural pairs of parallel branches.
There is also disclosed a method of controlling the time constant of an integrated RC circuit, the method adjusting a capacitance of the RC circuit by selecting a respective first or a respective second branch in each of plural pairs of parallel branches.
In each method, each pair of parallel branches may consist of a first branch with a first capacitor and a respective second branch with a second capacitor, the arrangement being that selecting a respective branch connects the respective capacitor in circuit.
In each pair of parallel branches, the respective second capacitor may have a capacitance that differs from that of the first capacitor by an amount defined as a step size, and in one stage the step size is less than the other step sizes.
In one embodiment, all of the first capacitors have the same first capacitance.
In one embodiment, the second capacitors have mutually different values of capacitance.
The foregoing will be apparent from the following more particular description of example embodiments of the invention, as illustrated in the accompanying drawings in which like reference characters refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating embodiments of the present invention.
A description of example embodiments of the invention follows.
As is well known to those skilled in the art, the frequency of oscillation is determined by the resonance of the tank circuit formed by the first and second variable capacitors (16,18) and inductances (22,24). If the inductances are equal, and have a value of L1 and the capacitances the same as one another and have a value of C1, then
Fo≈1/(2 π)*[L1*C1]1/2
Hence by choosing the value of C1 the frequency may be selected. By varying it, the frequency is varied.
In use, the common node (56) is connected for example, to the oscillator of
Variation is achieved using the bus (31). When only the first MOST (42) is controlled from the bus to be on, the capacitance between common node (56) and earth (41) has value C2. When only the second MOST (42) is turned on, the capacitance between common node (56) and earth (41) has value 2*C2 and so on. By rendering two or more MOSTs in the “on” state, intervening capacitance levels may be achieved. For example, for 3*C2 both first and second MOSTs (42,43) are “on”.
In one oscillator, the circuit of
In some oscillators, for example voltage controlled oscillators used in RF communications systems, fine resolution of frequency is essential. To achieve this using switched capacitors is hard. The smallest capacitor used in the switched capacitor array limits the resolution of the VCO frequency steps. Also, these steps must be smaller than the voltage tuning range to ensure constant frequency coverage.
Achieving a very small and well controlled capacitance is difficult. In some applications a tiny unit capacitance of less than 5 fF is required.
The traditional approach to achieve tiny capacitors is to couple two or more, typically several, larger capacitors in series. However, this has some serious disadvantages since a number of larger capacitors occupies real estate on the chip, while at the same time creating problems due to parasitic effects (R, L & C).
In all integrated circuit technologies there is a practical limit to the smallest sized, well-controlled capacitor realizable, whichever device type is chosen.
The limit is generally caused by two factors:
1) Minimum allowed capacitor device structure geometry according to process design rules;
2) Parasitics R, L & C associated with including a transistor switch in series with the capacitor.
To illustrate the geometry limit, a typical 65 nm CMOS process may have a Metal-Insulator-Metal (MIM) type capacitor with a minimum physical size limit of 4 μm×4 μm, with a 2 fF/μm-2−2 femtofarads per square micron-capacitance density, giving a 32 fF minimum unit capacitor. This is large when compared to possible required vales of less than 5 fF.
As noted above, the minimum device size problem is often addressed by using plural capacitors in series. For example eight 32 fF capacitors in series would have a capacitance of 4 fF. Using this configuration the total capacitance can be adjusted to any arbitrary small value, but at the cost of large silicon area and high parasitic capacitance (C), resistance (R) and inductance (L). For very small capacitance values, this approach becomes impossible to use in practice, as the parasitics involved quickly dominate the desired capacitance values, and the silicon area used may be unacceptable.
Referring to
The single capacitors of
Each branch (111,113,115,117) has a respective pair of NMOS transistors (142,143;144,145;146,147;148,149), consisting of first transistors (142,144,146,148) and second transistor (143,145,147,149). Each branch also has a respective first capacitor (152,154,156,158) and a respective second capacitor (153,155, 157, 159).
The drain of each first transistor (142,144,146,148) is connected to the common node (56) via a respective first capacitor (152,154,156,158). The drain of each second transistor (143,145,147,149) is connected to the common node (56) via a respective second capacitor (153,155, 157, 159).
The gate of each first transistor (142,144,146,148) is connected to a respective conductor of the bus (31) via a respective inverter (131,133,135,137), and the gate of each second transistor (143,145,147,149) is connected to the like conductor of the bus (31) directly, i.e. without inversion.
In this embodiment all of the first capacitors (152,154,156,158) are of the same capacitance Ct. The second capacitor (153) of the first branch (111) has a value of Cs+Ct, where Cu is herein referred to as minimum step size and has a value smaller than the capacitance of the minimum capacitor size capable of being made using the fabrication process of the integrated circuit.
In the second branch, the second capacitor (155) has a value of [2*Cu]+Ct; in the third the second capacitor (157) has a value of [4*Cu]+Ct; in the third the second capacitor (159) has a value of [8*Cu]+Ct.
In operation, when the bus (31) has all four lines at logic 0, all the four first transistors (142,144,146,148) will be “on” and all the second transistors (143,145,147,149) will be “off”. Thus the capacitance between the common node (56) and ground will be [4*Ct].
If only the first branch is activated by turning on its second transistor (143), the first transistor (142) turns off due to the inverter (131) and the capacitance between the common node (56) and ground will be [4*Ct] +Cu.
If only the second branch is activated by turning on its second transistor (145), the first transistor (144) turns off due to the inverter (133) and the capacitance between the common node (56) and ground will be [4*Ct]+[2*Cu].
It will be seen therefore that whatever the bus state, the capacitance between the common node (56) and ground (41) will lie between [4*Ct] and [4*Ct]+[15*Cu].
This is a convenient embodiment, however the invention is not restricted to the details of the embodiment.
The proposed invention achieves an arbitrarily small LSB capacitor size, with lower area usage than using series combined capacitors, and does not have the draw back of excessive parasitic capacitance, resistance or inductance.
This technique is specifically suited where monotonicity of programmable C is needed, rather than bit-linearity, for example in calibrating a tuned LC element.
The described embodiment is a differential circuit, but the invention is not restricted to this and extends to single-ended oscillator circuits as well. Oscillators may be voltage-controlled.
Other embodiments include LC filters, RC filters and such other applications where fine control of capacitance is required in integrated circuit devices as would be known to the person of ordinary skill in the art.
While this invention has been particularly shown and described with references to example embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the invention encompassed by the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 12180373.8 | Aug 2012 | EP | regional |
