The present disclosure relates generally to the field of semiconductor integrated circuits, and more particularly, to integrated circuits with cascode transistors.
The semiconductor industry has experienced continual rapid growth due to continuous improvements in the integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from repeated reductions in minimum feature size, allowing for the integration of more components into a given area. The scale down of features of integrated circuits has been implemented in various applications, e.g., digital circuits, analog circuits, and mixed-signal circuits.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
In analog circuits, cascode technology is deployed to enhance electrical performances. In cascode technology, a cascode transistor is electrically coupled with a transistor in series. As the cascode transistor is operated as a diode having a low input resistance to the transistor, the voltage gain of the transistor becomes small, such that the bandwidth of the analog circuit is increased.
One cascode technique is to electrically connect a gate and a drain of the cascode transistor together. A gate and a drain of the transistor are electrically connected to each other. The gate of the cascode transistor is electrically isolated from the gate of the transistor. During the operation, the cascode transistor and the transistor are both operated in a saturation mode. In such a configuration, the supply voltage is designed to be larger than a sum of threshold voltages of the cascode transistor and the transistor. This configuration of the cascode transistor and the transistor makes the voltage headroom small.
Another cascode technique is to supply a bias voltage to the gate of the cascode transistor to enhance the voltage headroom. To provide a desired bias voltage, the bias circuit electrically coupled with the gate of the cascode transistor is complicated and may be difficult to design.
It is understood that the following disclosure provides many different embodiments, or examples, for implementing different features of various embodiments. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition of reference numerals indicates the same element contained in different embodiments and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Referring to
During an operation, the cascode transistor MC1 is operated in a saturation mode or a sub-threshold mode. The transistor M1 is operated in a saturation mode. By operating the cascode transistor M1 in a saturation mode or a sub-threshold mode, the voltage headroom between the drain of the cascode transistor M1 and a supply voltage becomes larger. Additionally, the gates of the cascode transistor MC1 and the transistor M1 are electrically coupled with the drain of the cascode transistor M1. No bias circuit is electrically coupled to a bulk of the cascode transistor MC1 and configured to provide a bias to adjust the operation mode of the cascode transistor MC1. As a result, the design of the integrated circuit 100 is simplified. The area that is assigned to accommodate the bias circuit is saved.
In some embodiments, the cascode transistor MC1 is operated in a sub-threshold mode, and the transistor M1 is operated in a saturation mode. To achieve the operation, the voltage differential (VGSC1) between the gate and the source of the cascode transistor MC1 is less than the threshold voltage (VTHC1) of the cascode transistor MC1. The threshold voltage (VTHC1) of the cascode transistor MC1 is less than the threshold voltage (VTH1) of the transistor M1. The relationship among the voltage differential VGSC1 and the threshold voltages VTHC1 and VTH1 can be shown as below:
VGSC1VTHC1<VTH1
In some embodiments, the threshold voltage (VTHC1) of the cascode transistor MC1 being less than the threshold voltage (VTH1) of the transistor M1 allows a channel length of the cascode transistor MC1 to be designed shorter than a channel length of the transistor M1. In some embodiments, a channel width of the cascode transistor MC1 is designed to be wider than a channel width of the transistor M1. In other embodiments, the cascode transistor MC1 is a native transistor and the transistor M1 is not a native transistor. For example, the threshold voltage (VTHC1) of the cascode transistor MC1 is around 0, and the threshold voltage (VTH1) of the transistor M1 is higher than 0. In still other embodiments, the cascode transistor M1 is a low threshold voltage (LVT) transistor or an ultra-low threshold voltage (ULVT) transistor. For example, the cascode transistor MC1 is an N-type LVT cascode transistor. The P-type dopant concentration in the channel region of the cascode transistor is lower than that of the transistor.
Referring to
As noted, the cascode transistor MC2 is operated in a saturation mode or a sub-threshold mode. The transistor M2 is operated in a saturation mode. By operating the cascode transistor MC2 in a saturation mode or a sub-threshold mode, the voltage headroom of the analog circuit 120 becomes larger. Additionally, the gates of the cascode transistor MC2 and the transistor M2 are electrically coupled with the drain of the cascode transistor MC2. No bias circuit is electrically coupled with and used to provide a bias to the bulk of the cascode transistor MC2 to adjust the operation mode of the cascode transistor MC2.
In some embodiments, the cascode transistor MC2 is operated in a sub-threshold mode, and the transistor M2 is operated in a saturation mode. To achieve the operation, the absolute value of the voltage differential (VGSC2) between the gate and the source of the cascode transistor MC2 is less than the absolute value of the threshold voltage (VTHC2) of the cascode transistor MC2. The absolute value of the threshold voltage (VTHC2) of the cascode transistor MC2 is less than the absolute value of the threshold voltage (VTH2) of the transistor M2. The relationship among the absolute values of the voltage differential VGSC2 and the threshold voltages VTHC2 and VTH2 is shown as below:
|V1GSC2|<V1THC2|<|V1TH2|
In some embodiments, the absolute value of the threshold voltage (VTHC2) of the cascode transistor MC2 being less than the absolute value of the threshold voltage (VTH2) of the transistor M2 allows a channel length of the cascode transistor MC2 to be designed shorter than a channel length of the transistor M2. In some embodiments, a channel width of the cascode transistor MC2 is designed to be wider than a channel width of the transistor M2. In some embodiments, the cascode transistor MC2 is a native transistor and the transistor M2 is not a native transistor. For example, the absolute value of the threshold voltage (VTHC2) of the cascode transistor MC2 is around 0, and the absolute value of the threshold voltage (VTH2) of the transistor M2 is higher than 0. In still some embodiments, the cascode transistor MC2 is a low threshold voltage (LVT) transistor or an ultra-low threshold voltage (ULVT) transistor. As noted, the cascode transistor MC2 is a P-type LVT transistor. The N-type dopant concentration in the channel region of the cascode transistor is lower than that of the transistor.
Referring to
As noted, the cascode transistor MC3 is operated in a saturation mode or a sub-threshold mode. The transistor M1 is operated in a saturation mode. To achieve the operation, the threshold voltage (VTHC3) of the cascode transistor MC3 is lower than the threshold voltage (VTH1) of the cascode transistor M1.
In
In some embodiments, the bias circuit 230 includes transistors M3 and M4 that are electrically coupled to each other in a series fashion. The transistor M3 is an N-type transistor and the transistor M4 is a P-type transistor. A gate and a drain of the transistor M3 are electrically coupled with a node N1 between the transistors M3 and M4. The node N1 is electrically coupled with a bulk or a well region of the cascode transistor MC3. A bulk and a source of the transistor M4 are electrically coupled to each other and with a supply voltage VDD. A gate of the transistor M4 is controlled by a bias voltage that is provided from a bias circuit (not shown).
Referring to
As noted, the cascode transistor MC4 is operated in a saturation mode or a sub-threshold mode. The transistor M2 is operated in a saturation mode. It can be achieved by controlling the threshold voltage (VTHC4) of the cascode transistor MC4 lower than the threshold voltage (VTH2) of the cascode transistor M2.
In
In some embodiments, the bias circuit 240 includes transistors M5 and M6 that are electrically coupled to each other in a series fashion. The transistors M5 and M6 are N-type transistors. A gate and a drain of the transistor M6 are electrically coupled to each other. A node N2 between the transistors M5 and M6 is electrically coupled with the N-type well region of the cascode transistor MC4. In some embodiments, a bulk and a source of the transistor M5 are electrically coupled with a bulk of the transistor M6. A gate of the transistor M5 is controlled by a bias voltage that is provided by a bias circuit (not shown).
Following are various exemplary analog circuits that include at least one cascode transistor described above in conjunction with
In some embodiments, gates of the cascode transistors MC301, MC302, and MC305 and the transistor M305 are electrically coupled with each other. Gates of the cascode transistors MC303, MC304, and MC306 and gates of the transistors M303, M304, and M306 are electrically coupled with each other. Bulks of the transistors M301 and M302 and the bulk of the cascode transistor MC302 are electrically coupled with the current source. Bulks of the transistors M303 and M304 are electrically coupled with the supply voltage VDD. A source and a bulk of the transistor M306 are electrically coupled with each other. A source and a bulk of the transistor M305 are electrically coupled with each other and electrically grounded.
Referring to
In
In some embodiments, gates of the cascode transistors MC401 and MC402 and gates of the transistors M401 and M402 are electrically coupled with each other. Gates of the cascode transistors MC403 and MC404 and gates of the transistors M403 and M404 are electrically coupled with each other. A bulk and a source of the transistor M401 are electrically coupled to each other and electrically grounded. A bulk and a source of the transistor M402 are electrically coupled to each other and with the resistor R401. Bulks of the transistors M403 and M404 are electrically coupled with the supply voltage VDD.
Referring to
In some embodiments, gates of the cascode transistors MC501 and MC502 and gates of the transistors M501 and M502 are electrically coupled with each other. Gates of the cascode transistors MC503 and MC504 and gates of the transistors M503 and M504 are electrically coupled with each other. A bulk and a source of the transistor M501 are electrically coupled to each other and with the output VOUT of the bandgap reference circuit 500. A bulk and a source of the transistor M502 are electrically coupled to each other and with the resistor R503. Bulks of the transistors M503 and M504 are electrically coupled with the supply voltage VDD.
Referring to
As noted, the descriptions of the analog circuits in conjunction with
In some exemplary embodiments of this application, an integrated circuit includes an analog circuit including a first transistor. At least one cascode transistor is electrically coupled with the first transistor in a series fashion. A drain and a gate of the cascode transistor are electrically coupled with a gate of the first transistor of the analog circuit. The at least one cascode transistor is operated in a saturation mode or a sub-threshold mode.
In some exemplary embodiments of the current application, an integrated circuit includes an analog circuit including a first transistor. At least one cascode transistor is electrically coupled with the first transistor in a series fashion. A drain and a gate of the cascode transistor are electrically coupled with a gate of the first transistor of the analog circuit. The at least one cascode transistor includes at least one of a native transistor, a low threshold voltage (LVT) transistor, and an ultra-low threshold voltage (ULVT) transistor.
In some exemplary embodiments of the application, an integrated circuit includes a first P-type cascode transistor electrically coupled with a first P-type transistor in a series fashion. A second P-type cascode transistor is electrically coupled with a second P-type transistor in a series fashion. Gates of the first P-type cascode transistor, the second P-type cascode transistor, the first P-type transistor, and the second P-type transistor are electrically coupled to each other and with a drain of the first P-type cascode transistor.
The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the detailed description. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.