Claims
- 28) (NEW) An integrated device for amplification reactions, comprising:
a) a monolithic semiconductor material body having a surface; b) at least one buried channel extending in said semiconductor material body, arranged at a distance from said surface, and having a first and a second end; c) at least one inlet port and outlet port extending from said surface respectively as far as said first end and second end of said buried channel, and being in fluid connection with said buried channel; and d) at least one heating element arranged on said semiconductor material body.
- 29) (NEW) The device according to claim (28), comprising a plurality of buried channels extending parallel and adjacent to each other.
- 30) (NEW) The device according to claim (29), wherein said inlet port and said outlet port are connected to all said buried channels.
- 31) (NEW) The device according to claim (29), comprising a plurality of inlet ports and a plurality of outlet ports, said inlet and outlet ports extending from said surface of said semiconductor material body to a respective end of a respective buried channel.
- 32) (NEW) The device according to claim (29), comprising a plurality of heating elements extending adjacent to each other, and each having opposite electric connection regions arranged on opposite sides of said buried channel.
- 33) (NEW) The device according to claim (32), comprising a plurality of temperature sensing elements arranged between pairs of adjacent heating elements.
- 34) (NEW) The device of claim (28), wherein said semiconductor material body comprises a monocrystalline substrate, with a <110> crystallographic orientation, and wherein each buried channel has a longitudinal direction that is substantially parallel to a crystallographic plane with a <111> orientation.
- 35) (NEW) The device according to claim (34), wherein each buried channel has a depth of up to 600-700 μm.
- 36) (NEW) A process for manufacturing an integrated device for amplification reactions, comprising:
a) forming a monolithic semiconductor material body having a surface; b) forming at least a buried channel extending in said semiconductor material body, arranged at a distance from said surface, and having a first and a second end; c) forming at least a first and a second port extending from said surface respectively as far as said first and second ends of said buried channel, and being in fluid connection with said buried channel; and d) forming at least a heating element on said semiconductor material body.
- 37) (NEW) The process according to claim (36), wherein forming a semiconductor material body and forming at least a buried channel comprises:
a) forming a substrate of semiconductor material; b) forming surface trenches in said substrate; and c) forming a semiconductor layer on said substrate.
- 38) (NEW) The process according to claim (37), comprising, after forming surface trenches and before forming a semiconductor layer, anisotropically etching the substrate beneath said surface trenches to form said channels.
- 39) (NEW) The process according to claim (36), wherein forming a semiconductor material body comprises forming a monocrystalline substrate; forming said buried channel in said monocrystalline substrate; and forming a semiconductor layer on top of said monocrystalline substrate and said buried channel.
- 40) (NEW) The process according to claim (39), wherein forming a monocrystalline substrate comprises growing semiconductor material with a <110> orientation, and forming a buried channel comprises etching said monocrystalline substrate along a parallel direction to an <111> orientation plane.
- 41) (NEW) The process according to claim (40), wherein, during etching of said monocrystalline substrate, a grid-shaped mask is used with polygonal apertures, with sides extending at approximately 45° with respect to said <111> orientation plane.
- 42) (NEW) The process according to claim (40), wherein said monocrystalline substrate is etched using tetramethyl ammonium hydroxide.
- 43) (NEW) The process according to claim (39), wherein forming a buried channel comprises masking said substrate through a grid-like hard mask, and etching said substrate through the hard mask.
- 44) (NEW) The process according to claim (43), wherein said hard mask comprises a polycrystalline region, surrounded by a covering layer of dielectric material, and wherein, after etching of said substrate, said covering layer is removed, and said semiconductor layer forms on said polycrystalline region and forms a polycrystalline region, and on said substrate and forms a monocrystalline region.
- 45) (NEW) The process according to claim (43), wherein said hard mask comprises a dielectric material grid, and said semiconductor layer grows on said substrate and on said dielectric material grid, forming a monocrystalline region on said substrate, and a polycrystalline region on said dielectric material grid.
- 46) (NEW) The process of claim (39), comprising depositing an insulating material layer on said semiconductor material body, before forming at least a heating element.
- 47) (NEW) The process of claim (39), comprising forming at least a thermosensing element on said semiconductor material body, adjacent to said heating element.
- 48) (NEW) A device for biological tests comprising:
a) a plurality of buried channels formed a predetermined distance beneath a surface of a monolithic semiconductor material body; b) at least one port formed in the semiconductor material body and in fluid communication with the surface of the semiconductor material body and with first and second ends, respectively, of the at least one buried channel; and c) at least one heating element formed on the surface of the semiconductor material body and positioned over the at least one buried channel to heat fluid in the at least one buried channel.
- 49) (NEW) The device of claim (48), further comprising a temperature sensing element arranged adjacent the at least one heating element, the temperature sensing element configured to regulate the temperature of the at least one heating element to thereby regulate the temperature of fluid in the at least one buried channel.
- 50) (NEW) A method for manufacturing a device for biological tests, comprising:
a) forming at least one buried channel a predetermined distance beneath a surface of a monolithic semiconductor material body; b) forming first and second ports in the semiconductor material body to be in fluid communication with the surface of the semiconductor material body and with first and second ends, respectively, of the at least one buried channel; and c) forming at least one heating element on the surface of the semiconductor material body to be positioned over the at least one buried channel for heating fluid in the at least one buried channel.
- 51) (NEW) The method of claim (50), further comprising forming at least one temperature sensing element adjacent the at least one heating element on the surface of the semiconductor material body, the temperature sensing element configured to regulate the temperature of the at least one heating element to thereby regulate the temperature of fluid in the at least one buried channel.
- 52) (NEW) An integrated device for biological tests, comprising:
a) a monolithic semiconductor material body having a surface; b) a plurality of buried channels extending parallel and adjacent to each other in said semiconductor material body, arranged at a distance from said surface, and each buried channel having a first and a second end; c) at least one first port and second port extending from said surface respectively as far as said first end and second end of each buried channel, and being in fluid connection with each buried channel; and d) at least one heating element arranged on said semiconductor material body.
- 53) (NEW) A process for manufacturing an integrated device for biological tests, comprising:
a) forming a substrate of semiconductor material; b) forming surface trenches in said substrate; c) forming a semiconductor layer on a surface in said substrate to form at least a buried channel extending in said semiconductor material body, arranged at a distance from said surface, and having a first end and a second end; d) forming at least a first and a second port extending from said surface respectively as far as said first and second ends of said buried channel, and being in fluid connection with said buried channel; and e) forming at least a heating element on said semiconductor material body.
- 54) (NEW) A process for manufacturing an integrated device for biological tests, comprising:
a) forming a monocrystalline substrate; b) forming a channel in said monocrystalline substrate; c) forming a semiconductor layer on a surface of said monocrystalline substrate and over said channel to form at least a buried channel extending in said semiconductor material body, arranged at a distance from said surface, and having a first and a second end; d) forming at least a first and a second port extending from said surface respectively as far as said first and second ends of said buried channel, and being in fluid connection with said buried channel; and e) forming at least a heating element on said semiconductor material body.
- 55) (NEW) A device for biological tests comprising:
a) a plurality of buried channels formed a predetermined distance beneath a surface of a monolithic semiconductor material body; b) at least one port formed in the semiconductor material body and in fluid communication with the surface of the semiconductor material body and with first and second ends, respectively, of the at least one buried channel.
- 56) (NEW) A method of performing a biological test, wherein a biological fluid is applied to any one of the devices of claims (28-35), (48-49), (52), or (55) and a biological test is performed.
- 57) (NEW) The method of claim (56), wherein the biological test is amplification.
- 58) (NEW) The method of claim (57), wherein the device is the device of claim 33.
- 59) (NEW) The method of claim (58), wherein the amplification is DNA amplification.
Priority Claims (1)
Number |
Date |
Country |
Kind |
EP 00830098.0 |
Feb 2000 |
EP |
|
PRIOR RELATED APPLICATIONS
[0001] This application is a continuation of U.S. application Ser. No. 09/799,980, filed Feb. 8, 2001, which claims priority to EP application 00830098.0 (EPI 123739), filed Feb. 11, 2000, incorporated by reference in its entirety.
Continuations (1)
|
Number |
Date |
Country |
Parent |
09799980 |
Mar 2001 |
US |
Child |
10706246 |
Nov 2003 |
US |