This patent application claims priority from Italian patent application no. 102021000027956 filed on Nov. 3, 2021 the entire disclosure of which is incorporated herein by reference.
The present invention refers to an integrated electronic circuit with offset compensation for an implantable probe.
As is well known, so-called implantable multi-electrode array probes that are adapted to record numerous (in the order of thousands) electrophysiological signals generated, for example, by individual neurons are nowadays available.
In particular, active type probes are known, which each include a plurality of pixels, each of which integrates a respective sensing electrode and a corresponding amplification circuitry.
In use, the sensing electrode is contacted with a corresponding portion of tissue (e.g., brain tissue), in order to acquire a corresponding initial electrical signal, which is then amplified by the corresponding amplification circuitry, so as to generate a corresponding output signal.
For example,
In order to have a high density of pixels 2 per unit area, each pixel 2, and therefore also the corresponding amplification circuitry, should occupy a reduced area. For this reason, it is known to use the so-called CMOS technology to create pixels 2, this technology also allowing to reduce consumptions.
However, the Applicant has observed how, in use, a corresponding electrode-electrolyte interface is formed at each sensing electrode and which is subject to high direct voltage variations, i.e. it exhibits a DC offset that can be particularly high (up to hundreds of millivolts). The causes of this DC offset may include, for example, the differences in composition of the biological tissue being measured.
In order to reduce the impact of the aforementioned DC offset on the output signal, it is for example possible to implement an AC coupling between the amplification circuitries and the sensing electrodes, however this solution requires the formation of capacitors with high capacitance, resulting in high area occupancy. This solution is therefore unsuitable for high channel density recording systems, i.e. for recording systems having a high number of pixels per unit area.
The article “Large scale, high-resolution data acquisition system for extracellular recording of electrophysiological activity”, by Imfeld K. et al., IEEE TRANSACTIONS ON BIOMEDICAL ENGINEERING, vol. 5, no. 8, pp. 2064-2073 and the article “A low-power, low-area modular architecture for high-density neural probes”, by Angotzi G. N. and Berdondini L., 7th Annual International IEEE EMBS Conference on Neural Engineering, Montpellier, France, 20-22 Apr. 2015 describe electronic circuits in which an electrode is polarised by means of a pair of P-MOS transistors connected in parallel, which together deliver a current that polarises a further P-MOS transistor, whose gate terminal is connected to the electrode.
Aim of the present invention is therefore to provide an integrated electronic circuit that allows to solve at least in part the drawbacks of the prior art. According to the invention, there is provided an integrated electronic circuit as defined in the appended claims.
For a better understanding of the invention, embodiments thereof will now be disclosed, for merely illustrative and non-limiting purposes and with reference to the enclosed drawings, wherein:
In detail, the pixel 10 comprises a supply terminal, which in use is set to a supply voltage VDD for example equal to 1.8V, and a ground (GND). Furthermore, the pixel 10 comprises a first and a second transistor M1, M2, which are referred to hereinbelow as the first and second biasing transistors M1, M2 respectively.
The first and second biasing transistors M1, M2 are P-channel enhancement MOSFET transistors. Furthermore, the source terminal of the first biasing transistor M1 is connected to the supply voltage VDD; the drain terminal of the first biasing transistor M1 is connected to the source terminal of the second biasing transistor M2, so as to form an input node NIN. The drain terminal of the second biasing transistor M2 is grounded; furthermore, and without any loss of generality, the source terminal of the second biasing transistor M2 is connected to the body terminal of the second biasing transistor M2.
As shown in
As shown in
The pixel 10 further comprises a capacitor C, which has a first and a second terminal, which are respectively connected to the gate terminal of the first biasing transistor M1 and to the supply voltage VDD.
The pixel 10 further comprises an amplifier 20 (for example, but not limited to, of the transconductance type), the positive input terminal of which is connected to the input node NIN, and the negative input terminal of which is connected to the shared circuitry 12, shown in
The pixel 10 furthermore comprises three switches, which are referred to hereinbelow as the first and second calibration switches S1, S2 and as the output switch SOUT respectively. As described in greater detail below, the first and second calibration switches S1, S2 are controlled by a signal ΦAZ[i], while the output switch SOUT is controlled by a signal read [i]. The signal ΦAZ[i] and the signal read [i] are generated by the shared circuitry 12, as shown in
The shared circuitry 12 comprises a feedback amplifier stage 30 (shown in
The feedback amplifier stage 30 has furthermore an output terminal, which is connected to a first terminal of the first calibration switch S1, the second terminal of which is connected to the first terminal of the capacitor C, and therefore also to the gate terminal of the first biasing transistor M1.
In greater detail, as shown in
The output terminal of the feedback amplifier 32 forms the output terminal of the feedback amplifier stage 30, therefore it is connected to the first terminal of the first calibration switch S1.
The first additional switch SA1 is interposed between the negative input terminal of the feedback amplifier 32 and the first input terminal of the feedback amplifier stage 30, which, as mentioned above, is set to the voltage Vref2.
The second additional switch SA2 is interposed between the positive input terminal of the feedback amplifier 32 and the first input terminal of the feedback amplifier stage 30.
The third additional switch SA3 is interposed between the negative input terminal of the feedback amplifier 32 and the output terminal of the feedback amplifier 32.
The fourth additional switch SA4 is interposed between the positive input terminal of the feedback amplifier 32 and the second input terminal of the feedback amplifier stage 30.
Furthermore, the first and fourth additional switches SA1, SA4 are controlled by a signal ΦAZ generated by the shared circuitry 12. In particular, the first and fourth additional switches SA1, SA4 are closed when the signal ΦAZ is equal to ‘1’ and are open when the signal ΦAZ is equal to ‘0’.
The second and the third additional switches SA2, SA4 are controlled by a signal NΦAZ equal to the logical negation of the signal ΦAZ. In this way, the second and third additional switches SA2, SA3 are open when the signal ΦAZ is equal to ‘1’ and are closed when the signal ΦAZ is equal to ‘0’.
In practice, the first and second biasing transistors M1, M2 form a so-called common drain stage, which has a unit gain and receives as input the input voltage Vin. Furthermore, as explained below, the common drain stage allows to control the direct voltage present on the positive input terminal of the amplifier 20, which provides a high gain (e.g., higher than 40 dB) over a band extending, for example, up to 4 kHz. At the output from the amplifier there is an output signal VOUT, which, when read [i]=‘1’, is provided on the output node NOUT, therefore it is provided to the shared circuitry 12, which reads it in a per se known way.
In greater detail, the shared circuitry 12 generates the signals ΦAZ (and thus also NΦAZ) and ΦAZ[i] so that the pixel 10 operates under different operating conditions.
In particular, as shown in
As far as instead the signal ΦAZ[i] is concerned, however, it is relative to the i-th pixel 10. Furthermore, considering the i-th pixel 10, the corresponding signal ΦAZ [i] is generated by the shared circuitry 12 so as to be equal to ‘1’ only when the i-th pixel 10 is selected, otherwise it is equal to ‘0’; furthermore, the signal ΦAZ[i] has a single pulse (denoted with 29) for each pulse burst 25 of the signal ΦAZ, said single pulse 29 being temporally aligned with a corresponding pulse of the pulse burst 25. In addition, when ΦAZ[i]=‘1’, ΦAZ[j]=‘0’ occurs for each j between 1 and 32, but other than i.
That being said, referring again to the pixel 10 shown in
In detail, the first and second calibration switches S1, S2 are closed, therefore the feedback amplifier 32 is coupled to the amplifier 20 and forms an autozeroing loop such that a voltage approximately equal to the voltage Vref1 is set on the input node NIN. In particular, the capacitor C is subject to a voltage such that the gate terminal of the first biasing transistor M1 is in turn subject to a voltage such that the first biasing transistor M1 injects in the input node NIN a biasing current Ibias. The biasing current Ibias therefore depends on the charge stored in the capacitor C and is precisely such that the input node NIN is set equal to the voltage Vref1.
Furthermore, thanks to the autozeroing loop, on the output terminal of the amplifier 20 there is a voltage approximately equal to the voltage Vref2, as shown again in
Subsequently, when the signal ΦAZ[i] returns to ‘0’, the first and second calibration switches S1, S1 open and the pixel 10 operates under sensing conditions, shown in
Ideally, the capacitor C maintains the previously stored charge, therefore the biasing current Ibias does not vary and the input node NIN remains at the voltage Vref1; consequently, the biasing of the positive input terminal of the amplifier 20 does not vary. Furthermore, the amplifier 20 operates in open loop and amplifies the input signal VIN present on the electrode 15, allowing a correct sensing thereof. Thus, while the pixel 10 operates under sensing conditions, the shared circuitry 12 can set read [i]=‘1’, so that the same shared circuitry 12 can read the output signal VOUT, which includes a direct voltage contribution equal to the voltage Vref2 and a small signal contribution that is a function of the aforementioned small: signal voltage Vin.
In fact, due to unavoidable losses, the charge present in the capacitor C tends to reduce, causing a reduction of the biasing current Ibias and therefore a variation (reduction) of the voltage present on the input node NIN, with consequent reduction of the output signal VOUT, and in particular of the direct voltage component of the latter, as shown in
Furthermore, during each period of time in which the pixel 10 operates under calibration conditions, the autozeroing loop cancels the impact on the biasing of the amplifier 20 of the DC offset affecting the electrode 15, that is, it compensates for the DC offset. In this regard, thanks to the fact that the biasing current Ibias is injected in the input node NIN by a single transistor (in particular, the first biasing transistor M1), the interval of the DC offset values that can be compensated for (with the same voltage Vref1) is maximized, since the biasing current Ibias can be reduced up to a minimum value Imin which depends on the sizing of the first and second biasing transistors M1, M2. In this regard, the direct voltage on the input node NIN is equal to the sum between the direct voltage VDC of the input voltage Vin and a direct voltage VDCAZ set by the autozeroing loop; in the presence of high values of the direct voltage VDC, the autozeroing loop reduces the direct voltage VDCAZ (to the limit, until it cancels it, if VDC=Vref1) tending to turn off the first biasing transistor M1 so as to reduce the biasing current Ibias.
Still with reference to the biasing current Ibias, the current flowing in the second biasing transistor M2 is precisely equal to the biasing current Ibias, since no current flows in the positive input terminal of the amplifier 20. With regard to the signal ΦAZ, when it is equal to ‘0’, it happens that the second and third additional switches SA2, SA3 are closed, while the first and fourth additional switches SA1, SA4 are open. Consequently, as shown in
According to a variant, the voltages Vref1 generated on the negative input terminals of the amplifiers 20 of the pixels 10 may vary from pixel to pixel. In other words, the shared circuitry 12 applies, on each negative input terminal of the amplifiers 20 of the pixels 10, a corresponding voltage Vref1, with the following benefits.
In general, the autozeroing loop is capable of compensating for DC offsets in the interval Vref1±ΔV, where ΔV is proportional to the biasing current Ibias, which however is subject to an upper limit depending on the dimensions of the first and second biasing transistors M1, M2, as well as on the stability conditions of the autozeroing loop. Therefore, high values of the voltage Vref1 are better suited to compensate for high values of the DC offset; on the contrary, in case the DC offset has a reduced value, the compensation is preferably obtained by adopting a reduced voltage Vref1.
That being said, since electrodes 15 of different pixels 10 may be subject to different DC offsets, in particular in the event that the probe module 11 includes a very large array of electrodes 15, the possibility of setting, for different pixels 10, different values of the respective voltages Vref1 (which are set on the negative input terminals of the respective amplifiers 20) allows to optimize, for each pixel 10, the compensation for the DC offset it experiences.
The advantages that the present integrated electronic circuit allows obtaining emerge clearly from the previous description. In particular, during the calibration step, the autozeroing loop including the feedback amplifier 32 allows to control the biasing current Ibias that flows in the common drain stage and therefore allows to adjust the direct voltage present on the positive input terminal of the amplifier 20, compensating for the DC offset present in the voltage Vin. Furthermore, since the biasing current Ibias comes from a single transistor (in this case, the first biasing transistor M1), it is possible to compensate for high DC offsets, with the same voltage Vref1.
Furthermore, the Applicant has observed that the autozeroing loop is stable, despite the wide interval of values that can be assumed by the biasing current Ibias.
It is finally clear that modifications and variants can be made to this integrated electronic circuit, without departing from the scope of the present invention, as defined by the enclosed claims.
For example, the capacitor C may be made in MIM (“metal-insulator-metal”) technology or by using the parasitic capacitance present on the gate terminal of the first biasing transistor M1.
For example, the negative and positive input terminals of each amplifier 20 and/or of the feedback amplifier may be reversed with respect to what is described.
Furthermore, the probe module 11 can be used together with other probe modules similar to it, so as to implement a system for recording electrical signals of biological origin with high parallelism.
Finally, the capacitor C can be grounded (GND), instead of to the supply voltage VDD.
Number | Date | Country | Kind |
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102021000027956 | Nov 2021 | IT | national |
Filing Document | Filing Date | Country | Kind |
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PCT/IB2022/060551 | 11/2/2022 | WO |