1. Field of the Invention
The present invention relates generally to display technologies and, more specifically, to an integrated line selection apparatus within active matrix arrays.
2. Background
Flat panel displays with electrophoretic, liquid crystal (LC), or organic light emitting diode (OLED) based pixel technology, as well as many sensor applications, all rely on a well known low temperature active matrix backplane technology to address the individual pixels in the matrix array. In an active matrix array, each pixel is controlled by one to four transistors and selection of the active gate lines in the array is typically performed using crystalline silicon Complementary Metal Oxide Semiconductor (CMOS) multiplexers and line drivers.
However, the high voltage required to drive multiple backplane transistors within the active matrix array adds to the costs of the integrated circuit. In addition, the large number of interconnects required to address the pixels in the matrix array also increase the assembly costs of the flat panel displays.
Accordingly, there is a need for a method and apparatus for efficient integration of gate line selection into the low temperature active matrix display manufacturing process in order to reduce manufacturing costs and the number of components, thus improving the reliability of the product.
An integrated line selection apparatus within active matrix arrays is described. The circuit includes multiple gate line drive transistor devices, each gate line drive transistor device having a drain coupled to a gate line of multiple gate lines in a gate line driver circuit coupled to an active matrix array and a source to receive an input signal. The circuit further includes at least one address line transistor device corresponding to each gate line transistor device, each address line transistor device having a drain coupled to a gate of the corresponding gate line drive transistor device and a gate coupled to a corresponding address line, such that by asserting a predetermined combination of voltages on the plurality of address lines, a single gate line of said plurality of gate lines is selected to receive the input signal to be transmitted to a corresponding pixel within the corresponding active matrix array.
The data line driver circuit 120 supplies the video signals as voltages to the TFT devices 220, which are turned on and off using the timing signals applied in sequence from the gate line driver circuit 130. Specifically, each TFT device 220 keeps the corresponding pixel electrode 210 at a predetermined voltage, based on the video signal supplied to the pixel electrode 210 in response to a timing signal, until it receives a subsequent timing signal from the gate line driver circuit 130.
In amorphous or polycrystalline silicon technology, the gate line driver circuit 130 includes a shift register and/or a pass-transistor based demultiplexer module, as described in detail, for example, in “Stability Issues In Digital Circuits In Amorphous Silicon Technology,” by N. Mohan et al., Proc. IEEE CCECE 2001, Toronto, Canada, May 13-16, 2001, and in “Amorphous Silicon Shift Registers For Display Drivers,” by A. Kumar et al., J. Vac. Sci. Technol. A 22.3, May/June 2004. The shift register within the gate line driver circuit 130 further includes multiple concatenated shift register cells, each shift register cell being assigned to one gate line 112 in the active matrix array 110.
As shown in
The embodiments described in detail below provide for arbitrary selection of a gate line 112 with a single level of decoding, with ability to compensate for threshold shift by reversing the gate bias, and with ability to provide for fault tolerance with an increased number of addressing lines.
In one embodiment, gate line G0 is coupled to address lines A2 and A3 through transistor devices T1, T2, and T3, such that the gate of transistor T3 is coupled to the respective drains of transistors T1 and T2. The source of transistor T3 receives an input signal S transmitted from a signal source (not shown), as described in detail below. If a high voltage is applied at either of the address lines A2 or A3, the corresponding transistor devices T1 or T2 will be turned on, thus causing a negative voltage at the gate of transistor T3. As a result, the input signal S will not travel to the gate line G0 and, thus, the gate line G0 will be deselected. Similarly, all gate lines 112 that are coupled to either address lines A2 or A3, such as, for example, gate lines G1 through G4, will also be deselected. Therefore, the apparatus 600 enables selection of a single gate line 112, in this case gate line G5, and the de-selection of the other remaining gate lines.
In one embodiment, the most gate lines 112 that can be addressed by m address lines 113 is n=2m (2/mπ)1/2. Thus, if the number “m” of address lines 113 varies between 10 and 50, for example, the combinatorial addressing scheme will require approximately three additional address lines 113 in a single stage, as opposed to the binary addressing scheme. However, in a typical implementation, the binary addressing scheme for 1000 addressable gate lines 112 usually requires ten stages, which would create prohibiting delays in amorphous silicon technology.
Referring back to
In one exemplary embodiment, gate line G0 is coupled to address lines A3, A4, and A5 through transistor devices T1, T2, T3, and T4 such that the gate of transistor T4 is coupled to the respective drains of transistors T1, T2, and T3. The source of transistor T4 receives an input signal S transmitted from a signal source (not shown), as described in detail below. Similarly, gate line G1 is coupled to address lines A1, A2, and A5, and gate line G2 is coupled to address lines A0, A1, and A4.
In the embodiment shown in
Assuming that each bit of the gate line address is defined as having a “0” value if there is no connection between the address line 113 and the gate of the corresponding gate line transistor device 710, and, otherwise, each bit is defined as having a “1” value, then the 4-bit address of the gate line G0 in the embodiment of
The effects of threshold voltage shifts in the embodiments of
In one exemplary embodiment, gate line G0 is coupled to address lines A2 and A3 through transistor devices T1, T2, and T3, such that the gate of transistor T3 is coupled to the respective drains of transistors T1 and T2. The source of transistor T3 receives an input signal S transmitted from a signal source (not shown), as described in detail below. The gate of each transistor device 910 is further coupled to a pull-up transistor device 920. Specifically, in one example, transistor T3 is further coupled to transistor T4. The use of pull-up transistor T4 in the embodiment shown in
In one embodiment, gate line G0 is coupled to address lines A2 and A3 through transistor devices T1, T2, and inverter device I3, such that the input of the inverter device I3 is coupled to the respective drains of transistors T1 and T2. If a high voltage is applied at either of the address lines A2 or A3, the corresponding transistor devices T1 or T2 will be turned on, thus causing the voltage Vdd to be applied to the input of the inverter device I3. As a result, the gate line G0 will be deselected. Similarly, all gate lines 112 that are coupled to either address lines A2 or A3, such as, for example, gate lines G1 through G4, will also be deselected. Therefore, the apparatus 1000 enables selection of a single gate line 112, in this case gate line G5, and the de-selection of all the other remaining gate lines.
In one embodiment, gate line G0 is coupled to address lines A2 and A3 through transistor devices T1, T2, T3 and is coupled to address lines A0 and A1 through transistor devices T3, T4, T5, such that the gate of transistor T3 is coupled to the respective drains of transistors T1 and T2 and to the sources of transistors T4 and T5. The source of transistor T3 is coupled to a voltage source Vdd or more generally a signal source 410. If a high voltage is applied at either of the address lines A0 or A1, the corresponding transistor devices T4 or T5 will be turned on, thus causing a voltage Vdd to be applied at the gate of transistor T3. As a result, the voltage Vdd will turn on the transistor T3 and the signal 410 transferred to the gate line G0 will if none of the transistor devices connected to −Vss, such as, for example, transistors T1 or T2, are turned on. Alternatively, if a high voltage is applied at either of the address lines A2 or A3, the corresponding transistor devices T1 or T2 coupled to −Vss will be turned on, and a negative voltage −Vss will be applied at the gate of the transistor T3. Thus, in this embodiment, the bias on the select transistor device T3 can be made positive or negative based on the voltage selection applied at each address line 113 to counter any long term threshold drift.
Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The various illustrative logical blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or performed with a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor may read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a user terminal.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.