Patent Application
20050050305
The present invention is in the area of digital processors (e.g., microprocessors, digital signal processors, microcontrollers, etc.), and pertains more particularly to apparatus and methods relating to managing execution of multiple threads in a single processor.
In the realm of digital computing the history of development of computing power comprises steady advancement in many areas. Steady advances are made, for example, in device density for processors, interconnect technology, which influences speed of operation, ability to tolerate and use higher clock speeds, and much more. Another area that influences overall computing power is the area of parallel processing, which includes more than the parallel operation of multiple, separate processors.
The concept of parallel processing includes the ability to share tasks among multiple, separate processors, but also includes schemes for concurrent execution of multiple programs on single processors. This scheme is termed generally multithreading.
The concept of multithreading is explained as follows: As processor operating frequency increases, it becomes increasingly difficult to hide latencies inherent in the operation of a computer system. A high-end processor which misses in its data cache on 1% of the instructions in a given application could be stalled roughly 50% of the time if it has a 50-cycle latency to off-chip RAM. If instructions directed to a different application could be executed when the processor is stalled during a cache miss, the performance of the processor could be improved and some or all of the memory latency effectively hidden. For example,
More generally, individual computer instructions have specific semantics, such that different classes of instructions require different resources to perform the desired operation. Integer loads do not exploit the logic or registers of a floatingpoint unit, any more than register shifts require the resources of a load/store unit. No single instruction consumes all of a processor's resources, and the proportion of the total processor resources that is used by the average instruction diminishes as one adds more pipeline stages and parallel functional units to high-performance designs.
Multithreading arises in large measure from the notion that, if a single sequential program is fundamentally unable to make fully efficient use of a processor's resources, the processor should be able to share some of those resources among multiple concurrent threads of program execution. The result does not necessarily make any particular program execute more quickly—indeed, some multithreading schemes actually degrade the performance of a single thread of program execution—but it allows a collection of concurrent instruction streams to run in less time and/or on a smaller number of processors. This concept is illustrated in
Multithreading on a single processor can provide benefits beyond improved multitasking throughput, however. Binding program threads to critical events can reduce event response time, and thread-level parallelism can, in principle, be exploited within a single application program.
Several varieties of multithreading have been proposed. Among them are interleaved multithreading, which is a time-division multiplexed (TDM) scheme that switches from one thread to another on each instruction issued. This scheme imposes some degree of “fairness” in scheduling, but implementations which do static allocation of issue slots to threads generally limit the performance of a single program thread Dynamic interleaving ameliorates this problem, but is more complex to implement.
Another multithreading scheme is blocked multithreading, which scheme issues consecutive instructions from a single program thread until some designated blocking event, such as a cache miss or a replay trap, for example, causes that thread to be suspended and another thread activated. Because blocked multithreading changes threads less frequently, its implementation can be simplified. On the other hand, blocking is less “fair” in scheduling threads. A single thread can monopolize the processor for a long time if it is lucky enough to find all of its data in the cache. Hybrid scheduling schemes that combine elements of blocked and interleaved multithreading have also been built and studied.
Still another form of multithreading is simultaneous multithreading, which is a scheme implemented on superscalar processors. In simultaneous multithreading instructions from different threads can be issued concurrently. Assume for example, a superscalar reduced instruction set computer (RISC), issuing up to two instructions per cycle, and a simultaneously multithreaded superscalar pipeline, issuing up to two instructions per cycle from either of the two threads. Those cycles where dependencies or stalls prevented full utilization of the processor by a single program thread are filled by issuing instructions for another thread.
Simultaneous multithreading is thus a very powerful technique for recovering lost efficiency in superscalar pipelines. It is also arguably the most complex multithreading system to implement, because more than one thread may be active on a given cycle, complicating the implementation of memory access protection, and so on. It is perhaps worth noting that the more perfectly pipelined the operation of a central processing unit (CPU) may be on a given workload, the less will be the potential gain of efficiency for a multithreading implementation
Multithreading and multiprocessing are closely related. Indeed, one could argue that the difference is only one of degree: Whereas multiprocessors share only memory and/or connectivity, multithreaded processors share memory and/or connectivity, but also share instruction fetch and issue logic, and potentially other processor resources. In a single multithreaded processor, the various threads compete for issue slots and other resources, which limits parallelism. Some multithreaded programming and architectural models assume that new threads are assigned to distinct processors, to execute fully in parallel.
There are several distinct problems with the state-of-the-art multithreading solutions available at the time of submission of the present application. One of these is the treatment of real-time threads. Typically, real-time multimedia algorithms are run on dedicated processors/DSPs to ensure quality-of-service (QoS) and response time, and are not included in the mix of threads to be shared in a multithreading scheme, because one cannot easily guarantee that the real-time software will be executed in a timely manner.
What is clearly needed in this respect is a scheme and mechanism allowing one or more real-time threads or virtual processors to be guaranteed a specified proportion of instruction issue slots in a multithreaded processor, with a specified inter-instruction interval, such that the compute bandwidth and response time is well defined. If such a mechanism were available, threads with strict QoS requirements could be included in the multithreading mix. Moreover, real time threads (such as DSP-related threads) in such a system might be somehow exempted from taking interrupts, removing an important source of execution time variability. This sort of technology could well be critical to acceptance of DSP-enhanced RISC processors and cores as an alternative to the use of separate RISC and DSP cores in consumer multimedia applications.
Another distinct problem with state-of-the-art multithreading schemes at the time of filing the present application is in the creation and destruction of active threads in the processor. To support relatively fine-grained multithreading, it is desirable for parallel threads of program execution to be created and destroyed with the minimum possible overhead, and without intervention of an operating system being necessary, at least in usual cases. What is clearly needed in this respect is some sort of FORK (thread create) and JOIN (thread terminate) instructions. A separate problem exists for multi-threaded processors where the scheduling policy makes a thread run until it is blocked by some resource, and where a thread which has no resource blockage needs nevertheless to surrender the processor to some other thread. What is clearly needed in this respect is a distinct PAUSE or YIELD instruction.
It is a principle object of the present invention to provide a robust system for fine-grained multithreading wherein threads may be created and destroyed with minimum overhead. In accordance with this object, in a preferred embodiment of the present invention, in a processor enabled to support and execute multiple program threads, a mechanism for processing is provided, comprising a parameter for scheduling a program thread and an instruction disposed within the program thread and enabled to access the parameter. When the parameter equals a first value, the instruction reschedules the program thread in accordance with one or more conditions encoded within the parameter. In a preferred embodiment of the mechanism the parameter is held in a data storage device. Also in a preferred embodiment, when the parameter equals a second value, the second value being different from the first value, the instruction deallocates the program thread. In some embodiments the second value is zero.
In some embodiments, when the parameter equals a second value, the second value being different from the first value, the instruction unconditionally reschedules the program thread Also in some embodiments the second value is an odd value. In some other embodiments the second value is negative 1.
In some embodiments one of the one or more conditions is associated with the program thread relinquishing execution to another thread until the one condition is met. Also in some embodiments the one condition is encoded in one of a bit vector or bit field in the parameter. Also in some embodiments, in the circumstance of the program thread being rescheduled, execution of the program thread resumes at a place in the thread following the instruction. In still other embodiments, when the parameter equals a third value, the third value being different from the first and second values, the instruction unconditionally reschedules the program thread.
In some embodiments of the mechanism one of the one or more conditions is a hardware interrupt. Also in some embodiments, one of the one or more conditions is a software interrupt. In many embodiments, in the circumstance of the program thread being rescheduled, execution of the program thread resumes at a place in the thread following the instruction.
In another aspect of the invention, in a processor enabled to support and execute multiple program threads, a method for rescheduling execution or deallocating itself by a thread is provided, comprising (a) issuing an instruction that accesses a portion of a record in a data storage device encoding one or more parameters associated with one or more conditions under which the thread is or is not to be rescheduled; and (b) following the conditions for rescheduling according to the one or more parameters in the portion of the record or deallocating the thread. In a preferred embodiment the record is in a general purpose register (GPR). Also in a preferred embodiment one of the parameters is associated with the thread being deallocated rather than rescheduled. In some embodiments the parameter associated with the thread being deallocated is a value of zero.
In some embodiments of the method one of the parameters is associated with the thread being requeued for scheduling. Also in some embodiments the parameter is any-odd-value. In some embodiments the parameter is a two's compliment value of negative 1. In some embodiments one of the parameters is associated with the thread relinquishing execution to another thread until a specific condition is met. In other embodiments parameter is encoded in one of a bit vector or one or more value fields in the record.
Further in many embodiments of the method, in the circumstance of the thread issuing the instruction and being rescheduled, execution of the thread resumes, upon the one or more conditions being met, at a place in the thread instruction stream following the instruction that the thread issued. In some embodiments one of the parameters is associated with the thread being deallocated rather than rescheduled, and another of the parameters is associated with the thread being requeued for scheduling. In other embodiments one of the parameters is associated with the thread being deallocated rather than rescheduled, and another of the parameters is associated with relinquishing execution to another thread until a specific condition is met. In still other embodiments one of the parameters is associated with the thread being requeued for rescheduling, and another of the parameters is associated with relinquishing execution to another thread until a specific condition is met. In yet other embodiments one of the parameters is associated with the thread being deallocated rather than rescheduled, another of the parameters is associated with the thread being requeued for scheduling, and another of the parameters is associated with relinquishing execution to another thread until a specific condition is met.
In another aspect of the invention, a digital processor for supporting and executing multiple software entities is provided, comprising a portion of a record in a data storage device encoding one or more parameters associated with one or more conditions under which a thread is or is not to be rescheduled once the thread yields execution to another thread.
In some preferred embodiments of the processor the portion of the record is in a general purpose register (GPR). In some other preferred embodiments one of the parameters is associated with the thread being deallocated rather than rescheduled. In still other preferred embodiments the parameter associated with the thread being deallocated is a value of zero.
In other embodiments of the processor one of the parameters is associated with the thread being requeued for scheduling. In other embodiments the parameter is any-odd-value. In still other embodiments the parameter is a two's compliment value of negative 1. In yet other embodiments one of the parameters is associated with the thread relinquishing execution to another thread until a specific condition is met. In some cases the parameter may be encoded in one of a bit vector or one or more value fields in the record.
In some other embodiments of the processor one of the parameters is associated with the thread being deallocated rather than rescheduled, and another of the parameters is associated with the thread being requeued for scheduling. In yet other embodiments one of the parameters is associated with the thread being deallocated rather than rescheduled, and another of the parameters is associated with relinquishing execution to another thread until a specific condition is met. In still other embodiments one of the parameters is associated with the thread being requeued for rescheduling, and another of the parameters is associated with relinquishing execution to another thread until a specific condition is met.
In some other embodiments one of the parameters is associated with the thread being deallocated rather than rescheduled, another of the parameters is associated with the thread being requeued for scheduling, and another of the parameters is associated with relinquishing execution to another thread until a specific condition is met.
In yet another aspect of the invention a processing system enabled to support and execute multiple program threads is provided, comprising a digital processor, a portion of a record in a data storage device encoding one or more parameters associated with one or more conditions under which a thread is or is not to be rescheduled, and an instruction set including an instruction for rescheduling and deallocating the thread. The instruction, when issued by the thread, accesses the one or more parameters of the record, and the system follows the one or more conditions for rescheduling or deallocating the issuing thread according to the one or more parameters of the portion of the record.
In some preferred embodiments of the processing system the record is in a general purpose register (GPR). Also in some preferred embodiments one of the parameters is associated with the thread being deallocated rather than rescheduled. In some embodiments the parameter associated with the thread being deallocated is a value of zero. In some other embodiments one of the parameters is associated with the thread being requeued for scheduling. The parameter for rescheduling in some is any-odd-value. In some other embodiments the parameter for rescheduling is a two's compliment value of negative 1.
In some embodiments of the system one of the parameters is associated with the thread relinquishing execution to another thread until a specific condition is met Also in some embodiments the parameter is encoded in one of a bit vector or one or more value fields in the record. In many embodiments, in the circumstance of a thread issuing the instruction and being conditionally rescheduled, execution of the thread resumes, upon the one or more conditions being met, at a place in the thread instruction stream following the instruction.
In some embodiments of the processing system one of the parameters is associated with the thread being deallocated rather than rescheduled, and another of the parameters is associated with the thread being requeued for scheduling. Also in some embodiments one of the parameters is associated with the thread being deallocated rather than rescheduled, and another of the parameters is associated with relinquishing execution to another thread until a specific condition is met.
In some other embodiments one of the parameters is associated with the thread being requeued for rescheduling, and another of the parameters is associated with relinquishing execution to another thread until a specific condition is met In still other embodiments one of the parameters is associated with the thread being deallocated rather than rescheduled, another of the parameters is associated with the thread being requeued for scheduling, and another of the parameters is associated with relinquishing execution to another thread until a specific condition is met.
In yet another aspect of the invention a digital storage medium having written thereon instructions from an instruction set for executing individual ones of multiple software threads on a digital processor is provided, the instruction set including an instruction which causes the issuing thread to yield execution, and to access a parameter in a portion of a record in a data storage device wherein conditions for deallocation or rescheduling are associated with the parameter, and the conditions for deallocation or rescheduling according to the parameter of the portion of the record are followed
In some embodiments of the medium the record is in a general purpose register (GPR). Also in some embodiments of the medium one of the parameters is associated with the thread being deallocated rather than rescheduled. In some embodiments the parameter associated with the thread being deallocated is a value of zero. In some other embodiments one of the parameters is associated with the thread being requeued for scheduling. In still other embodiments the parameter is any-odd-value. In yet other embodiments the parameter is a two's compliment value of negative 1.
In still other embodiments of the medium one of the parameters is associated with the thread relinquishing execution to another thread until a specific condition is met. In yet other embodiments the parameter is encoded in one of a bit vector or one or more value fields in the record. In still other embodiments one of the parameters is associated with the thread being deallocated rather than rescheduled, and another of the parameters is associated with the thread being requeued for scheduling. In still other embodiments one of the parameters is associated with the thread being deallocated rather than rescheduled, and another of the parameters is associated with relinquishing execution to another thread until a specific condition is met.
In some embodiments of the mechanism one of the parameters is associated with the thread being requeued for rescheduling, and another of the parameters is associated with relinquishing execution to another thread until a specific condition is met. Also, in some embodiments of the digital storage medium, one of the parameters is associated with the thread being deallocated rather than rescheduled, another of the parameters is associated with the thread being requeued for scheduling, and another of the parameters is associated with relinquishing execution to another thread until a specific condition is met
In some embodiments of the mechanism the instruction is a YIELD instruction. Also in some embodiments of the mechanism the portion of the record comprises a bit vector. In other embodiments of the mechanism the portion of the record comprises one or more multi-bit fields.
In some embodiments of the method the instruction is a YIELD instruction, and in some embodiments of the processing system the instruction is a YIELD instruction.
In some embodiments of the digital storage medium the instruction is a YIELD instruction.
In yet another aspect of the invention a computer data signal embodied in a transmission medium is provided, comprising computer-readable program code for describing a processor enabled to support and execute multiple program threads, and including a mechanism for rescheduling and deallocating a thread, the program code comprising a first program code segment for describing a portion of a record in a data storage device encoding one or more parameters associated with one or more conditions under which a thread is or is not to be rescheduled, and a second program code segment for describing an instruction enabled to access the one or more parameters of the record, wherein the instruction when issued by the thread, accesses the one or more values in the record, and follows the one or more conditions for rescheduling according to the one or more values, or deallocates the thread.
In another aspect, in a processor enabled to support multiple program threads, a method is provided, comprising executing an instruction that accesses a parameter related to thread scheduling, wherein the instruction is included in a program thread, and deallocating the program thread in response to the instruction when the parameter equals a first value. In some embodiments of the method the first value is zero. Also in some embodiments of the method there is further a step for suspending the program thread from execution in response to the instruction when the parameter equals a second value, wherein the second value is different from the first value. In some embodiments of this method the second value indicates that a condition required for execution of the program thread is unsatisfied.
In some other embodiments of the method the condition is encoded within the parameter as a bit vector or value field. In some other embodiments rescheduling the program thread in response to the instruction when the parameter equals a third value, wherein the third value is different from the first and second values. In other embodiments the third value is a negative one. In yet other embodiments the third value is an odd value.
In still another aspect of the invention, in a processor enabled to support multiple program threads, a method is provided comprising executing an instruction that accesses a parameter related to thread scheduling, wherein the instruction is included in a program thread, and suspending the program thread from execution in response to the instruction when the parameter equals a first value. In some embodiments of this method there is a further step for rescheduling the program thread in response to the instruction when the parameter equals a second value, wherein the second value is different from the first value.
In yet another aspect, in a processor enabled to support multiple program threads, a method is provided comprising executing an instruction that accesses a parameter related to thread scheduling, wherein the instruction is included in a program thread, and rescheduling the program thread in response to the instruction when the parameter equals a first value. In some embodiments of this method there is a further a step for deallocating the program thread in response to the instruction when the parameter equals a second value, wherein the second value is different from the first value.
In embodiments of the invention described in enabling detail below, for the first time a truly robust system for fine-grained multithreading is provided minimizing overhead for creating and destroying threads.
In one preferred embodiment of the present invention, a processor architecture includes an instruction set comprising features, functions and instructions enabling multithreading on a compatible processor. The invention is not limited to any particular processor architecture and instruction set, but for exemplary purposes the well-known MIPS architecture, instruction set, and processor technology (collectively, “MIPS technology”) is referenced, and embodiments of the invention described in enabling detail below are described in context with MIPS technology. Additional information regarding MIPS technology (including documentation referenced below) is available from MIPS Technologies, Inc. (located in Mountain View California) and on the Web at www.mips.com (the company's website).
The terms “processor” and “digital processor” as used herein are intended to mean any programmable device (e.g., microprocessor, microcontroller, digital signal processor, central processing unit, processor core, etc.) in hardware (e.g., application specific silicon chip, FPGA, etc.), software (e.g., hardware description language, C, C+, etc.) or any other instantiation (or combination) thereof.
The terms “thread” and “program thread” as used herein have the same meaning.
General Description
A “thread context” for purposes of description in embodiments of this invention is a collection of processor state necessary to describe the state of execution of an instruction stream in a processor. This state is typically reflected in the contents of processor registers. For example, in a processor that is compatible with the industry-standard MIPS32 and/or MIPS64 Instruction Set Architectures (a “MIPS Processor”), a thread context comprises a set of general purpose registers (GPRs), Hi/Lo multiplier result registers, some representation of a program counter (PC), and some associated privileged system control state. The system control state is retained in that portion of a MIPS Processor typically referred to as coprocessor zero (“CP0”), and is largely maintained by system control registers and (when used) a Translation Lookaside Buffer (“TLB”). In contrast, a “processor context” is a larger collection of processor state, which includes at least one thread context. Referring again to a MIPS Processor, a processor context in this case would include at least one thread context (as described above) as well as the CP0 and system state necessary to describe an instantiation of the well-known MIPS32 or MIPS64 Privileged Resource Architecture (“PRA”). (In brief, a PRA is a set of environments and capabilities upon which an instruction set architecture operates. The PRA provides the mechanisms necessary for an operating system to manage the resources of a processor; e.g., virtual memory, caches, exceptions and user contexts.) In accordance with one embodiment of the present invention, a multithreading application-specific extension (“Multithreading ASE”) to an instruction set architecture and PRA allows two distinct, but not mutually-exclusive, multithreading capabilities to be included within a given processor. First, a single processor can contain some number of processor contexts, each of which can operate as an independent processing element through the sharing of certain resources in the processor and supporting an instruction set architecture. These independent processing elements are referred to herein as Virtual Processing Elements (“VPEs”). To software, an N VPE processor looks exactly like an N-way symmetric multiprocessor (“SMP”). This allows existing SMP-capable operating systems to manage the set of VPEs, which transparently share the processor's execution units.
FIG, 3 illustrates this capability with single processor 301 supporting a first VPE (“VPE0”) that includes register state zero 302 and system coprocessor state zero 304. Processor 301 also supports a second VPE (“VPE1”) that includes register state one 306 and system coprocessor state one 308. Those portions of processor 301 shared by VPE0 and VPE1 include fetch, decode, and execute pipelines, and caches 310. The SMP-capable operating system 320, which is shown running on processor 301, supports both VPE0 and VPE1. Software Process A 322 and Process C 326 are shown running separately on VPE0 and VPE1, respectively, as if they were running on two different processors. Process B 324 is queued and may run on either VPE0 or VPE1.
The second capability allowed by the Multithreading ASE is that each processor or VPE can also contain some number of thread contexts beyond the single thread context required by the base architecture. Multi-threaded VPEs require explicit operating system support, but with such support they provide a lightweight, fine-grained multithreaded programming model wherein threads can be created and destroyed without operating system intervention in typical cases, and where system service threads can be scheduled in response to external conditions (e.g., events, etc.) with zero interrupt latency.
FIG, 4 illustrates this second capability with processor 401 supporting a single VPE that includes register state 402, 404 and 406 (supporting three threads 422), and system coprocessor state 408. Unlike
A thread context may be in one of four states. It may be free, activated, halted, or wired. A free thread context has no valid content and cannot be scheduled to issue instructions. An activated thread context will be scheduled according to implemented policies to fetch and issue instructions from its program counter. A halted thread context has valid content, but is inhibited from fetching and issuing instructions. A wired thread context has been assigned to use as Shadow Register storage, which is to say that is held in reserve for the exclusive use of an exception handler, to avoid the overhead of saving and restoring register contexts in the handler. A free thread context is one that is neither activated, nor halted, nor wired. Only activated thread contexts may be scheduled Only free thread contexts may be allocated to create new threads.
To allow for fine-grained synchronization of cooperating threads, an inter-thread communication (“ITC”) memory space is created in virtual memory, with empty/full bit semantics to allow threads to be blocked on loads or stores until data has been produced or consumed by other threads. Thread creation/destruction, and synchronization capabilities function without operating system intervention in the general case, but the resources they manipulate are all vitalable via an operating system. This allows the execution of multithreaded programs with more virtual threads than there are thread contexts on a VPE, and for the migration of threads to balance load in multiprocessor systems.
At any particular point in its execution, a thread is bound to a particular thread context on a particular VPE. The index into that VPE's set of thread contexts provides a unique identifier at that point in time. But context switching and migration can cause a single sequential thread of execution to have a series of different thread indices, for example on a series of different VPES.
Dynamic binding of thread contexts, TLB entries, and other resources to multiple VPEs on the same processor is performed in a special processor reset configuration state. Each VPE enters its reset vector exactly as if it were a separate processor.
Multithreaded Execution and Exception Model
The Multithreading ASE does not impose any particular implementation or scheduling model on the execution of parallel threads and VPEs. Scheduling may be round-robin, time-sliced to an arbitrary granularity, or simultaneous. An implementation must not, however, allow a blocked thread to monopolize any shared processor resource which could produce a hardware deadlock.
In a MIPS Processor, multiple threads executing on a single VPE all share the same system coprocessor (CP0), the same TLB and the same virtual address space. Each thread has an independent Kernel/Supervisor/User state for the purposes of instruction decode and memory access. When an exception is taken, all threads other than the one taking the exception are stopped and suspended until the EXL and ERL bits of the Status word are cleared, or, in the case of an EJTAG Debug exception, the Debug state is exited. The Status word resides in the status register, which is located in CP0. Details regarding the EXL and ERL bits as well as EJTAG debug exceptions may be found in the following two publications, each of which is available from MIPS Technologies, Inc. and hereby incorporated by reference in its entirety for all purposes: MIPS32™ Architecture for Programmers Volume III: The MIPS32™ Privileged Resource Architecture, Rev. 2.00, MIPS Technologies, Inc. (2003), and MIPS64™ Architecture for Programmers Volume III. The MIPS64™ Privileged Resource Architecture, Rev. 2.00, MIPS Technologies, Inc. (2003).
Exception handlers for synchronous exceptions caused by the execution of an instruction stream, such as TLB miss and floating-point exceptions, are executed by the thread executing the instruction stream in question. When an unmasked asynchronous exception, such as an interrupt, is raised to a VPE, it is implementation dependent which thread executes the exception handler.
Each exception is associated with a thread context, even if shadow register sets are used to run the exception handler. This associated thread context is the target of all RDPGPR and WRPGPR instructions executed by the exception handler. Details regarding the RDPGPR and WRPGPR instructions (used to access shadow registers) may be found in the following two publications, each of which is available from MIPS Technologies, Inc. and hereby incorporated by reference in its entirety for all purposes: MIPS32™ Architecture for Programmers Volume II. The MIPS32™ Instruction Set, Rev. 2.00, MIPS Technologies, Inc. (2003), and MIPS64™ Architecture for Programmers Volume II. The MIPS64™ Instruction Set, Rev. 2.00, MIPS Technologies, Inc. (2003).
The Multithreading ASE includes two exception conditions. The first of these is a Thread Unavailable condition, wherein a thread allocation request cannot be satisfied. The second is a Thread Underflow condition, wherein the termination and de-allocation of a thread leaves no threads allocated on a VPE. These two exception conditions are mapped to a single new Thread exception. They can be distinguished based on CP0 register bits set when the exception is raised.
Instructions
The Multithreading ASE in a preferred embodiment includes seven instructions. FORK and YIELD instructions control thread allocation, deallocation, and scheduling, and are available in all execution modes if implemented and enabled. MFTR and MTTR instructions are system coprocessor (Cop0) instructions available to privileged system software for managing thread state. A new EMT instruction and a new DMT instruction are privileged Cop0 instructions for enabling and disabling multithreaded operation of a VPE. Finally, a new ECONF instruction is a privileged Cop0 instruction to exit a special processor configuration state and re-initialize the processor.
FORK—Allocate and Schedule a New Thread
The FORK instruction causes a free thread context to be allocated and activated. Its format 500 is shown in
YIELD—De-schedule and Conditionally Deallocate a Thread
The YIELD instruction causes the current thread to be de-scheduled. Its format 600 is shown in
The YIELD instruction takes a single operand value from, for example, a GPR identified in field 602 (rs). A GPR is used in a preferred embodiment, but in alternative embodiments the operand value may be stored in and retrieved from essentially any data storage device (e.g., non-GPR register, memory, etc.) accessible to the system. In one embodiment, contents of GPR rs can be thought of as a descriptor of the circumstances under which the issuing thread should be rescheduled If the contents of GPR rs is zero (i.e., the value of the operand is zero), as shown in step 3202 of
Referring to table 700, bits 15 to 10 of the GPR rs indicate hardware interrupt signals presented to the processor, bits 9 and 8 indicate software interrupts generated by the processor, bits 7 and 6 indicate the operation of the Load Linked and Store Conditional synchronization primitives of the MIPS architecture, and bits 5 to 2 indicate non-interrupt external signals presented to the processor.
If the content of GPR rs is even (i.e., bit zero is not set), and any other bit in the qualifier mask of GPR rs is set (step 3208), the thread is suspended until at least one corresponding condition is satisfied. If and when such a situation occurs, the thread is rescheduled (step 3210) and resumes execution at the instruction following the YIELD. This enabling is unaffected by the CP0.Status.IMn interrupt mask bits, so that up to 10 external conditions (e.g., events, etc.) encoded by bits 15 to 10 and 5 to 2 (as shown in
In EIC interrupt mode, the IP2-IP7 bits encode the value of the highest priority enabled interrupt, rather than express a vector of orthogonal indications. The GPR rs bits associated with IP2-IP7 in a YIELD instruction when the processor is using EIC interrupt mode can thus no longer be used to re-enable thread scheduling on a specific external event. In EIC mode, only the system-dependent external event indications (i.e., bits 5 to 2 of the GPR rs of the present embodiment) should be used as YIELD qualifiers. The EIC interrupt mode and IP2-IP7 bits are further described in the following publications as fully identified and incorporated above: MIPS32™ Architecture for Programmers Volume III. The MIPS32™ Privileged Resource Architecture, and MIPS64™ Architecture for Programmers Volume III. The MIPS64™ Privileged Resource Architecture.
If the execution of a YIELD results in the de-allocation of the last allocated thread on a processor or VPE, a Thread Exception, with an underflow indication in the ThreadStatus register of CP0 (shown in FIG, 18 and described below), is raised on the YIELD instruction.
The foregoing embodiment utilizes the operand contained in the GPR rs of the YIELD instruction as a thread-scheduling parameter. In this case, the parameter is treated as a 15-bit vector of orthogonal indications (referring to
Other embodiments of this instruction may treat such a thread-scheduling parameter as containing one or more multi-bit value fields so that a thread can specify that it will yield on a single event out of a large (e.g., 32-bit, or larger) event name space. In such an embodiment, at least the bits associated with the one target event would be accessed by the subject YIELD instruction. Of course, additional bit fields could be passed to the instruction (associated with additional events) as desired for a particular embodiment.
Other embodiments of the YIELD instruction may include a combination of the foregoing bit vector and value fields within a thread-scheduling parameter accessed by the instruction, or other application-specific modifications and enhancements to (for example) satisfy the needs of a specific implementation. Alternative embodiments of the YIELD instruction may access such a thread-scheduling parameter as described above in any conventional way; e.g., from a GPR (as shown in
MFTR—Move From Thread Register
The MFTR instruction is a privileged (Cop0) instruction which allows an operating system executing on one thread to access a different thread context. Its format 800 is shown in
The thread context to be accessed is determined by the value of the AlternateThread field of the ThreadControl register of CP0, which is shown in
MTTR—Move To Thread Register
The MTTR instruction is the inverse of MFTR. It is a privileged Cop0 instruction which copies a register value from the thread context of the current thread to a register within another thread context. Its format 1000 is shown in
The thread context to be accessed is determined by the value of the AlternateThread field of the ThreadControl register of CP0, which is shown in
EMT—Enable Multithreading
The EMT instruction is a privileged Cop0 instruction which enables the concurrent execution of multiple threads by setting the TE bit of the ThreadControl register of CP0, which is shown in
DMT—Disable Multithreading
The DMT instruction is a privileged Cop0 instruction which inhibits the concurrent execution of multiple threads by clearing the TE bit of the ThreadControl register of CP0, which is shown in
All threads other than the thread issuing the DMT instruction are inhibited from further instruction fetch and execution. This is independent of any per-thread halted state. The value of the ThreadControl register, containing the TE (Threads Enabled) bit value prior to the execution of the DMT, is returned in register rt.
ECONF—End Processor Configuration
The ECONF instruction is a privileged Cop0 instruction which signals the end of VPE configuration and enables multi-VPE execution Its format 1400 is shown in
When an ECONF is executed, the VPC bit of the Config3 register (described below) is cleared, the MVP bit of this same register becomes read-only at its current value, and all VPEs of a processor, including the one executing the ECONF, take a Reset exception.
Privileged Resources
The table 1500 of
New Privileged Resources
(A) ThreadControl Register (Coprocessor 0 Register 7, Select 1)
The ThreadControl register is instantiated per VPE as part of the system coprocessor. Its layout 1600 is shown in
(B) ThreadStatus Register (Coprocessor 0 Register 12, Select 4)
The ThreadStatus register is instantiated per thread context. Each thread sees its own copy of ThreadStatus, and privileged code can access those of other threads via MFTR and MTTR instructions. Its layout 1800 is shown in
Writing a one to the Halted bit of an activated thread causes an activated thread to cease fetching instructions and to set its internal restart PC to the next instruction to be issued. Writing a zero to the Halted bit of an activated thread allows the thread to be scheduled, fetching and executing from the internal restart PC address. A one in either the Activated bit or the Halted bit of a non-activated thread prevents that thread from being allocated and activated by a FORK instruction.
(C) ThreadContext Register (Coprocessor 0 Register 4, Select 1)
The ThreadContext register 2000 is instantiated per-thread, with the same width as the processor GPRs, as shown in
(D) ThreadConfig Register (Coprocessor 0 Register 6, Select 1)
The ThreadConfig register is instantiated per-processor or VPE. Its layout 2100 is shown in
The WiredThread field of ThreadConfig allows the set of thread contexts available on a VPE to be partitioned between Shadow Register sets and parallel execution threads. Thread contexts with indices less than the value of the WiredThread register are available as shadow register sets.
(E) ThreadSchedule Register (Coprocessor 0 Register 6, Select 2)
The ThreadSchedule register is optional, but when implemented is preferably implemented per-thread. Its layout 2300 is shown in
The Schedule Vector (which, as shown, is 32 bits wide in a preferred embodiment) is a description of the requested issue bandwidth scheduling for the associated thread. In this embodiment, each bit represents {fraction (1/32)} of the issue bandwidth of the processor or VPE, and each bit location represents a distinct slot in a 32-slot scheduling cycle.
If a bit in a thread's ThreadSchedule register is set, that thread has a guarantee of the availability of one corresponding issue slot for every 32 consecutive issues possible on the associated processor or VPE. Writing a 1 to a bit in a thread's ThreadSchedule register when some other thread on the same processor or VPE already has the same ThreadSchedule bit set will result in a Thread exception. Although 32 bits is the preferred width of the ThreadSchedule register, it is anticipated that this width may be altered (i.e., increased or decreased) when used in other embodiments.
(F) VPESchedule Register (Coprocessor 0 Register 6, Select 3)
The VPESchedule register is optional, and is preferably instantiated per VPE. It is writable only if the MVP bit of the Config3 register is set (see,
The Schedule Vector (which, as shown, is 32 bits wide in a preferred embodiment) is a description of the requested issue bandwidth scheduling for the associated VPE. In this embodiment, each bit represents {fraction (1/32)} of the issue total bandwidth of a multi VPE processor, and each bit location represents a distinct slot in a 32-slot scheduling cycle.
If a bit in a VPE's VPESchedule register is set, that thread has a guarantee of the availability of one corresponding issue slot for every 32 consecutive issues possible on the processor. Writing a 1 to a bit in a VPE's VPESchedule register when some other VPE already has the same VPESchedule bit set will result in a Thread exception.
Issue slots not specifically scheduled by any thread are free to be allocated to any runnable VPE/thread according to the current default thread scheduling policy of the processor (e.g., round robin, etc.).
The VPESchedule register and the ThreadSchedule register create a hierarchy of issue bandwidth allocation. The set of VPESchedule registers assigns bandwidth to VPEs as a proportion of the total available on a processor or core, while the ThreadSchedule register assigns bandwidth to threads as a proportion of that which is available to the VPE containing the threads.
Although 32 bits is the preferred width of the VPESchedule register, it is anticipated that this width may be altered (i.e., increased or decreased) when used in other embodiments.
(G) The Config4 Register (Coprocessor 0 Register 16, Select 4)
The Config4 Register is instantiated per-processor. It contains configuration information necessary for dynamic multi-VPE processor configuration. If the processor is not in a VPE configuration state (i.e., the VMC bit of the Config3 register is set), the value of all fields except the M (continuation) field is implementation-dependent and may be unpredictable. Its layout 2500 is shown in
Modifications to Existing Privileged Resource Architecture
The Multithreading ASE modifies some elements of current MIPS32 and MIPS64PRA.
(A) Status Register
The CU bits of the Status register take on additional meaning in a multithreaded configuration. The act of setting a CU bit is a request that a coprocessor context be bound to thread associated with the CU bit. If a coprocessor context is available, it is bound to the thread so that instructions issued by the thread can go to the coprocessor, and the CU bit retains the 1 value written to it. If no coprocessor context is available, the CU bit reads back as 0. Writing a 0 to a set CU bit causes any associated coprocessor to be deallocated.
(B) Cause Register
There is a new Cause register ExcCode value required for the Thread exceptions, as shown in
(C) EntryLo Register
A previously reserved cache attribute becomes the ITC indicator, as shown in
(D) Config3 Register
There are new Config3 register fields defined to express the availability of the Multithreading ASE and of multiple thread contexts, as shown in table 2900 of
(E) EBase
The previously reserved bit 30 of the EBase register becomes a VPE inhibit bit per VPE context, as is illustrated in
(F) SRSCtl
The formerly preset HSS field now generated as a function of the ThreadConfig WiredThread field.
Thread Allocation and Initialization Without FORK
The procedure for an operating system to create a thread “by hand” in a preferred embodiment is:
The newly allocated thread will then be schedulable. The steps of executing DMT, setting the new thread's Halted bit, and executing EMT can be skipped if EXL or ERL are set during the procedure, as they implicitly inhibit multithreaded execution.
Thread Termination and Deallocation without YIELD
The procedure for an operating system to terminate the current thread in a preferred embodiment is:
The normal procedure is for a thread to terminate itself in this manner. One thread, running in a privileged mode, could also terminate another, using MTTR instructions, but it would present an additional problem to the OS to determine which thread context should be deallocated and at what point the state of the thread's computation is stable.
Inter-Thread Communication Storage
Inter-Thread Communication (ITC) Storage is an optional capability which provides an alternative to Load-Linked/Store- Conditional synchronization for fine-grained multi-threading. It is invisible to the instruction set architecture, as it is manipulated by loads and stores, but it is visible to the Privileged Resource Architecture, and it requires significant microarchitectural support.
References to virtual memory pages whose TLB entries are tagged as ITC storage resolve to a store with special attributes. Each page maps a set of 1-128 64-bit storage locations, each of which has an Empty/Full bit of state associated with it, and which can be accessed in one of 4 ways, using standard load and store instructions. The access mode is encoded in the least significant (and untranslated) bits of the generated virtual address, as shown in table 3100 of
Each storage location could thus be described by the C structure:
where all four of the locations reference the same 64 bits of underlying storage. References to this storage may have access types of less than 64 bits (e.g. LW, LH, LB), with the same Empty/Full protocol being enforced on a per-access basis.
Empty and Full bits are distinct so that decoupled multi-entry data buffers, such as FIFOs can be mapped into ITC storage.
ITC storage can be saved and restored by copying the {bypass_location, ef_state} pair to and from general storage. While 64 bits of bypass_location must be preserved, strictly speaking, only the least significant bits of the ef_state need to be manipulated. In the case of multi-entry data buffers, each location must be read until Empty to drain the buffer on a copy.
The number of locations per 4K page and the number of ITC pages per VPE are configuration parameters of the VPE or processor. The “physical address space” of ITC storage can be made global across all VPEs and processors in a multiprocessor system, such that a thread can synchronize on a location on a different VPE from the one on which it is executing. Global ITC storage addresses are derived from the CPUNum field of each VPE's EBase register. The 10 bits of CPUNum correspond to 10 significant bits of the ITC storage address. Processors or cores designed for uniprocessor applications need not export a physical interface to the ITC storage, and can treat it as a processor-internal resource.
Multi-VPE Processors
A core or processor may implement multiple VPEs sharing resources such as functional units. Each VPE sees its own instantiation of the MIPS32 or MIPS64 instruction and privileged resource architectures. Each sees its own register file or thread context array, each sees its own CP0 system coprocessor and its own TLB state. Two VPEs on the same processor are indistinguishable to software from a 2-CPU cache-coherent SMP multiprocessor.
Each VPE on a processor sees a distinct value in the CPUNum field of the Ebase register of CP0.
Processor architectural resources such as thread context and TLB storage and coprocessors may be bound to VPEs in a hardwired configuration, or they may be configured dynamically in a processor supporting the necessary configuration capability.
Reset and Virtual Processor Configuration
To be backward compatible with the MIPS32 and MIPS64 PRAs, a configurably multithreaded//multi-VPE processor must have a sane default thread/VPE configuration at reset This would typically be, but need not necessarily be, that of a single VPE with a single thread context. The MVP bit of the Config3 register can be sampled at reset time to determine if dynamic VPE configuration is possible. If this capability is ignored, as by legacy software, the processor will behave as per specification for the default configuration.
If the MVP bit is set, the VPC (Virtual Processor Configuration) bit of the Config3 register can be set by software. This puts the processor into a configuration state in which the contents of the Config4 register can be read to determine the number of available VPE contexts, thread contexts, TLB entries, and coprocessors, and certain normally read-only “presef” fields of Config registers that become writable. Restrictions may be imposed on configuration state instruction streams, e.g. they may be forbidden to use cached or TLB-mapped memory addresses.
In the configuration state, the total number of configurable VPEs is encoded in the PVPE field of the Config4 register. Each VPE can be selected by writing its index into the CPUNum field of the EBase register. For the selected VPE, the following register fields can potentially be set by writing to them.
Not all of the above configuration parameters need be configurable. For example, the number of ITC locations per page may be fixed, even if the ITC pages per VPE is configurable, or both parameters may be fixed, FPUs may be pre-allocated and hardwired per VPE, etc.
Coprocessors are allocated to VPEs as discrete units. The degree to which a coprocessor is multithreaded should be indicated and controlled via coprocessor-specific control and status registers.
A VPE is enabled for post-configuration execution by clearing the VPI inhibit bit in the EBase register.
The configuration state is exited by issuing an ECONF instruction. This instruction causes all uninhibited VPEs to take a reset exception and begin executing concurrently. If the MVP bit of the Config3 register is cleared during configuration and latched to zero by an ECONF instruction, the VPC bit can no longer be set, and the processor configuration is effectively frozen until the next processor reset. If MVP remains set, an operating system may re-enter the configuration mode by again setting the VPC bit. The consequences to a running VPE of the processor re-entering configuration mode may be unpredictable.
Quality of Service Scheduling for Multithreaded Processors
This specification up to the present point describes an application specific extension for a MIPS compatible system to accommodate multithreading. As previously stated, the MIPS implementation described is exemplary, and not limiting, as the functionality and mechanisms described may be applied in other than MIPS systems.
An issue visited in the background section, that of special service in multithreading for real-time and near real-time threads, has been briefly touched upon in the foregoing discussion directed to the ThreadSchedule register (
Background
Networks designed for transporting multimedia data evolved a concept of Quality of Service (“QoS”) to describe the need for different policies to be applied to different data streams in a network. Speech connections, for example, are relatively undemanding of bandwidth, but cannot tolerate delays beyond a few tens of milliseconds. QoS protocols in broadband multimedia networks ensure that time-critical transfers get whatever special handling and priority is necessary to ensure timely delivery.
One of the primary objections raised to combining “RISC” and “DSP” program execution on a single chip is that guaranteeing the strict real-time execution of the DSP code is far more difficult in a combined multi-tasking environment. The DSP applications can thus be thought of as having a “QoS” requirement for processor bandwidth.
Multithreading and QoS
There are a number of ways to schedule issuing of instructions from multiple threads. Interleaved schedulers will change threads every cycle, while blocking schedulers will change threads whenever a cache miss or other major stall occurs. The Multithreading ASE described in detail above, provides a framework for explicitly multithreaded processors that attempts to avoid any dependency on a specific thread scheduling mechanism or policy. However, scheduling policy may have a huge impact on what QoS guarantees are possible for the execution of the various threads.
A DSP-extended RISC becomes significantly more useful if QoS guarantees can be made about the real-time DSP code. Implementing multithreading on such a processor, such that the DSP code is running in a distinct thread, perhaps even a distinct virtual processor, and such that the hardware scheduling of the DSP thread can be programmably determined to provide assured QoS, logically removes a key barrier to acceptance of a DSP-enhanced RISC paradigm.
QoS Thread Scheduling Algorithms
Quality of Service thread scheduling can be loosely defined as a set of scheduling mechanisms and policies which allow a programmer or system architect to make confident, predictive statements about the execution time of a particular piece of code. These statements in general have the form “This code will execute in no more than Nmax and no less than Nmin cycles”. In many cases, the only number of practical consequence is the Nmax number, but in some applications, running ahead of schedule is also problematic, so Nmin may also matter. The smaller the range between Nmin and Nmax, the more accurately the behavior of the overall system can be predicted.
Simple Priority Schemes
One simple model that has been proposed for providing some level of QoS to multithreaded issue scheduling is simply to assign maximal priority to a single designated real-time thread, such that if that thread is runnable, it will always be selected to issue instructions. This will provide the smallest value of Nmin, and might seem to provide the smallest possible value of Nmax for the designated thread, but there are some adverse consequences.
Firstly, only a single thread can have any QoS assurance in such a scheme. The algorithm implies that the Nmax for any code in a thread other than the designated real-time thread becomes effectively unbounded. Secondly, while the Nmin number for a code block within the designated thread is minimized, exceptions must be factored into the model. If the exceptions are taken by the designated thread, the Nmax value becomes more complex, and in some cases impossible to determine. If the exceptions are taken by threads other than the designated thread, Nmax is strictly bounded for code in the designated thread, but the interrupt response time of the processor becomes unbounded.
While such priority schemes may be useful in some cases, and may have some practical advantages in hardware implementation, they do not provide a general QoS scheduling solution.
Reservation-based Schemes
An alternative, more powerful and unique thread-scheduling model is based on reserving issue slots. The hardware scheduling mechanisms in such a scheme allow one or more threads to be assigned N out of each M consecutive issue slots. Such a scheme does not provide as low an Nmin value as a priority scheme for a real-time code fragment in an interrupt-free environment, but it does have other virtues.
One simple form of reservation scheduling assigns every Nth issue slot to a real-time thread. As there is no intermediate value of N between 1 and 2, this implies that real-time threads in a multithreading environment can get at most 50% of a processor's issue slots. As the real-time task may consume more than 50% of an embedded processor's bandwidth, a scheme which allows more flexible assignment of issue bandwidth is highly desirable.
Hybrid Thread Scheduling with QoS
The Multithreading system described above is deliberately scheduling-policy-neutral, but can be extended to allow for a hybrid scheduling model. In this model, real-time threads may be given fixed scheduling of some proportion of the thread issue slots, with the remaining slots assigned by the implementation-dependent default scheduling scheme.
Binding Threads to Issue Slots
In a processor instructions are issued sequentially at a rapid rate. In a multithreading environment one may quantify the bandwidth consumed by each thread in a mix by stating the proportional number of slots each thread issues in a given fixed number of slots. Conversely, the inventor recognizes that one may arbitrarily state a fixed number of slots, and predicate a means of constraining the processor to reserve a certain number of slots of the fixed number for a specific thread. One could then designate a fixed fraction of bandwidth guaranteed to a real-time thread.
Clearly one could assign slots proportionally to more than one real-time thread, and the granularity under which this scheme would operate is constrained by the fixed number of issue slots over which the proportions are made. For example, if one selects 32 slots, then any particular thread may be guaranteed from {fraction (1/32)} to {fraction (32/32)} of the bandwidth.
Perhaps the most general model, then, for assigning fixed issue bandwidth to threads is to associate each thread with a pair of integers, {N, D} which form the numerator and denominator of a fraction of issue slots assigned to the thread, e.g. {fraction (1/2, 4/5)}. If the range of integers allowed is sufficiently large, this would allow almost arbitrarily fine-grained tuning of thread priority assignments, but it has some substantial disadvantages. One problem is that the hardware logic to convert a large set of pairs, {{N0, D0}, {N1, D1}, . . . .{Nn, Dn}} into an issue schedule is nontrivial, and error cases in which more than 100% of slots are assigned are not necessarily easy to detect. Another is that, while such a scheme allows specification that, over the long run, a thread will be assigned N/D of the issue slots, it does not necessarily allow any statements to be made as to which issue slots will be assigned to a thread over a shorter subset code fragment.
Therefor, in a preferred embodiment of the present invention, instead of an integer pair, each thread for which real-time bandwidth QoS is desired is associated with a bit-vector which represents the scheduling slots to be allocated to that thread. In the preferred embodiment, this vector is visible to system software as the contents of a ThreadSchedule Register (
Scheduling conflicts in this embodiment can be detected fairly simply, in that no bit should be set in the ThreadSchedule Register of more than one thread That is, if a particular bit is set for one thread, that bit must be zero for all other threads to which issue masks are assigned. Conflicts are thus relatively easy to detect.
The issue logic for real-time threads is relatively straightforward: Each issue opportunity is associated with a modulo-32 index, which can be sent to all ready threads, at most one of which will be assigned the associated issue slot. If there is a hit on the slot, the associated thread issues its next instruction. If no thread owns the slot, the processor selects a runnable non-real-time thread.
ThreadSchedule Register implementations of less than 32-bits would reduce the size of the per-thread storage and logic, but would also reduce the scheduling flexibility. In principle, the register could also be enlarged to 64-bits, or even implemented (in the case of a MIPS Processor) as a series of registers at incrementing select values in the MIPS32 CP0 register space to provide much longer scheduling vectors.
Exempting Threads from Interrupt Service
As noted above, interrupt service can introduce considerable variability in the execution time of the thread which takes the exception. It is therefore desirable to exempt threads requiring strict QoS guarantees from interrupt service. This is accomplished in a preferred embodiment with a single bit per thread, visible to the operating system, which causes any asynchronous exception raised to be deferred until a no- exempt thread is scheduled (i.e., bit IXMT of the ThreadStatus Register; see,
Issue Slot Allocation to Threads versus Virtual Processing Elements
The Multithreading ASE described in enabling detail above describes a hierarchical allocation of thread resources, wherein some number of Virtual Processing Elements (VPEs) each contain some number of threads. As each VPE has an implementation of CP0 and the privileged resource architecture (when configured on a MIPS Processor), it is not possible for the operating systems software (“OS”) running on one VPE to have direct knowledge and control of which issue slots have been requested on another VPE. Therefore the issue slot name space of each VPE is relative to that VPE, which implies a hierarchy of issue slot allocation.
Referring to
When a VPE is granted an issue, it employs similar logic at the VPE level. Referring again to
Referring to
In accordance with the foregoing, , each VPE in a preferred embodiment, for example VPE 0 (3406) and VPE 1 (3404) in
Also in accordance with the foregoing, the slots assigned to threads within a VPE are assigned from the allocation given to that VPE. To give a concrete example, if a processor has two VPEs configured, as is shown in
Thus the value of the VPESchedule register associated with each VPE determines which processing slots go to each VPE. Specific threads are assigned to each VPE, such as Thread 0 and Thread 1 shown in VPE 0. Other threads not shown are similarly assigned to VPE 1. Associated with each thread there is a ThreadSchedule register, for example register 3418 for Thread 0 and register 3420 for Thread 1. The value of the ThreadSchedule registers determines the allocation of processing slots for each Thread assigned to a VPE.
Schedulers 3402 and 3412 may be constructed from simple combinational logic to carry out the functions set out above, and constructing these schedulers will be within the skill of the skilled artisan without undue experimentation, given the disclosure provided herein. They may, for example, be constructed in any conventional way, such as by combinational logic, programmable logic, software, and so forth, to carry out the functions described.
Further Refinements
The embodiment described thus far for fixed 32-bit ThreadSchedule and VPESchedule registers does not allow for allocations of exact odd fractions of issue bandwidth. A programmer wishing to allocate exactly one third of all issue slots to a given thread would have to approximate to {fraction (10/32)} or b {fraction (11/32)}. A further programmable. mask or length register in one embodiment allows the programmer to specify that a subset of the bits in the ThreadSchedule and/or VPESchedule Register(s) be used by the issue logic before restarting the sequence. In the example case, the programmer specifies that only 30 bits are valid, and programs the appropriate VPESchedule and/or ThreadSchedule Registers with 0x24924924.
The Multithreading ASE described in this application may, of course, be embodied in hardware; e.g., within or coupled to a Central Processing Unit (“CPU”), microprocessor, microcontroller, digital signal processor, processor core, System on Chip (“SOC”), or any other programmable device. Additionally, the Multithreading ASE may be embodied in software (e.g., computer readable code, program code, instructions and/or data disposed in any form, such as source, object or machine language) disposed, for example, in a computer usable (e.g., readable) medium configured to store the software. Such software enables the function, fabrication, modeling, simulation, description and/or testing of the apparatus and processes described herein. For example, this can be accomplished through the use of general programming languages (e.g., C, C++), GDSII databases, hardware description languages (HDL) including Verilog HDL, VHDL, AHDL (Altera HDL) and so on, or other available programs, databases, and/or circuit (i.e., schematic) capture tools. Such software can be disposed in any known computer usable medium including semiconductor, magnetic disk, optical disc (e.g., CD-ROM, DVD-ROM, etc.) and as a computer data signal embodied in a computer usable (e.g., readable) transmission medium (e.g., carrier wave or any other medium including digital, optical, or analog- based medium). As such, the software can be transmitted over communication networks including the Internet and intranets.
A Multithreading ASE embodied in software may be included in a semiconductor intellectual property core, such as a processor core (e.g., embodied in HDL) and transformed to hardware in the production of integrated circuits. Additionally, a Multithreading ASE as described herein may be embodied as a combination of hardware and software.
It will be apparent to those with skill in the art that there may be a variety of changes made in the embodiments described herein without departing from the spirit and scope of the invention. For example, the embodiments described have been described using MIPS processors, architecture and technology as specific examples. The invention in various embodiments is more broadly applicable, and not limited specifically to such examples. Further, a skilled artisan might find ways to program the functionality described above in subtle different ways, which should also be within the scope of the invention. In the teachings relative to QoS the contents of the ThreadSchedule and VPESchedule Registers are not limited in length, and many changes may be made within the spirit and scope of the invention.
Therefore, the invention is limited only by the breadth of the claims that follow.
This application claims the benefit of (1) U.S. Provisional Application No. 60/499,180, filed Aug. 28, 2003 and entitled, “Multithreading Application Specific Extension” No. EV 315085819 US), (2) U.S. Provisional Application No. 60/502,358, filed Sep. 12, 2003 and entitled, “Multithreading Application Specific Extension to a Processor Architecture” (Attorney Docket No. 0188.02US, inventor Kevin D. Kissell, Express Mail No. ER 456368993 US), and (3) U.S. Provisional Application No. 60/502,359, filed Sep. 12, 2003 and entitled, “Multithreading Application Specific Extension to a Processor Architecture” (Attorney Docket No. 0188.03US, inventor Kevin D. Kissell, Express Mail No. ER 456369013 US), each of which is incorporated by reference in its entirety for all purposes. This application is related to co-pending U.S. Non-Provisional Application No. (not yet received), filed Oct. 10, 2003 and entitled “Mechanisms for Assuring Quality of Service for Programs Executing on a Multithreaded Processor,” (Attorney Docket No. 3865.01, inventor Kevin D. Kissell, Express Mail No. EL 988990749 US), which is hereby incorporated by reference in its entirety for all purposes.
| Number | Date | Country | |
|---|---|---|---|
| 60499180 | Aug 2003 | US | |
| 60502358 | Sep 2003 | US | |
| 60502359 | Sep 2003 | US |
