Patent Application
20210391528
The present invention relates to the technical field of semiconductor and, in particular, to an integrated structure of crystal resonator and control circuit and an integration method therefor.
A crystal resonator is a device operating on the basis of inverse piezoelectricity of a piezoelectric crystal. As key components in crystal oscillators and filters, crystal resonators have been widely used to create high-frequency electrical signals for performing precise timing, frequency referencing, filtering and other frequency control functions that are necessary for measurement and signal processing systems.
The continuous development of semiconductor technology and increasing popularity of integrated circuits has brought about a trend toward miniaturization of various semiconductor components. However, it is difficult to integrate existing crystal resonators with other semiconductor components, and also the sizes of the existing crystal resonators are relatively large.
For example, commonly used existing crystal resonators include surface-mount ones, in which a base is bonded with a metal solder (or an adhesive) to a cover to form a hermetic chamber in which a piezoelectric vibrator is housed. In addition, electrodes for the piezoelectric vibrator are electrically connected to an associated circuit via solder pads or wires. Further shrinkage of such crystal resonators is difficult, and their electrical connection to the associated circuit by soldering or gluing additionally hinders their miniaturization.
It is an object of the present invention to provide a method for integrating a crystal resonator with a control circuit, which overcomes the above described problems with conventional crystal resonators, i.e., a bulky size and difficult integration.
To solve the problem, the present invention provides a method for integrating a crystal resonator with a control circuit, comprising:
providing a device wafer in which the control circuit is formed
forming, in the device wafer, a lower cavity with an opening at a back side of the device wafer;
forming, on the back side of the device wafer, a piezoelectric vibrator comprising a top electrode, a piezoelectric crystal and a bottom electrode above the lower cavity;
forming, on the device wafer, a connecting structure configured to connect the top electrode and the bottom electrode of the piezoelectric vibrator to the control circuit; and
forming a cap layer on the back side of the device wafer, wherein the cap layer covers the piezoelectric vibrator, and the cap layer together with the piezoelectric vibrator and the device wafer delimits an upper cavity for the crystal resonator.
It is a further object of the present invention to provide an integrated structure of a crystal resonator and a control circuit, comprising:
a device wafer in which the control circuit and a lower cavity are formed, wherein the lower cavity extends through the device wafer;
a piezoelectric vibrator comprising a top electrode, a piezoelectric crystal and a bottom electrode, wherein the piezoelectric vibrator is formed on the back side of the device wafer and in positional correspondence with the lower cavity;
a connecting structure, formed on the device wafer, configured to electrically connect the top and bottom electrodes of the piezoelectric vibrator to the control circuit; and
a cap layer which is formed on the back side of the device wafer and covers the piezoelectric vibrator, wherein the cap layer together with the piezoelectric vibrator and the device wafer delimits an upper cavity.
In the method of the present invention, the lower cavity is so formed in the device wafer that its opening is exposed at the back side of the device wafer, and the piezoelectric vibrator is then formed on the back side of the device wafer in positional correspondence with the lower cavity. Moreover, planar fabrication processes are performed to form the cap layer that encloses the piezoelectric vibrator within the upper cavity, thus resulting in the formation of the crystal resonator and its integration with the control circuit.
Therefore, the method of the present invention allows the crystal resonator to integrate with other semiconductor components with a higher degree of integration, and compared with traditional crystal resonators (e.g., surface-mount ones), the crystal resonator resulting from the method is more compact, miniaturized in size, less costly and less power-consuming. Further, with the support from the support wafer, the piezoelectric vibrator can be formed on the back side of the device wafer and brought into electrical connection with the control circuit from the back side thereof, allowing higher process flexibility for the piezoelectric vibrator.
In these figures,
100 denotes a device wafer; AA, a device area; 100U, a front side; 100D, a back side; 100A, a substrate wafer; 100B, a dielectric layer; 101, a base layer; 102, a buried oxide layer; 103, a top silicon layer; 110, a control circuit; 111, a first circuit; 111T, a first transistor; 111C, a first interconnecting structure; 112, a second circuit; 112T, a first transistor; 112C, a first interconnecting structure; 120, a lower cavity; 211, a first connecting wire; 212, a second connecting wire; 221, a first conductive plug; 222, a second conductive plug; 300, a planarized layer; 400, a support wafer; 500, a piezoelectric vibrator; 510, a bottom electrode; 520, a piezoelectric crystal; 530, a top electrode; 600, a plastic encapsulation layer; 610, a third conductive plug; 700, an upper cavity; 710, a sacrificial layer; 720, a cap layer; 720a, an opening; 721, a cap material layer; and 730, a closure plug.
The core idea of the present invention is to provide a method for integrating a crystal resonator with a control circuit, in which planar fabrication processes are utilized to integrate the piezoelectric vibrator onto a wafer where the control circuit is formed. This, on the one hand, results in a size reduction of the crystal resonator and, on the other hand, allows an increased degree of integration of the crystal resonator with other semiconductor components.
Specific embodiments of the structure and method proposed in the present invention will be described below in greater detail with reference to the accompanying drawings. Features and advantages of the invention will be more apparent from the following description. Note that the accompanying drawings are provided in a very simplified form not necessarily drawn to exact scale, and their only intention is to facilitate convenience and clarity in explaining the disclosed embodiments.
In step S100, with reference to
In this embodiment, at least some of interconnecting structures in the control circuit 110 extend to, and are exposed from, a front side 100U of the device wafer 100. Specifically, the device wafer 100 further has a back side 100D opposing the front side 100U, and the interconnecting structures of the control circuit 110 exposed from the surface of the device wafer 100 can be brought into electrical connection with a subsequently formed piezoelectric vibrator and thus be able to apply an electrical signal to the piezoelectric vibrator.
Further, a plurality of crystal resonators may be formed on the device wafer 100 simultaneously. Accordingly, there may be a plurality of device areas AA defined on the device wafer 100, and each crystal resonator may be formed in a respective one of the device areas AA.
Specifically, the control circuit 110 may include a first circuit 111 and a second circuit 112, which may be electrically connected to a top electrode and a bottom electrode of the subsequently formed piezoelectric vibrator, respectively.
With continued reference to
Similarly, the second circuit 112 may include a second transistor 112T and a second interconnecting structure 112C. The second transistor 112T may be buried within the device wafer 100, and the second interconnecting structure 112C may be connected to the second transistor 112T and extend to the front side 100U of the device wafer 100. The second interconnecting structure 112C may include conductive plugs electrically connected respectively to a gate, source and drain of the second transistor 112T.
The formation of the control circuit 110 may include:
providing a substrate wafer 100A, and forming a first transistor 111T and a second transistor 112T on the substrate wafer 100A; and
then, forming a dielectric layer 100B on the substrate wafer 100A to cover the first transistor 111T and the second transistor 112T, and forming a first interconnecting structure 111C and a second interconnecting structure 112C in the dielectric layer 100B, resulting in the formation of the device wafer 100.
In other words, the device wafer 100 includes the substrate wafer 100A and the dielectric layer 100B formed thereon, and a surface of the dielectric layer 100B facing away from the substrate wafer 100A provides the front side 100U. The first transistor 111T and the second transistor 112T are both formed on the substrate wafer 100A. Additionally, the dielectric layer 100B covers the first transistor 111T and the second transistor 112T, and each of the first interconnecting structure 111C and the second interconnecting structure 112C are formed in the dielectric layer 100B and extends to the surface of the dielectric layer 100B facing away from the substrate wafer.
The substrate wafer 100A may be either a silicon wafer or a silicon-on-insulator (SOI) wafer. In this embodiment, the substrate wafer 100A is a SOI wafer including a base layer 101, a buried oxide layer 102 and a top silicon layer 103, which are sequentially stacked in this order in the direction from the back side 100D to the front side 100U.
It is to be noted that, the interconnecting structures of the control circuit extend to the front side 100U of the device wafer, while the piezoelectric vibrator is to be subsequently formed on the back side 100D of the device wafer. Accordingly, a connecting structure may be subsequently formed to lead connection ports of the control circuit 110 from the front to back side of the device wafer and brought into electrical connection with the subsequently formed piezoelectric vibrator there.
Specifically, the connecting structure may include a first connection for electrically connecting the first interconnecting structure 111C to the bottom electrode of the subsequently formed piezoelectric vibrator and a second connection for electrically connecting the second interconnecting structure 112C to the top electrode of the subsequently formed piezoelectric vibrator.
In addition, the first connection may include a first conductive plug 221 having two ends configured to respectively connect to the first interconnecting structure 111C and the subsequently formed bottom electrode. That is, the first conductive plug 221 may serve to lead a connecting port of the first interconnect 111C in the control circuit from a front side of the control circuit to a back side thereof so as to enable electrical connection of the bottom electrode subsequently formed on the back side of the device wafer to the control circuit from the back side of the control circuit.
Optionally, in this embodiment, the first connection may further include a first connecting wire 211 formed, for example, on the front side of the device wafer. The first connecting wire 211 may connect one end of the first conductive plug 221 to the first interconnecting structure, and the other end of the first conductive plug 221 may be electrically connected to the bottom electrode.
In alternative embodiments, the first connecting wire in the first connection may be formed on the back side of the device wafer. In this case, the first connecting wire may connect one end of the first conductive plug 221 to the bottom electrode, and the other end of the first conductive plug 221 may be electrically connected to the first interconnecting structure in the control circuit.
Similarly, the second connection may include a second conductive plug 222 having two ends configured to respectively connect to the second interconnecting structure 112C and the subsequently formed top electrode. That is, the second conductive plug 222 may serve to lead a connecting port of the second interconnecting structure 112C in the control circuit from the front to back side of the control circuit so as to enable electrical connection of the top electrode subsequently formed on the back side of the device wafer to the control circuit from the back side of the control circuit.
In this embodiment, the second connection may further include a second connecting wire 212 formed, for example, on the front side of the device wafer. The second connecting wire 212 may connect one end of the second conductive plug 222 to the second interconnecting structure, and the other end of the second conductive plug 222 may be electrically connected to the top electrode.
In alternative embodiments, the second connecting wire in the second connection may be formed on the back side of the device wafer. In this case, the second connecting wire may connect one end of the second conductive plug 222 to the top electrode, and the other end of the second conductive plug 222 may be electrically connected to the second interconnecting structure in the control circuit.
The first conductive plug 221 in the first connection and the second conductive plug 222 in the second connection may be formed in a single process step. The first connecting wire 211 in the first connection and the second connecting wire 212 in the second connection may also be formed in a single process step.
Specifically, in this embodiment, the formation of the first connection that includes the first conductive plug 221 and the first connecting wire 211 on the front side of the device wafer and of the second connection that includes the second conductive plug 222 and the second connecting wire 212 on the front side of the device wafer may include the following steps:
Step 1: Etching the device wafer 100 from the front side 100U thereof so that a first connecting hole and a second connecting hole are formed, as shown in
Step 2: Filling a conductive material in the first and second connecting holes, thereby resulting in the formation of the first and second conductive plugs 221, 222, as shown in
In this way, compared with the bottom of the control circuit, the bottoms of both the first and second connecting holes are closer to the back side 100D of the device wafer. As a result, the first and second conductive plugs 221, 222 may both extend from the front side of the control circuit 110 to the back side thereof and be able to be connected to the first and second circuits 111, 112, respectively.
Specifically, the first and second transistors 111T, 112T may be formed within the top silicon layer 103 above the buried oxide layer 102, and the first and second conductive plugs 221, 222 may penetrate sequentially through the dielectric layer 100B and the top silicon layer 103 and terminate at the buried oxide layer 102. Thus, it can be considered that the buried oxide layer 102 may serve as an etch stop layer for the etching process for forming the first and second connecting holes. In this way, high etching accuracy can be achieved for the etching process.
In a subsequent process, the device wafer may be thinned from the back side so that the first and second conductive plugs 221, 222 are exposed from the processed back side and brought into electrical connection with the top and bottom electrodes of the piezoelectric vibrator formed on the back side.
Step 3: Forming the first connecting wire 211 that connects the first conductive plug 221 to the first interconnecting structure 111C and the second connecting wire 212 that connects the second conductive plug 222 to the second interconnecting structure 112C on the front side of the device wafer, as shown in
In alternative embodiments, the first connecting wire in the first connection and the second connecting wire in the second connection are both formed on the back side of the device wafer, the formation of the first connection that includes the first conductive plug and the first connecting wire and of the second connection that includes the second conductive plug and the second connecting wire may include, for example:
first, etching the device wafer from the front side thereof to form a first connecting hole and a second connecting hole;
then, filling the first connecting hole and the second connecting hole with a conductive material, to form the first conductive plug electrically connected to the first interconnecting structure and the second conductive plug electrically connected to the second interconnecting structure respectively;
subsequently, thinning the device wafer from the back side thereof so that the first and second conductive plugs are exposed; and
forming, on the back side of the device wafer, the first connecting wire that is connected to the first conductive plug at one end and configured for electrical connection with the bottom electrode at the other end and the second connecting wire that is connected to the second conductive plug at one end and configured for electrical connection with the top electrode at the other end.
It is to be noted that although the first and second conductive plugs 221, 222 have been described above as being formed from the front side of the device wafer prior to the formation of the first and second connecting wires 221, 212, they may alternatively formed from the back side of the device wafer subsequent to the thinning of the device wafer, as will be described in greater detail below.
In addition, in a subsequent process, a support wafer may be bonded to the front side 100U of the device wafer 100. Accordingly, subsequent to the formation of the first and second connecting wires 221, 212, the method may optionally further include forming, on the front side 100U of the device wafer 100, a planarized layer 300 which provides the device wafer 100 with a flatter bonding surface.
With reference to
In this embodiment, the planarized layer 300 may be formed using a polishing process. In this case, for example, the first and second connecting wires 221, 212 may serve as a polish stop layer such that the top surface of the formed planarized layer 300 is flush with those of the first and second connecting wires 221, 212, and all these surfaces may make up the bonding surface for the device wafer 100.
In step S200, with reference to
In this embodiment, the lower cavity 120 may be formed, for example, using a method including steps S210 and S220 below.
In step S210, with reference to
Specifically, the lower cavity 120 extends deep into the device wafer 100 from the front side 100U. Compared with the bottom of the control circuit, the bottoms of both the first and second connecting holes may are closer to the back side 100D of the device wafer.
In this embodiment, the lower cavity 120 may be formed subsequent to the formation of the planarized layer 300 by etching the planarized layer 300 and the device wafer 100. Specifically, during the formation of the lower cavity 120 the planarized layer 300, the dielectric layer 100B and the top silicon layer 103 are etched sequentially and the etching is stopped at the buried oxide layer 102.
Thus, in this embodiment, the buried oxide layer 102 may serve as an etch stop layer for both the etching process for forming the first and second connecting holes for the first and second conductive plugs 221, 222 and the etching process for forming the lower cavity 120. As a result, bottoms of the resulting first and second conductive plugs 221, 222 are at the same or similar level as that of the lower cavity 120. In this way, when the device wafer is subsequently thinned from the back side 100D, the first and second conductive plugs 221, 222 and the lower cavity 12 can be all exposed.
It is to be noted that the relative positions of the lower cavity 120 and the first and second circuits shown in the figures are merely for illustration, and in practice, the arrangement of the first and second circuits may depend on the actual circuit lay-out requirements. The present invention is not limited in this regard.
In step S220, with reference to
In this embodiment, the lower cavity 120 is bottomed at the buried oxide layer 102. Therefore, as a result of the thinning of the device wafer, the base layer 101 and the buried oxide layer 102 are sequentially stripped away, and the top silicon layer 103 and lower cavity 120 are both exposed. The exposed lower cavity 120 is configured to provide a space in which the subsequently formed piezoelectric vibrator can vibrate. Moreover, the first and second conductive plugs 221, 222 are also exposed as a result of thinning the device wafer. As such, it is made possible to electrically connect the exposed first and second conductive plugs 221, 222 to the subsequently formed piezoelectric vibrator.
Optionally, with reference to
It is to be noted that, in this embodiment, the lower cavity 120 is formed by etching the device wafer 100 from the front side and thinning the device wafer 100 from the back side so that the opening of the lower cavity 120 is exposed at the back side of the device wafer 100.
However, in other embodiments, referring to
With particular reference to
At first, the device wafer is thinned from the back side. In case of the substrate wafer being a SOI wafer, this may involve sequential removal of the base layer and the buried oxide layer of the substrate wafer. Of course, the thinning of the substrate wafer may involve partial removal of the base layer, or complete removal of the base layer and hence exposure of the buried oxide layer, or the like.
Next, the device wafer is etched from the back side so that the lower cavity is formed. It is to be noted that the lower cavity resulting from the etching of the device wafer may have a depth as practically required, and the present invention is not limited in this regard. For example, after the device wafer is thinned and the top silicon layer 103 is exposed, the top silicon layer 103 may be etched to form the lower cavity therein. Alternatively, the etching process may proceed through the top silicon layer 103 and further into the dielectric layer 100B, so that the resulting lower cavity 120 extends from the top silicon layer 103 into the dielectric layer 100B.
It is to be also noted that during the formation of the lower cavity as shown in
As discussed above, in other embodiments, the first conductive plug 221 of the first connection and the second conductive plug 222 of the second connection may be formed from the back side of the device wafer 100 after the thinning of the device wafer.
Specifically, a method for forming the first and second connecting wires on the front side of the device wafer 100, forming the first and second conductive plugs 221, 222 from the back side of the device wafer 100, connecting the first conductive plug 221 to the first connecting wire 211 and connecting the second conductive plug 222 to the second connecting wire 212 may include the steps detailed below.
At first, prior to the bonding of the support wafer 400, the first and second connecting wires 221, 212 that are electrically connected to first and second interconnecting structures, respectively, are formed on the front side of the device wafer 100.
Next, after the device wafer 100 is thinned, it is etched from the back side to form therein first and second connecting holes, both of which extend through the device wafer 100 so that the first and second connecting wires 211, 212 are exposed respectively in the holes.
Subsequently, a conductive material is filled in the first and second connecting holes, resulting in the formation of the first and second conductive plugs 221, 222. The first conductive plug 221 is connected at one end to the first connecting wire 211 and configured for electrical connection with the bottom electrode of the piezoelectric vibrator at the other end. The second conductive plug 222 is connected at one end to the second connecting wire 212 and configured for electrical connection with the top electrode of the piezoelectric vibrator at the other end.
In an alternative embodiment, a method for forming the first and second connecting wires on the back side of the device wafer 100, forming the first and second conductive plugs from the back side of the device wafer 100, connecting the first conductive plug 221 to the first connecting wire and connecting the second conductive plug 222 to the second connecting wire may include the steps detailed below.
At first, the device wafer 100 is thinned from the back side, followed by etching the device wafer 100 from the back side and thus forming first and second connecting holes therein.
Next, a conductive material is filled in the first and second connecting holes, resulting in the formation of the first and second conductive plugs, so that he first conductive plug is electrically connected at one end to the first interconnecting structure, and the second conductive plug is electrically connected at one end to the second interconnecting structure.
Subsequently, the first and second connecting wires are formed on the back side of the device wafer 100, so that one end of the first connecting wire is connected to the other end of the first conductive plug, the other end of the first connecting wire is configured for electrical connection with the bottom electrode, one end of the second connecting wire is connected to the other end of the second conductive plug, and the other end of the second connecting wire is configured for electrical connection with the top electrode.
In step S300, with reference to
Specifically, the formation of the piezoelectric vibrator 500 may include, for example, the steps as follows:
Step 1: Forming the bottom electrode 510 at a predetermined location on the back side of the device wafer 100, as shown in
It is to be noted that in alternative embodiments where the first connecting wire of the first connection is formed on the back side of the device wafer, the bottom electrode 510 may be brought into electrical connection with the first connecting wire.
The bottom electrode 510 may be formed of, for example, silver, and the formation may involve successive processes of thin-film deposition, photolithography and etching. Alternatively, the bottom electrode 510 may be formed using a vapor deposition process.
Step 2: Bonding the piezoelectric crystal 520 to the bottom electrode 510, as shown in
Step 3: Forming the top electrode 530 on the piezoelectric crystal 520, as shown in
It is to be noted that, in this embodiment, the bottom electrode 510, the piezoelectric crystal 520 and the top electrode 530 are successively formed over the device wafer 100 using semiconductor processes. However, in other embodiments, it is also possible to form the top and bottom electrodes on opposing sides of the piezoelectric crystal and then bond the three as a whole onto the device wafer.
As described above, in the resulting piezoelectric vibrator 200, the bottom electrode 510 is electrically connected to the first circuit via the first connection, and the top electrode 530 is electrically connected to the second circuit via the second connection.
Thus, the piezoelectric vibrator 500 is electrically connected to the control circuit 110 from the back side thereof, thus allowing the control circuit 110 to apply an electrical signal to the bottom and top electrodes 510, 530 of the piezoelectric vibrator 500 to create an electric field therebetween, which causes the piezoelectric crystal 520 of the piezoelectric vibrator 500 to change its shape. When the electric field in the piezoelectric vibrator 500 is inverted, the piezoelectric crystal 520 will change its shape in the opposite direction. Therefore, when the control circuit 110 applies an AC signal to the piezoelectric vibrator 500, the piezoelectric crystal 520 will change shape alternately in opposite directions and thus alternately contract and expand due to change in direction of the electric field. As a result, the piezoelectric crystal 520 will vibrate mechanically.
The first connection comprises the first conductive plug 221 and the first connecting wire 211. The bottom electrode 510 is located below the piezoelectric crystal 520 and extends out from the piezoelectric crystal 520, so that the bottom electrode 510 covers the first conductive plug 221. In this way, the bottom electrode 510 can be electrically connected to the control circuit by the first connection.
In this embodiment, in addition to the second conductive plug 222 and the second connecting wire 212, the second connection may also include a third conductive plug 610 that is connected to the second conductive plug 222 at the bottom and to the top electrode 530 at the top and supports the top electrode 530.
Specifically, the formation of the third conductive plug 610 in the second connection may include the steps below.
At first, with reference to
Next, with continued reference to
Subsequently, a conductive material is filled in the through hole, resulting in the formation of the third conductive plug 610, so that the third conductive plug 610 is electrically connected to the second conductive plug 222 at the bottom and exposed from the plastic encapsulation layer 600 at the top.
Thereafter, with reference to
Afterward, with reference to
It is to be noted that in embodiments where the second connecting wire in the second connection is formed on the back side of the device wafer, the third conductive plug of the second connection may be brought into electrical connection with the second connecting wire at the top.
Of course, in alternative embodiments, the second connection comprises the second connecting wire 212, the second conductive plug 222, the third conductive plug, and an interconnecting wire. In such embodiments, the third conductive plug may be connected to the second conductive plug 222 at the bottom and to one end of the interconnecting wire at the top, and the other end of the interconnecting wire may overlap at least part of, and thus come into electrical connection with, the top electrode 530.
Specifically, in these embodiments, the formation of the third conductive plug and the interconnecting wire may include, for example, the steps below.
At first, a plastic encapsulation layer is formed over the surface of the device wafer 100 facing away from the support wafer 400. The plastic encapsulation layer may be formed subsequent to the formation of the top electrode in such a manner that the top electrode 530 is exposed from the plastic encapsulation layer.
Next, a through hole is formed in the plastic encapsulation layer, and the through hole extends through the plastic encapsulation layer to the back side of the device wafer (in this embodiment, the second conductive plug 222 is exposed in the through hole), and a conductive material is filled in the through hole to result in the formation of the third conductive plug that is electrically connected at the bottom to the control circuit (in this embodiment, more exactly, to the second conductive plug 222).
Subsequently, the interconnecting wire is formed on the plastic encapsulation layer. The interconnecting wire covers at least part of the top electrode 530 and extends from the top electrode 530 over the third conductive plug. The plastic encapsulation layer is then removed. Thus, the top electrode 530 is electrically connected to the second conductive plug 222 via the interconnecting wire and the third conductive plug.
In step S400, with reference to
Specifically, the formation of the cap layer 720 that delimits the upper cavity 700 may include, for example, the steps below.
In a first step, with reference to
In a second step, with continued reference to
The space occupied by the sacrificial layer 710 corresponds to the internal space of the subsequently formed upper cavity. Therefore, a depth of the resulting upper cavity may be adjusted by changing a height of the sacrificial layer. It will be recognized that the depth of the upper cavity may be determined as practically required, and the present invention is not limited in this regard.
In a third step, with reference to
As a result, the piezoelectric vibrator 500 is enclosed in the upper cavity 700 so that it can vibrate in the lower and upper cavities 120, 400.
Optionally, with reference to
Furthermore, after the cap layer 720 is formed, the support wafer may be retained as a cap substrate for closing the opening of the lower cavity exposed at the front side of the device wafer. Alternatively, after the cap layer 720 is formed, the support wafer may be removed and a separate cap substrate may be bonded to the front side of the device wafer to close the opening of the lower cavity exposed at the front side of the device wafer.
A structure of the crystal resonator formed according to the above method will be described below with reference to
a device wafer 100, in which the control circuit and a lower cavity 120 are formed, the lower cavity 120 having an opening at a back side of the device wafer;
a piezoelectric vibrator 500 comprising bottom electrode 510, a piezoelectric crystal 520 and a top electrode 530, the piezoelectric vibrator 500 formed on the back side of the device wafer 100 and is in positional correspondence with the lower cavity 120;
a connecting structure formed on the device wafer 100, the connecting structure configured to electrically connect both the top and bottom electrodes 530, 510 of the piezoelectric vibrator 500 to the control circuit; and
a cap layer 720 formed on the back side of the device wafer 100 so as to cover the piezoelectric vibrator 500 and delimit an upper cavity 700 together with the piezoelectric vibrator 500 and the device wafer 100 (the cap layer 720 can be considered as a layer enclosing the piezoelectric vibrator 500 within the upper cavity 700).
Thus, the integration of the crystal resonator with the control circuit is accomplished by forming the crystal resonator through utilizing semiconductor processes to form the piezoelectric vibrator and enclose it within the device wafer 100 containing the control circuit. This is helpful in correcting raw deviations of the crystal resonator such as temperature and frequency drifts. Moreover, the crystal resonator fabricated using the semiconductor processes is more compact in size and thus less power-consuming. Further, the piezoelectric vibrator is allowed to be arranged, and brought into electrical connection with the control circuit, on the back side of the device wafer.
In this embodiment, the control circuit may include a first circuit 111 and a second circuit 112, which are electrically connected to the bottom and top electrodes 510, 530 of the piezoelectric vibrator 500, respectively. The first circuit 111 may include a first transistor 111T and a first interconnecting structure 111C. The first transistor 111T may be buried within the device wafer 100, and the first interconnecting structure 111C may be connected to the first transistor 111T and extend to the front side of the device wafer 100. The second circuit 112 may include a second transistor 112T and a second interconnecting structure 112C. The second transistor 112T may be buried within the device wafer 100, and the second interconnecting structure 112C may be connected to the second transistor 112T and extend to the front side of the device wafer 100.
The connecting structure may include a first connection that connects the first interconnecting structure 111C to the bottom electrode 510 of the piezoelectric vibrator and a second connection that connects the second interconnecting structure 112C to the top electrode 530 of the piezoelectric vibrator.
The first connection may include a first conductive plug 221 which penetrates through the device wafer 100 so as to extend to the front side of the device wafer into electrical connection with the first interconnecting structure at one end and to extend to the back side of the device wafer 100 into electrical connection with the bottom electrode 510 of the piezoelectric vibrator at the other end.
The first connection may further include a first connecting wire 211. In this embodiment, the first connecting wire 221 is formed on the front side of the device wafer 100 and connects the first conductive plug 221 to the first interconnecting structure. In alternative embodiments, the first connecting wire 211 may be formed on the back side of the device wafer 100 and connect the first conductive plug to the bottom electrode.
With this arrangement, the first connecting wire 211 and first conductive plug 221 collaboratively lead a connection port of the first interconnect 111a from the front side of the device wafer 100 to the back side thereof. In this way, the connection port is allowed to be electrically connected to the bottom electrode 510 of the piezoelectric vibrator 500 that is formed on the back side of the device wafer 100.
In this embodiment, the bottom electrode 510 is so formed on the back side of the device wafer 100 so as to laterally extend beyond the piezoelectric crystal over the first conductive plug 221, thus coming into electrical connection with the first conductive plug 221.
The second connection may include a second conductive plug 222 which penetrates through the device wafer 100 so as to extend to the front side of the device wafer 100 into electrical connection with the second interconnecting structure at one end and to extend to the back side of the device wafer 100 into electrical connection with the top electrode 530 of the piezoelectric vibrator at the other end.
The second connection may further include a second connecting wire 212. In this embodiment, the second connecting wire 212 is formed on the front side of the device wafer 100 and connects the second conductive plug 222 to the second interconnecting structure. In alternative embodiments, the second connecting wire 212 may be formed on the back side of the device wafer 100 and connect the second conductive plug to the top electrode.
Likewise, the second connecting wire 212 and second conductive plug 222 collaboratively lead a connection port of the second interconnecting structure 112a from the front to back side of the device wafer 100. Thus, the connection port is allowed to be electrically connected to the top electrode of the piezoelectric vibrator 500 that is formed on the back side of the device wafer 100.
In this embodiment, the second connection may further include a third conductive plug 610 which electrically connects the top electrode 530 to the second conductive plug 222 and hence to the second interconnecting structure in the second circuit 112.
Specifically, the third conductive plug 610 in the second connection may be formed on the back side of the device wafer in such a manner that its one end is electrically connected to the top electrode and the other end is electrically connected to the second conductive plug 222. It can be considered that the top electrode 530 overlaps at least part of the piezoelectric crystal 520 and extends beyond the piezoelectric crystal 520 and covers the top of the third conductive plug 610, thus the top electrode 530 to the second conductive plug 222 are connected by the conductive plug 610.
In alternative embodiments, the second connection may comprise the second conductive plug 222, the second connecting wire 212, the third conductive plug, and an interconnecting wire. In such embodiments, the third conductive plug may be formed on the back side of the device wafer in such a manner that it is electrically connected to the second conductive plug 222 at the bottom. Additionally, the interconnecting wire may cover at least part of the top electrode 530 at one end and overlap the top of the third conductive plug at the other end, thus coming into connection with the third conductive plug. It will be recognized that, in such cases, the third conductive plug also serves to support the interconnecting wire.
With continued reference to
In this embodiment, the device wafer 100 includes a substrate wafer and a dielectric layer 100B. The first and second transistors 111T, 112T may be both formed on the substrate wafer, and the dielectric layer 100B is so formed on the substrate wafer as to cover both the first and second transistors 111T, 112T. The first and second interconnecting structures 111C, 112C may be both formed in the dielectric layer 100B.
With continued reference to
Furthermore, in this embodiment, the lower cavity extends through the device wafer. Accordingly, a cap substrate may be bonded to the front side of the device wafer to close the opening of the lower cavity present at the front side of the device wafer. The cap substrate may be composed of, for example, a silicon wafer.
In summary, in the method for integrating the crystal resonator with the control circuit according to the present invention, the piezoelectric vibrator is formed, and then brought into electrical connection with the control circuit, on the back side of the device wafer, followed by forming the cap layer using planar fabrication processes, which encloses the piezoelectric vibrator within the upper cavity, thus resulting in the formation of the crystal resonator. Obviously, compared with traditional crystal resonators (e.g., surface-mount ones), the crystal resonator fabricated using planar fabrication processes in accordance with the present invention is more compact in size and hence less power-consuming. Moreover, the crystal resonator of the present invention is able to integrate with other semiconductor components more easily with a higher degree of integration. Further, forming the piezoelectric vibrator on the back side of the device wafer allows higher process flexibility for the crystal resonator.
The description presented above is merely that of a few preferred embodiments of the present invention without limiting the scope thereof in any sense. Any and all changes and modifications made by those of ordinary skill in the art based on the above teachings fall within the scope as defined in the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 201811647865.1 | Dec 2018 | CN | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CN2019/115647 | 11/5/2019 | WO | 00 |
