Claims
- 1. An integrated, tunable capacitance, comprising:
a semiconductor body having a semiconductor region of a first conductivity type embodied as a well, said semiconductor body being of a second conductivity type; at least one first insulating region disposed in said semiconductor body, said first insulating region having a common interface with said semiconductor region and a first layer thickness; a second insulating region having a common interface with said semiconductor region and a common interface with said first insulating region; a control electrode disposed on said second insulating region; and at least one well terminal region for connecting said semiconductor region to a control voltage for tuning the capacitance, said well terminal region having a higher dopant concentration than said semiconductor region and a second layer thickness greater than the first layer thickness.
- 2. The capacitance according to claim 1, further comprising a buried layer of the first conductivity type having a higher dopant concentration than said semiconductor region, and adjoining said well terminal region.
- 3. The capacitance according to claim 1, wherein said well terminal region is formed using bipolar fabrication technology.
- 4. The capacitance according to claim 1, wherein said well terminal region has a common interface with said second insulating region and said semiconductor region below said control electrode.
- 5. The capacitance according to claim 1, further comprising a further region for connecting to a reference-ground potential, said further region being of the second conductivity type and also highly doped as compared to said semiconductor body and has a common interface with said second insulating region and said semiconductor region below said control electrode.
- 6. The capacitance according to claim 1, wherein said second insulating region having a third layer thickness, being less than the first layer thickness of said first insulating region.
- 7. The capacitance according to claim 1, wherein said first insulating region is a shallow trench insulation region.
- 8. The capacitance according to claim 1, wherein said second insulating region is an oxide layer.
- 9. The capacitance according to claim 1, wherein said control electrode is a polycrystalline layer.
Priority Claims (1)
Number |
Date |
Country |
Kind |
101 26 116.0 |
May 2001 |
DE |
|
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application is a continuation of copending International Application No. PCT/DE02/01993, filed May 29, 2002, which designated the United States and was not published in English.
Continuations (1)
|
Number |
Date |
Country |
Parent |
PCT/DE02/01993 |
May 2002 |
US |
Child |
10712664 |
Nov 2003 |
US |