The present disclosure generally relates to the field of electronics. More particularly, an embodiment of the invention relates to techniques for integration of a processor and an Input/Output (I/O) hub.
In some current implementations, a processor may communicate with input/output (I/O) devices via an I/O Hub (IOH). Furthermore, the processor may be provided on a different integrated circuit (IC) device than the IOH. A bus may be used to communicate between these IC devices.
Such implementations may, however, reduce speed, e.g., due to delay associated with communicating signals between the IC devices, and/or increase power consumption, e.g., due to presence of additional circuitry required to allow for communication between the IC devices. Also, additional (board) space may be required for the discrete IOH component(s).
The detailed description is provided with reference to the accompanying figures. In the figures, the left-most digit(s) of a reference number identifies the figure in which the reference number first appears. The use of the same reference numbers in different figures indicates similar or identical items.
FIGS. 1 and 4-5 illustrate block diagrams of embodiments of computing systems, which may be utilized to implement various embodiments discussed herein.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of various embodiments. However, some embodiments may be practiced without the specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to obscure the particular embodiments.
Some embodiments relate to techniques to reduce delay, reduce power consumption, reduce die size, and/or reduce complexity associated with power management in a computing device. In addition, some embodiments allow for more control and/or communication bandwidth between the two integrated components, e.g., to further refine power state manipulation/control.
In an embodiment, an IOH may be integrated on the same IC device as a processor (which may include one or more processor cores as discussed herein in more detail below). This allows for removal of logic that is only needed for off-chip communication. For example, logic associated with transmission of signals off chip across an interconnect (e.g., physical link) may be removed. Also, logic that would normally control transmitting, training, testing, power state management, etc. of the physical link may be removed.
Even though the physical link and additional logic is removed, the same communication mechanisms may be maintained in some embodiments, e.g., to allow for compatibility with other existing logic, communication protocols, design requirements, etc. For instance, in a QPI (Quick Path Interconnect) based processor, the QPI physical layer and lower link layer may be removed. For the accompanying IOH, the physical layer may be.
In some embodiments, one or more of the following may be utilized to provide the integrated IOH (IIO) and processor:
1. a wider and/or slower bus/interconnect to couple the processor components and IIO, e.g., to eliminate high speed circuit and power challenges (when compared with the bus/interconnect that couples the non-integrated processor and IOH, for example);
2. one or more First-In, First-Out (FIFO) devices to enable deterministic data transfer between the processor and Integrated IIO;
3. one or more side band signals to signal powering up and down of the link(s) between the processor and IIO;
4. protocol to enable either side to initiate shutting down or waking up of the computing system that includes the processor;
5. optional side band signals to further control granularity/depth of low power states; and/or
6. additional signal(s) to take advantage of common mechanisms (e.g., for more space/power reductions).
One or more of the above-mentioned elements may be provided in various computing environments. More particularly,
The system 100 may include a Central Processing Unit (CPU) 101 (or more generally a processor) which includes a processor portion 102. CPU 101 components may be on a single IC die. The CPU 101 may include one or more processors (or processor cores) as discussed herein, e.g., with reference to
As illustrated in
The IIO 120 may include a sideband control logic 124 (e.g., to communicate sideband signals with the logic 112), one or more FIFOs 126 (e.g., to enable deterministic data transfer between the upper link layer 110 and IIO 120 via an interconnect/bus 127), a link logic 128 (e.g., to provide link support for communication between the processor 102 and the IIO 120), and a protocol logic 130 (e.g., to provide the support for shutting down or waking system 100).
In an embodiment, a relatively wider and/or slower bus/interconnect 127 may eliminate high speed circuit and power challenges (when compared with the bus/interconnect that couples the non-integrated processor and IOH, for example). In one embodiment, the bus 127 is widened four times, allowing the frequency to be reduced by four times. A valid bit may be added to allow for more flexibility (null flits are now optional, etc.) and/or to support tester modes.
In some embodiments, FIFOs 126 going in both directions (to and from IIO 120) are added. When transferring data between the processor 102 components (e.g., logic 110) and IIO 120, the data is written into a FIFO based on a write pointer and is read by the receiver based on a read pointer. The separation of the write and read pointers may be programmable, for example, to account for clock skew differences between the processor 102 components (e.g., logic 110) and IIO 120. This allows the processor 102 and IIO 120 to run off of different Phase-Locked Loops (PLLs) for flexibility, finer granularity of power states, etc.
In an embodiment, the following sideband signals are used (e.g., via logics 112 and 124):
1. From the IIO 120:
2. From the processor 102:
As shown in
Similar handshakes may be performed in the exchange of
Furthermore, the IIO or processor may initiate a wake from low power state (e.g., without QPI messages). This was previously done over QPI with analog levels and level detectors. In an embodiment, IIO initiates a wake by asserting IIO_wake. Processor may initiate a wake by asserting processor_wake. Once the wake signal is transmitted, the remaining signals may be sent in a specific order to complete the wake.
For example, for an IIO initiated wake, the following sequence occurs (which assumes that signals are normally high—but of course the reverse implementation is also contemplated in some embodiments):
The protocol (marked with *) also supports the IIO already being awake during the low power state (another medium low power state). In that case, IIO_is_awake may already have been asserted by this point.
In some embodiments, optional sideband signals are used for more granularity/control power modes between the IIO and processor such as one or more of the following:
1. From the processor:
2. From the IIO:
In various embodiments, additional signals may also be used to take advantage of common mechanisms (more space/power reductions). For instance, common infrastructure features present on chips may be combined for additional reduction such as:
(1) Fuses—Separate fuse blocks with a number of common fuses are not needed anymore. A single fuse block, e.g., with additional fuse(s) added for unique IIO fused options may be used. The interface may be a serial download fuse bus to the IIO, e.g., which may be identical to the fuse bus that is coupled to the rest of the processor blocks.
(2) Frequency selection—Non-integrated components generally require separate mechanisms to select the frequency of key interfaces. This selection mechanism requires power cycle reset and careful coordination between the two components. With the integrated IIO and processor, one frequency selection logic may be removed and both the IIO and processor frequency selected off of a single frequency selection logic. This may be done with sideband signals that reflect the clock ratio.
In an embodiment, the IIO resets the processor the same way that the IOH reset the discrete processor. Further, the circuits to drive the pin may be removed for power/space reduction.
As illustrated in
In one embodiment, the system 400 may support a layered protocol scheme, which may include a physical layer, a link layer, a routing layer, a transport layer, and/or a protocol layer. The fabric 404 may further facilitate transmission of data (e.g., in form of packets) from one protocol (e.g., caching processor or caching aware memory controller) to another protocol for a point-to-point or shared network. Also, in some embodiments, the network fabric 404 may provide communication that adheres to one or more cache coherent protocols.
Furthermore, as shown by the direction of arrows in
As illustrated in
In an embodiment, the processors 502 and 504 may be one of the processors 502 discussed with reference to
In at least one embodiment, the I/O functionality may be integrated into the processors 502/504. Other embodiments of the invention, however, may exist in other circuits, logic units, or devices within the system 500 of
The chipset 520 may communicate with a bus 540 (e.g., using an interface circuit 541). The bus 540 may have one or more devices that communicate with it, such as a bus bridge 542 and I/O devices 543 (which may communicate with the IIO via other components such as shown in
Referring to
Referring to
In various embodiments of the invention, the operations discussed herein, e.g., with reference to
The storage medium may include volatile and/or nonvolatile memory (or storage). For example, nonvolatile memory may include one or more of the following: read-only memory (ROM), programmable ROM (PROM), erasable PROM (EPROM), electrically EPROM (EEPROM), a disk drive (e.g., 528), a floppy disk, a compact disk ROM (CD-ROM), a digital versatile disk (DVD), flash memory, a magneto-optical disk, or other types of nonvolatile machine-readable media capable of storing electronic data (e.g., including instructions). Volatile memory may include devices such as random access memory (RAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), static RAM (SRAM), etc.
Also, the term “logic” may include, by way of example, software, hardware, or combinations of software and hardware. The machine-readable medium may include a storage device such as those discussed herein. Additionally, such computer-readable media may be downloaded as a computer program product, wherein the program may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) through data signals provided in a propagation medium via a communication link (e.g., a bus, a modem, or a network connection).
Reference in the specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least an implementation. The appearances of the phrase “in one embodiment” in various places in the specification may or may not be all referring to the same embodiment.
Also, in the description and claims, the terms “coupled” and “connected,” along with their derivatives, may be used. In some embodiments of the invention, “connected” may be used to indicate that two or more elements are in direct physical or electrical contact with each other. “Coupled” may mean that two or more elements are in direct physical or electrical contact. However, “coupled” may also mean that two or more elements may not be in direct contact with each other, but may still cooperate or interact with each other.
Thus, although embodiments of the invention have been described in language specific to structural features and/or methodological acts, it is to be understood that claimed subject matter may not be limited to the specific features or acts described. Rather, the specific features and acts are disclosed as sample forms of implementing the claimed subject matter.
Number | Name | Date | Kind |
---|---|---|---|
5404544 | Crayford | Apr 1995 | A |
5761516 | Rostoker et al. | Jun 1998 | A |
5893153 | Tzeng et al. | Apr 1999 | A |
6009488 | Kavipurapu | Dec 1999 | A |
6442697 | Jain et al. | Aug 2002 | B1 |
6487689 | Chuah | Nov 2002 | B1 |
6536024 | Hathaway | Mar 2003 | B1 |
6721840 | Allegrucci | Apr 2004 | B1 |
6980024 | May et al. | Dec 2005 | B1 |
7181188 | Vu et al. | Feb 2007 | B2 |
7353374 | Trimberger | Apr 2008 | B1 |
7702639 | Stanley et al. | Apr 2010 | B2 |
7814371 | Sams et al. | Oct 2010 | B2 |
7865744 | Lee et al. | Jan 2011 | B2 |
7882294 | Love | Feb 2011 | B2 |
7898994 | Zhao et al. | Mar 2011 | B2 |
8181059 | Millet et al. | May 2012 | B2 |
8304698 | Tischler | Nov 2012 | B1 |
20020033828 | Deering et al. | Mar 2002 | A1 |
20030159024 | Chen | Aug 2003 | A1 |
20030226050 | Yik et al. | Dec 2003 | A1 |
20040139283 | Arimilli et al. | Jul 2004 | A1 |
20040215371 | Samson et al. | Oct 2004 | A1 |
20050128846 | Momtaz et al. | Jun 2005 | A1 |
20050149768 | Kwa et al. | Jul 2005 | A1 |
20050283561 | Lee et al. | Dec 2005 | A1 |
20060174142 | Lin et al. | Aug 2006 | A1 |
20060224806 | Suzuki | Oct 2006 | A1 |
20070005995 | Kardach et al. | Jan 2007 | A1 |
20070094436 | Keown et al. | Apr 2007 | A1 |
20070180281 | Partovi et al. | Aug 2007 | A1 |
20070300088 | Lippojoki | Dec 2007 | A1 |
20080062927 | Zhu et al. | Mar 2008 | A1 |
20080074992 | Sams et al. | Mar 2008 | A1 |
20080162855 | Thomas | Jul 2008 | A1 |
20080307244 | Bertelsen et al. | Dec 2008 | A1 |
20090164684 | Atherton et al. | Jun 2009 | A1 |
20090210595 | Chaussade | Aug 2009 | A1 |
20090259713 | Blumrich et al. | Oct 2009 | A1 |
20100083026 | Millet et al. | Apr 2010 | A1 |
20100153759 | Singhal | Jun 2010 | A1 |
20100162019 | Kumar et al. | Jun 2010 | A1 |
20100257393 | Zhuang et al. | Oct 2010 | A1 |
20100281195 | Daniel et al. | Nov 2010 | A1 |
20110293035 | Kobayashi | Dec 2011 | A1 |
20110296222 | Tan et al. | Dec 2011 | A1 |
20120079159 | Rajwar et al. | Mar 2012 | A1 |
Number | Date | Country |
---|---|---|
102270187 | Dec 2011 | CN |
2006-285872 | Oct 2006 | JP |
2007-517332 | Jun 2007 | JP |
2007-249808 | Sep 2007 | JP |
2008-194563 | Aug 2008 | JP |
2009-217813 | Sep 2009 | JP |
2010-500807 | Jan 2010 | JP |
2010-515164 | May 2010 | JP |
546560 | Aug 2003 | TW |
8904516 | May 1989 | WO |
2008018017 | Feb 2008 | WO |
2011153042 | Dec 2011 | WO |
2011153042 | Apr 2012 | WO |
2012047600 | Apr 2012 | WO |
2012088530 | Jun 2012 | WO |
2012047600 | Aug 2012 | WO |
2012088530 | Dec 2012 | WO |
Entry |
---|
International Search Report and Written Opinion Received for PCT Application No. PCT/US2011/037990 , mailed on Feb. 9, 2012, 10 pages. |
Berktold et al., “CPU Monitoring With DTS/PECI”, Intel Corporation, White Paper, Sep. 2009, pp. 1-23. |
International Search Report and Written Opinion Received for the PCT Application No. PCT/US2011/053335, mailed on Jun. 22, 2012, 9 pages. |
International Search Report and Written Opinion Received for the PCT Application No. PCT/US2011/067260, mailed on Aug. 14, 2012, 9 pages. |
International Preliminary Report on Patentability Received for the PCT Application No. PCT/US2011/037990, mailed on Dec. 13, 2012, 5 pages. |
International Preliminary report on Patentability and Written Opinion received for PCT Application No. PCT/US2011/053335, mailed on Apr. 4, 2013, 6 pages. |
Office Action received for Chinese Patent Application No. 201110158611.5, mailed on Jun. 7, 2013, 5 pages of English Translation and 6 pages of Office Action. |
Office Action received for U.S. Appl. No. 13/040,507, mailed on Apr. 8, 2013, 19 pages. |
Office Action received for U.S. Appl. No. 12/978,452 , mailed on Sep. 20, 2013, 9 pages. |
“FIFO: First-In First-Out”, FOLDOC: Free On-Line Dictionary of Computing, Dec. 6, 1999, retrieved on Nov. 22, 2013, 1 page. available online at <http://foldoc.org/fifo>. |
Office Action received for U.S. Appl. No. 13/040,507, mailed on Oct. 9, 2013, 37 pages. |
Extended European Search Report received for European Patent Application No. 11790212.2, mailed on Jan. 8, 2014, 6 pages. |
Supplementary Search Report received for European Patent Application No. 11790212.2, mailed on Jan. 24, 2014, 1 page. |
Office action received for Japanese Patent Application No. 2013-513224, mailed on Dec. 10, 2013, 3 pages of English Translation and 3 pages of Japanese Office Action. |
“Data link layer”, extracted from The Free Online Dictionary of Computing, last update on Feb. 14, 1995, Retrieved on Apr. 4, 2014, Webpage available at: <http://foldoc.org/data+link-Flayer+22 . |
Office Action Received for Taiwanese Patent Application No. 100134377 mailed on Nov. 13, 2013, 8 pages of Office Action and 9 pages of English Translation. |
Notice of Allowance Received for U.S. Appl. No. 12/978,452 mailed on Mar. 18, 2014, 5 pages. |
Office Action Received for U.S Appl. No. 13/040,507 mailed on Apr. 9, 2014, 32 pages. |
Office Action Received for the Chinese Application No. 201110158611.5 mailed on Feb. 8, 2014, 6 pages of Office Action and 5 pages of English Translation. |
International Preliminary Report and Written Opinion Received for the PCT Application No. PCT/US2011/067260 mailed on Jul. 4, 2013, 6 pages. |
Number | Date | Country | |
---|---|---|---|
20110296216 A1 | Dec 2011 | US |