Patent Application
20220384704
The present disclosure is related to Josephson junctions, and in particular to Josephson junctions including a shunt resistor and methods for manufacturing the same.
A Josephson junction includes a non-superconducting material sandwiched between two layers of superconducting material. Josephson junctions can be used to build electronic circuitry, and in particular logic circuitry and quantum computing circuitry. Further, Josephson junctions can be arranged to provide superconducting quantum interference devices (SQUIDs), which can be used for extremely sensitive measurement tools. Integrating one or more Josephson junctions along with other circuitry may require supporting components such as a shunt resistor. Generally, it is desirable to integrate these supporting components along with the Josephson junctions. However, processes for fabricating Josephson junctions including one or more support components have generally been defined by low volume, complex fabrication techniques. As demand for circuitry including Josephson junctions continues to increase, there is a need for Josephson junctions integrated with supporting components and processes for providing these Josephson junctions using high volume manufacturing techniques.
In one embodiment, a method for manufacturing a Josephson junction structure begins with providing a substrate. An insulating layer is provided on the substrate. A support structure is on the insulating layer. A wetting layer is provided on the insulating layer and the support structure. An etch-stop layer is provided on the wetting layer. A base metal layer is provided on the etch-stop layer. The base metal layer comprises a superconducting material and is in electrical contact with the support structure via the etch-stop layer and the wetting layer. A middle layer is provided on the base metal layer. The middle layer comprises an insulating material. A top metal layer is provided on the middle layer. The top metal layer comprises a superconducting material. The top metal layer is patterned with a first etch process that is selective with respect to the middle layer. The middle layer is patterned with a second etch process that is selective with respect to the base metal layer. The base metal layer is patterned with a third etch process that is selective with respect to the etch-stop layer. The etch-stop layer and the wetting layer are patterned with a fourth etch process that is selective with respect to the support structure. The base metal layer, the middle layer, and the top metal layer are patterned such that they provide a Josephson junction that is electrically coupled to the support structure. Providing the etch-stop layer and the wetting layer allows the materials for the support structure and the base metal layer to be chosen independently of their etch selectivity with respect to one another. Providing the etch-stop layer and the wetting layer and patterning the layers using selective etch processes, the Josephson junction structure can be manufactured using high volume manufacturing techniques.
In one embodiment, the support structure is a resistor. The resistor may be a shunt resistor. In various embodiments, the resistor comprises one of titanium tungsten and tungsten. The wetting layer comprises titanium. The etch-stop layer comprises aluminum. The base metal layer and the top metal layer comprise niobium. The middle layer comprises aluminum oxide.
The first etch process and the third etch process may utilize an etching solution comprising fluorine. The second etch process and the fourth etch process may utilize an etching solution comprising chlorine.
In one embodiment, a Josephson junction structure includes a substrate, an insulating layer, a wetting layer, an etch-stop layer, a base metal layer, a middle layer, and a top metal layer. The insulating layer is on the substrate. The support structure is on the insulating layer. The wetting layer is on the insulating layer and the support structure. The etch-stop layer is on the wetting layer. The base metal layer is on the etch-stop layer. The base metal layer comprises a superconducting material and is in electrical contact with the support structure via the etch-stop layer and the wetting layer. The middle layer is on the base layer and comprises a non-superconducting material. The top metal layer is on the middle layer and comprises a superconducting material. Providing the etch-stop layer and the wetting layer allows the materials for the support structure and the base metal layer to be chosen independently of their etch selectivity with respect to one another.
Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures.
The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.
The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.
Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including” when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
As discussed in detail below, the materials for the resistor structure 16, the wetting layer 18, the etch-stop layer 20, the base metal layer 22, the middle layer 24, and the top metal layer 26 are chosen not only for one or more electrical characteristics thereof (e.g., superconducting, non-superconducting, resistivity, etc.), but also for their selectivity with respect to one another in certain etch processes used to form the Josephson junction structure 10. In particular, etch processes for the base metal layer 22 and the top metal layer 26 are selective with respect to the middle layer 24 and the etch-stop layer 20, and vice-versa. Similarly, etch processes for the etch-stop layer 20 and the wetting layer 18 are selective with respect to the resistor structure 16. As defined herein, an etch process is selective between materials when the etching rate of the etching process between the material for which etching is not desired (e.g., a lower layer) and a material for which etching is desired (e.g., an upper layer) is less than 1. In some embodiments, however, the etching rate between the material for which etching is not desired and the material for which etching is desired may be less than 0.75, less than 0.5, and less than 0.1.
To satisfy the above requirements, the resistor structure 16 may comprise titanium tungsten (TiW) or tungsten. However, the resistor structure 16 may also comprise any other suitable material, and in various embodiments can comprise any non-superconducting metal that is not magnetic and is also selective in an etch process with respect to the etch-stop layer 20 and the wetting layer 18. Previously, the base metal layer 22 was provided directly on the resistor structure 16. Such a structure required etch selectivity between the base metal layer 22 and the resistor structure 16. Due to the superconducting requirements of the base metal layer 22 to provide the Josephson junction 28, the materials available for the resistor structure 16 were very limited (e.g., to noble metals including gold that have a low sheet resistivity). Due to the low sheet resistivity of the materials available for the resistor structure 16, a large area or footprint was required to achieve a desired resistance. The use of the wetting layer 18 and the etch-stop layer 20 described herein effectively decouples the etch selectivity requirements of the base metal layer 22 and the resistor structure 16, which enables the use of additional categories of materials for the resistor structure 16. In particular, this may enable the use of materials with a high sheet resistivity for the resistor structure 16. As a result, the resistor structure 16 can have a much smaller area or footprint compared to previous approaches while providing a desired resistance. In one embodiment, an area of the resistor structure 16 may be less than 90 μm2, and may be as low as 10 nm2 in some embodiments.
As discussed above, to provide the Josephson junction 28 the base metal layer 22 and the top metal layer 26 must comprise superconducting materials, while the middle layer 24 must comprise a non-superconducting material. Further, the top metal layer 26 must be selective with respect to the middle layer 24 in an etch process, and the middle layer 24 must be selective with respect to the base metal layer 22 in an etch process. In one embodiment, the base metal layer 22 and the top metal layer 26 comprise niobium, while the middle layer 24 comprises aluminum oxide (Al2O3). The base metal layer 22 and the top metal layer 26 may also comprise other niobium class superconductors such as niobium-titanium nitride (Nb—Ti)N, niobium nitride (NbN), or any other superconducting material that meets the etch selectivity requirements discussed herein.
The wetting layer 18 and the etch-stop layer 20 may comprise titanium and aluminum, respectively. However, the wetting layer 18 and the etch-stop layer 20 may comprise any suitable material that is selective in an etch process with the base metal layer 22 and the resistor structure 16 while also being electrically conductive such that the base metal layer 22 electrically contacts the resistor structure 16 via the etch-stop layer 20 and the wetting layer 18. The wetting layer 18 must also be capable of smooth deposition onto the insulating layer 14 and the resistor structure 16.
The substrate 12 may comprise any suitable material such as silicon. The insulating layer 14 may similarly comprise any suitable material such as silicon oxide (SiO2).
A thickness of the base metal layer 22 and the top metal layer 26 may be between 1 nm and 500 nm. The thickness of the resistor structure 16 should be at least 1.5 times less than the thickness of the base metal layer 22 and the top metal layer 26, and can be up to 5.0 times less, depending on a desired resistance of the resistor structure 16. A thickness of the wetting layer 18 may be between 1 nm and 100 nm. A thickness of the etch-stop layer 20 may be between 1 nm and 100 nm. A thickness of the middle layer 24 may be between 1 nm and 20 nm.
The Josephson junction structure 10 discussed herein is capable of being made in a high-volume manufacturing facility with existing semiconductor fabrication tooling (e.g., for complementary metal-oxide semiconductor (CMOS) devices). In addition to the constraints discussed above, the materials for the substrate 12, the insulating layer 14, the resistor structure 16, the wetting layer 18, the etch-stop layer 20, the base metal layer 22, the middle layer 24, and the top metal layer 26 may thus be chosen for their compatibility with a particular fabrication tooling scheme, which may restrict the available pool of materials for each of the above. For example, gold is generally not compatible with CMOS fabrication processes due to the affinity thereof for diffusion into semiconductor materials.
A resistor layer 34 is provided on the insulating layer 14 (step 104 and
Subsequent to the patterning of the resistor layer 34 to provide the resistor structure 16, the Josephson junction structure 10 is cleaned (step 108 and
The wetting layer 18 is then provided on the exposed portions of the insulating layer 14 and the resistor structure 16 (step 110 and
The etch-stop layer 20 is provided on the wetting layer 18 (step 112 and
The base metal layer 22 is provided on the etch-stop layer 20 (step 114 and
While not shown in the flow diagram of
The top metal layer 26 is patterned (step 120 and
The middle layer 24 is patterned (step 122 and
The base metal layer 22 is patterned (step 124 and
The etch-stop layer 20 and wetting layer 18 are patterned (step 126 and
As discussed above, contacts may be provided to various parts of the Josephson junction structure 10 such as those discussed above with respect to
The process described above is compatible with high volume manufacturing such as processes designed for semiconductor devices, and in particular CMOS devices. The choice of materials allows for the creation of a desired pattern at each layer and thus provides a Josephson junction that is integrated with a support structure such as the resistor structure 16. Notably, the principles of the present disclosure are not limited to the integration of Josephson junctions with resistor structures, but rather are more broadly applicable to the integration of Josephson junctions with any support structures. The wetting layer 18 and the etch-stop layer 20 enable the integration of a Josephson junction with any desired support component (e.g., series resistors, other semiconductor devices such as diodes, transistors, and the like) using a similar process to the one discussed above.
While the above shows the base metal layer 22 directly on the etch-stop layer 20, which is directly on the wetting layer 18, which in turn is directly on the resistor structure 16, there may be additional intervening layers such as an additional inter-layer dielectric layer between the base metal layer 22 and the resistor structure 16. Vias or other metal connecting structures may be used to electrically couple the base metal layer 22 to the resistor structure 16. Further, while the resistor structure 16 is shown on the insulating layer 14 and described as being provided before manufacture of the Josephson junction 28, the resistor structure 16 may instead be provided on the additional insulating layer 30 such that the Josephson junction 28 is first provided and the resistor structure 16 is subsequently provided. In such an embodiment, the resistor structure 16 may contact the base metal layer 22 by any number of vias and/or additional metallization layers. The process for forming the Josephson junction 28 and the resistor structure 16 is the same as described above, with the order of manufacturing steps being changed. The selectivity of etch chemistries and selection of materials discussed throughout the present disclosure enables the manufacture of the Josephson junction structure 10 in any number of desired configurations.
To illustrate,
Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.
