Patent Application
20100327835
For a more complete understanding, reference is now made to the following description taken in conjunction with the accompanying Drawings in which:
a and 9b disclose wave forms illustrating operation of the circuit of
Referring now to the drawings, wherein like reference numbers are used herein to designate like elements throughout, the various views and embodiments of an GM amplifier for providing overshoot protection and light switching mode during non-zero load condition for an led driver circuit are illustrated and described, and other possible embodiments are described. The figures are not necessarily drawn to scale, and in some instances the drawings have been exaggerated and/or simplified in places for illustrative purposes only. One of ordinary skill in the art will appreciate the many possible applications and variations based on the following examples of possible embodiments.
LED drivers are used for driving LEDs in various applications. Multi channel LED drivers may be used for driving multiple strings (i.e., channels) of LEDs for use in various applications such as backlighting. Existing LED drivers may have problems providing sufficient headroom for the LED strings and may also experience excessive transients within the output of switching converters within the LED driver due to changes in load currents.
Referring now to the drawings, and more particularly to
Referring now to
The top of the LED string at node 214 comprises an output voltage node VOUT which is connected to a resistor divider consisting of resistors 222 and 224. Resistor 222 is connected between node 214 and node 226. Resistor 224 is connected between node 226 and ground. A voltage measurement is taken at node 226 (from the pin usually used for over voltage protection purposes) and provided to the boost regulator 202 as a feedback voltage VFB. The LED string 204 consists of a plurality of individual LEDs 215 which are connected in series between node 214 and node 228. A current source is provided at the bottom of the LED string at node 228. The current source consists of an amplifier 230 connected to receive a reference voltage VSET at the non-inverting input. The voltage VSET is used to set the current. The output of the amplifier 230 is connected to a transistor 232 having its drain/source path connected between node 228 and node 234. The other input of amplifier 230 is connected to node 234. The inverting input of amplifier 230 is connected to node 234. A resistor 236 is connected between node 234 and ground. The disclosed embodiment comprises one example of the current source. However, other implementations of the current source may be used.
The voltage generated at node 228 is applied to the non-inverting input of comparators 238 and inverting input of comparator 240. The inverting input of comparator 238 is connected to receive a reference voltage VHIGH. The non-inverting input of comparator 240 is connected to receive a reference voltage VLOW. The output of comparator 238 is connected to one input of an AND gate 242. The remaining inputs of AND gate 242 would be connected to the outputs of the comparator 238 from each of the other channels associated with each of the other circuit blocks 206. Similarly, the output of comparator 240 is connected to one input of an OR gate 244. The remaining inputs of OR gate 244 would be connected to the outputs of the comparators in each of the other channels from circuit block 206. The output of AND gate 242 is provided to the DOWN input of counter/stepping algorithm 246. The output of OR gate 244 is connected to the UP input of the counter/stepping algorithm 246. The counting/stepping algorithm 246 generates a count value via bus 248 that is input to a digital-to-analog converter 250. The digital-to-analog converter 250 generates an output analog value that is used as the reference voltage VREF that is applied back to the boost regulator circuitry 202.
The multi-channel LED configuration using a boost/buck switching regulator generates a single voltage at node 214 to drive the top of a plurality of series LED strings 204. Each of the series stacks of LED strings 204 are connected in parallel to a separate current source at the bottom node 228. This allows a savings in circuit hardware by sharing the switching regulator between multiple LED strings 204. This configuration drives a large number of LEDs without requiring excessively high voltages. However, the voltages must be carefully regulated to eliminate power dissipation in the current sources which will cause thermal problems and limit overall circuit efficiency. As the voltage of the LEDs are variable (with process, temperature and aging effects), previous implementations of these systems have used the voltage at the output of the current sources at node 228 as a feedback point for the regulator allowing the regulator to be adaptive and move the optimum operating level. This minimizes power dissipation due to the voltage drop across the current source. Typically this is done by passing the analog voltages at the bottom of each LED string 204 to a control block which picks out the lowest voltage level from each of the LED strings and passes this selected voltage on as the feedback voltage. This feedback voltage is regulated to a level which has been defined such that the current sources will have sufficient headroom not to be pushed in a linear region of operation (typically several hundred millivolts). This works well when all LED strings are running with the same pulse width modulated (PWM) dimming signal, as whenever any string is conducting, all strings are conducting. This means that real time information is available on which string has the lowest voltage at all times when the boost voltage regulator 202 is switching.
However, for systems where different PWM dimming signals are used for different channels, it is possible for there to be no time when all channels are conducting at once. It would be possible to regulate on the basis of only those channels that are conducting at a given point in time, resulting in a switching regulator output voltage level which varies as different channels turn on and off. However, this solution provides a poor output voltage transient response resulting in short current pulses being noticeably compressed in situations where there is a mismatch between strings.
If, for example, all LED strings 204 have the same conducting voltage, except for one which needs one volt more, and the LED string is only turned on for a 490 nanosecond pulse every 500 microseconds (as would be the case with the lowest dimming signal in a 10-bit PWM dimming scheme running on a 2 KHz PWM frequency), the boost regulator 202 would have to respond in substantially less than this time. It is not practical to build the boost regulator 202 for such an application that has a transient response that is dynamically faster than 490 nanoseconds. In practice, the response time will be a period of tens to hundreds of microseconds, which is far too slow. This means that the boost regulator 202 will miss the 490 nanosecond period when the circuit requires extra head room, which in turn is likely to mean that the current source has insufficient headroom and that the 490 nanosecond current pulse will not reach its intended peak current. This compression of current will cause a corresponding reduction of the brightness of the LED string, for the lower PWM duty cycles and strings with higher forward voltages than other strings in the system. The implementation described with respect to
The voltage window between the reference voltages VHIGH and VLOW is set to be larger than the smallest single step that can be introduced onto the boost regulator output voltage node 214 by the control scheme, guaranteeing that at least one output level will obtain a stable operating point. The voltage control is achieved by regulating the output voltage of the boost regulator 202 to a reference voltage input VREF that is generated from the digital-to-analog converter (DAC) 250. The counter/stepping algorithm 246 controls the reference voltage provided by the DAC 250 to cause the voltage at the bottom of a lowest voltage node of the plurality of LED strings 204 to remain between the high reference voltage and the low reference voltage The DAC 250 output can be moved up and down to the required level by digital control signals provided from the counter/stepping algorithm 246 to the required level by a digital control scheme based upon information gained from monitoring the channel voltages at the bottom of each LED string 204. The OVP signal monitored at node 226 is used as the feedback signal for the boost regulator 202, which is regulated to the voltage level dictated by the reference voltage provided from the DAC 250. This provides the correct voltage for the LED string 204 with the highest forward voltage requirement no matter how short the time a particular LED string is conducting. Additionally, stability is improved over systems which take the boost feedback from the bottom of the LED strings, as the phase shift that would normally be introduced into the feedback path due to the interaction with the current source transient response and LED characteristics is eliminated from the control loop.
The DAC 250 is configured such that successive changes get larger and larger (up to a maximum step size limit) in order to reach a target point, unless the output remains constant for longer than a certain time or changes direction. Any subsequent changes will be small to allow for minor fluctuations in the level required for temperature variations in the forward voltage of the LEDs, and those caused by noise in the system. The control algorithm is optimized to enable the output voltage to fall faster than it can rise as if the output voltage is too high, it can quickly cause thermal problems for the LED driver.
The LED driver monitors the switching regulator output voltage at node 226 to prevent the reference voltage VREF from being changed if the boost regulator has not caught up with the target reference value and generates an output voltage responsive to the reference voltage. This prevents the reference voltage from “running away” from the required value and taking a long time to come back in line once the boost regulator 202 has caught up. This is particularly important when the boost regulator 202 output voltage is dropping. This is due to the fact that the boost regulator 202 can produce a very fast rise in the output voltage, but the only way to reduce the output voltage is to allow the current source to discharge the output capacitor during its normal conduction time. This can take a significant amount of time to lower the output voltage if the LED duty cycles are very low. Thus, the system will not allow the reference voltage to be changed upwards if the feedback of the output level is significantly below the current reference voltage and will not allow the reference voltage to be changed downwards if the feedback of the output level is significantly above the current reference voltage. The configuration also provides over voltage protection without requiring additional circuitry as there is a maximum DAC code above which the boost regulator 202 will not go. This level can be modified by changing the pot down ratio to the pin.
Referring now to
If inquiry step 312 determines that none of the voltages at node 228 of the LED strings fall below the referenced voltage VLOW, inquiry step 304 determines whether during the entire PWM period all channels associated with each LED string 204, except those channels which are completely turned off (i.e., 0% PWMs/disabled), were conducting at least once and whether all channels had a voltage at the bottom of its LED string that was above VHIGH during conduction. If so, the regulated voltage is reduced by the counter/stepping algorithm 246. In this circumstance, the output of the comparator 238 would be at a logical “high” level for each LED string being driven by the LED driver, and these signals would drive the output of the AND gate 242 to a logical “high” level generating the DOWN signal at step 306. Responsive to the DOWN signal, the reference voltage VREF is decreased by the counter/stepping algorithm 246 and DAC 250 at step 308. The reduced reference voltage provided by the DAC 250 will cause a corresponding decrease in the regulated voltage provided at node 214 by the boost regulator 202 at step 310.
If inquiry step 304 determines that all channel voltages at node 228 are not above the reference voltage VHIGH for the entire PWM period, at least one of the voltages at nodes 228 is within the established voltage window, and the reference voltage is maintained at step 320. This causes the regulated voltage to be maintained at the established level at step 322. The process continues at step 324 and returns back to step 302 to continue monitoring the voltage at the bottom of each LED string at node 228.
Referring now to
The control algorithm and DAC 408 generates a correction offset that is added with the COMP voltage provided from the output of the integrator configured GM amplifier 402 to dramatically reduce the boost transients as described herein above. The control algorithm and DAC 408 generates the correction offset responsive to the provided COMP voltage and provided load information provided from control input 414. The load information would comprise the load current through inductor 207. The COMP voltage including the correction offset is provided to the inputs of a summation circuit 416. Also provided as input to the summation circuit 416 are a slope compensation ramp signal, the feedback voltage VFB, the reference voltage VREF, the voltage monitored at node 218 at the source of switching transistor 216 and connections to system ground. The output of the summation circuit 416 is provided as a control output to the R input of a latch circuit 418. The latch circuit 418 also receives at its S input, a leading edge blanking signal (LEB). The leading edge blanking signal is a fixed frequency clock signal with a very low duty cycle (short “HIGH” time) which set the 418 flip flop. It can be used as a leading edge blanking signal, as well, if the flip flop 418 is set dominant. The flip-flop 418 generates at its Q output drive signals to the switching transistor 216.
In a switching regulator 202, when a proportional control scheme is used, load regulation is very poor. Any increase in the load current through inductor 207 that is above the conduction point of the inductor 207 will result in a corresponding decrease in the output voltage VOUT. However, while the response to a load step causes a change in the output voltage level, the time taken to settle to the new voltage level is very fast. In an integral system, extra gain at low frequencies is used to eliminate most of this load regulation characteristic. This is at the expense of a fast transient response, as the system can only respond to a transient with a bandwidth defined by the GM amplifier gm and loop filter (COMP) network impedance. This means that a step increase in the load current will cause an initial output voltage fall followed by a correction. Likewise, when a load is reduced in a step, the initial transient is in a positive direction. The larger the load current transient, the larger the corresponding output transient. These scenarios are more fully illustrated in
Referring now to
There is a component in these transients illustrated in
For example, if the circuit is designed to drive 8 stacks of LEDs, there exist 9 possible load conditions. These load conditions are 0 amps (all stacks off), ILED (one stack conducting), 2XILED (two stacks conducting), . . . 8XILED (all 8 stacks conducting). Thus, over the course of operation, a control term specific to each of these load conditions may be provided. The control scheme related to the circuit of
This may be accomplished by the control algorithm and DAC 408 in a number of ways. In a first embodiment, a simple scheme uses a gain term that amplifies the input to the loop defined by the integrator 402. Given that the integral term is proportional to the inductor current IL (beyond the continuous conduction point), the gain may be varied to attempt to reduce the total range of the output of the integrator, formed from GM amplifier 402, over the range of possible load currents. In an LED driver system which uses PWM controls to dim the LEDs, a differential gain can be applied to each possible load combination (0 to N LED strings conducting), providing a much reduced integrator output swing, and therefore smaller voltage transients. This can be based on calculations of the inductor current at the time of design or simulation based, where a gain is picked via simulations that show the characteristics of the GM integrator output during the various load conditions. In non LED systems where the load is known but has many more states than is practical to implement discretely, the gain term can be continuous with a relationship between load and gain developed to best fit the application. This probably will not give a perfect fit, but so long as the total integrator range is reduced, the transient response is improved.
In an alternative embodiment, a more complex scheme can be used with discrete load steps. The integrator output can be monitored and make use of a digital control scheme to attempt to pull the output value to a known level. For example, the integrator output voltage goes up in response to a higher load current, and the system will add a contribution to the loop via the digital-to-analog controller (DAC) within block 408 to try and bring down the output voltage. Similarly, a contribution is removed from the loop when the output voltage goes down in order to attempt to bring it back up to a desired level. The latest digital-to-analog controller code used can be stored for each possible load level and applied at the start of any condition where the particular load is presented. In this manner, the system can build up and use a stored predetermined set of offset values as inputs to the loop to limit the range of the integrator output and minimize output voltage transients. The advantage of this method over the first alternative is that the effective gain of the integrator term in the loop does not change with load level and proportional control can still be carried out by use of a resistor in series with the compensation capacitor without providing varying proportional gains of the load current.
Referring now to
Referring now to
Referring now to
Duty cycle D=(Vout−Vin)Nout
Avg inductor current ILavg(average)=Iload*Vout/(Vin*efficiency)
Peak inductor current ILpeak=ILavg+Vin/L*D*T*0.5(for continuous system)
Capacitor ripple current Iripple=ILpeak
Capacitor ripple voltage Vripple=ESR*ILpeak
In a given system, where most of these terms are defined, the important figures for defining ripple are the peak inductor current which is defined by the load current and other factors, and the output capacitor ESR. In high voltage applications such as an LED driver where many LEDs are connected in series, the type of capacitors used to obtain the required output capacitances can have a relatively high ESR. This can provide high level output ripple. The operation of the integral control scheme will mean that the average value of this ripple wave form will be regulated to the required level. For most applications this is acceptable. However, LED driver systems attempt to regulate the voltage at the top of an LED string such that the voltage at the bottom is only just enough for the current source to function properly. This is done to minimize power dissipation in the LED driver. If this lower level is regulated to the average of the target level, the lower portions of the ripple are below the target and they push the current source into its linear region of operation. This will get worse as the load current and ESR increase and also if the number of LEDs increases thus increasing the inductor current. To solve this, the target voltage must be raised to guarantee that it does not affect operation. This is difficult to do in practice and will result in the headroom for the current sources being set higher than required to guarantee that there is never a problem, increasing potential power dissipation in cases where it is not needed.
Referring now to
The boost regulator produces the minimal voltage needed to enable the LED string 204 with the highest forward voltage drop to run at the programmed current. The circuit employs a current mode control boost architecture that has a fast current sense loop and a slow voltage feedback loop. This architecture achieves a fast transient response that is essential for notebook backlit applications where the power can be a serious drain on batteries or instantly charged to an AC/DC adaptor without rendering noticeable visual nuisance. The number of LEDs that can be driven by the circuit depends on the type of LED chosen by the application.
The circuit is capable of boosting up to 34.5 volts and driving 9 LEDs in series for each channel. However, other voltage boost levels and numbers of LEDs may be supported in alternative embodiments. The dynamic headroom control circuit controls the highest forward voltage LED stack or effectively the lowest voltage from any of the input current pins. The input current pin at the lowest voltage is used as a feedback signal for the boost regulator. The boost regulator drives the output to the correct levels such that the input current pin at the lowest voltage is at the target headroom voltage. Since all of these LED strings are connected to the same output voltage, the other input current pins will have a higher voltage, but the regulated current source on each channel will ensure that each channel has the same programmed current. The output voltage will regulate cycle by cycle and is always referenced to the highest forward voltage string in the architecture.
A common problem within switching converters that include integral control terms is that the output voltage level VOUT of the switching converter will overshoot at start up and when high load levels step to a lower level. This can create a variety of problems within the voltage regulator including providing an over voltage condition to the circuit being supplied by the converter. Thus, there is a need to provide some manner for picking up this overshoot voltage at an early stage and dramatically limiting its size by halting switching within the switching converter. Additionally, there is a need to enable the output voltage from a switching converter used with an LED driver to be held at the voltage level necessary for a start condition even when the LED off times are long during which the output capacitor associated with the switching converter would normally start to discharge due to self-discharge in the OVP (Over Voltage Protection) resistors across the capacitor. The switching converter implemented within, for example, the circuit of
Referring now to
The boost regulator also includes a diode 208 having its anode connected to node 1006 and its cathode connected to the output voltage node 1011. The output voltage node 1011 provides the output voltage VOUT which is applied to the LED strings discussed previously. A capacitor 212 is connected between node 1011 and ground. The boost controller 1010 controls operation of the switching transistor 216 responsive to a feedback voltage provided at feedback pin 1012 and a current to the switching transistor sensed at node 1008 via pin 1014. The feedback pin 1012 is connected to a resistor divider network consisting of resistors 1016 and 1018. Resistor 1016 is connected between node 1011 and node 1020 which is connected to the FB pin 1012 and resistor 1018 is connected between node 1020 and ground.
The boost controller 1010 includes an integrator consisting of a GM amplifier 402 and capacitor 1026 has one input connected to the feedback voltage pin 1012 and the other input connected to a reference voltage VREF. The integrator provides an output that is connected to one input of the summation circuit 416. The GM amplifier 402 may be used for eliminating large voltage overshoots at the output node 1010 and for holding the output voltage at a correct level even during extended LED off times. The output of the GM amplifier 402 is also connected to COMP pin 1022 to which a loop filter network is connected. The loop filter circuitry 1021 consists of a combination of a capacitor 1024 connected between node 1022 and ground and a series connection of a resistor 1026 and a capacitor 1028 that is connected in parallel with capacitor 1024 between pin 1022 and ground. Other loop filter configurations are also possible. The GM amplifier 402 also provides a control signal VOUTHIGH and FB_TOO_HIGH via control lines 1029 and 1031, respectively.
The summation circuit 416 receives the output from the integrator formed around GM amplifier 402, a ramp signal 1030 and the sensed current at node 1008 to generate a control output to switching control logic 1032. The switching control logic 1032 provides control signals to the switch driver 1034 for generating the PWM control signals to the switching transistor 216.
Referring now to
Transistor 1122 comprises an N-channel transistor having its drain/source path connected between node 1110 and ground. The gate of transistor 1122 is also connected to node 1110 and to the gate of another transistor 1124. Transistor 1124 comprises an N-channel transistor having its drain/source path connected between node 1126 and ground. A P-channel transistor 1128 has its source/drain path connected between node VDD 1106 and node 1126. The gate of transistor 1128 is connected to node 1120. A Schmitt trigger 1030 has its input connected to node 1026 and provides the output signal VOUTHIGH that is provided as the output of the GM amplifier 402.
The circuitry for use with the light load mode is implemented at node 1126. The Schmitt trigger 1130 is only used to determine when to switch in that the light load mode. A switch 1132 is connected between node 1126 and the COMP pin 1134. The compensation network includes a capacitor 1136 connected between pin 1134 and ground. Connected in parallel with the capacitor 1136 between pin 1134 and ground is a series connection of resistor 1138 and capacitor 1140. The switch 1132 is opened and closed based upon whether a load connected to the output node 1011 of the switching converter is zero. In normal mode, when a load is present, switch 1132 is closed and the compensation network is attached providing an integrator in the system. Pin 1134 comprises an analog output and is provided to the summation circuit 416. The output from node 1142 is ignored in this mode. When the load is zero, the switch 1132 is opened and disconnects the compensation network from the GM amplifier 402. This removes the integrator from the system. The output from node 1142 is used in the no load condition to give a digital switch/don't switch indication. In this mode, the output of summation circuit (a multi-input comparator) 416 is ignored as its output is invalid. The switch 1132 enables the operation of the light switching mode of operation when no load is present. This guarantees that the same regulation point is maintained, as the GM amplifier input offset is the same for both modes of operation.
In systems such as LED drivers where the load on the switching converter/switching regulator is known and can step to zero at various times during its operation, the switching converter is often turned off during “zero load” periods. The value on the GM amplifier output is typically held at a selected level to enable the system to snap quickly back to its previous regulation point when the load resumes. However, while the intended load is zero, there is usually a residual load provided by the feedback/OVP (over voltage protection) resistors connected to the output circuit, as well as self capacitor discharge. Some LED systems rely on keeping this output voltage poised at a correct level to resume conduction even during zero load periods in order to enable high accuracy, very short pulse currents to be generated from the correct voltage. This must typically be done using a large output capacitor to maintain the charge during these times (the “off” periods of the LED PWM switching times) from the previous time. If this was not done the current pulse can initially be compressed. Additionally, when fast pulses are used, the pulses can be finished before the switching current has had a chance to regulate back to the correct level. Additional problems arise if the current pulses are short enough, there is not enough time during these pulses for the converter to switch on, meaning that the converter spends its entire time not switching and cannot deliver the load current required even though the average load is very small.
The GM amplifier 402 maintains the output voltage level of the converter by enabling the DC switching converter to switch at low current levels during these zero load times. In systems where the GM amplifier output is sampled and held when the load is zero, the normal proportional control term feeding the switching loop is not present during these times making it impractical for the loop to regulate in a normal manner. Thus, a solution is needed for some other type of switching which still regulates the same target point including errors from the offsets normally in the closed loop. The GM amplifier described with respect to
When the load is zero, a control signal LED OFF causes switch 1132 to open and disconnects the compensation network connected at COMP pin 1134 from transistors 1124 and 1128. This causes node 1126 (the GM amplifier output node) to have a very low time constant, and swing high or low dependant on whether the output voltage is above or below the target. This provides an indication of whether the feedback signal is below or above the reference voltage VREF in a digital fashion. This operates as a comparator. This information can be used to initiate a short pulse in the inductor 1004, and keep doing so as long as the feedback voltage (1012) is below the reference voltage VREF. This causes the switching converter to switch and increase the output voltage. In this manner, the output level can be maintained indefinitely even when the load is zero.
Additionally, when the load is made up of very short pulses of current, and the switching converter cannot switch normally within the short pulse times, the current can instead be provided by the switching method during the zero load times. This means that not only can the voltage be maintained when not loaded, but when the pulses are long enough to allow the switching converter to switch, the converter can snap on and off to a very accurate level, with the minimal of VOUT transients, as the integrator output value (used during loaded conditions) is held in between, maintaining the information needed to control the loop regulation point during conduction. This implementation enables any offsets in the GM amplifier 402, which causes an error in the normal regulation point, to provide exactly the same error in a regulation point during the zero load mode of operation. This means that the voltage maintained at zero load should be as close as possible to the normal level.
The converter is switched responsive to an output from the GM amplifier 402 when the output voltage falls below the reference voltage VREF. A low current limit is used in the switch 216 such that the cycle terminates as soon as the current in the inductor reaches a fixed low level. This provides small fixed size current pulses into the load, which complete in less than one switching cycle, providing just enough energy to keep the output voltage at the required level. Should a single pulse not be sufficient, several pulses will occur consecutively to cause the output to reach the correct level. This can also be done by switching in a fixed duty cycle in this condition although it would be less well controlled. This solution is only applicable to designs that regulate VOUT correctly by monitoring VOUT continuously through, for example, a resistor stack. Some LED drivers take their feedback voltage from the bottom of the LED stack something that would not be possible here as these cases all output level information is lost when the LEDs are off.
Referring now to
Referring now back to
Transistor 1152 comprises a P-channel transistor having its source/drain path connected between node vdd and node 1154. The gate of transistor 1152 is connected to the gates of transistors 1144, 1128 and 1118. An N-channel transistor 1156 has its drain/source path connected between node 1154 and ground. The gate of transistor 1156 is connected with the gates of transistors 1148, 1124 and 1122 at node 1110. A Schmitt trigger 1158 has its input connected to node 1154 and its output provides a signal indicating when the feedback voltage is too low at node 1011 of the voltage converter. The Schmitt trigger 1158 generates an under voltage indication indicating the regulated output voltage has fallen below a second predetermined level and activates the voltage regulator in response thereto.
The circuitry of the GM amplifier 402, as illustrated in
The GM amplifier 402 illustrated in
This solution eliminates the need to know the offset of the GM amplifier 402. The offset is dominated by the input stage consisting of transistors 1102 and 1104 which is shared by all three input stages, and enables detection of a predictable window around the regulation point whatever the offset may be. This implementation can be used for a number of functions including voltage overshoot protection. So long as the output of the GM amplifier 402 is filtered, so as to guarantee that it will provide a constant indication that the feedback level is higher than the target value VREF for more than a fixed period of time (for example, at least one switching cycle), the filtered output can be used to stop the converter from switching. This allows the overshoot to be detected early and prevented from continuing. By filtering the signal in this way, the thresholds can be very close to the regulation level (approximately 6 millivolts has been used in one design) making voltage overshoot quite small. It is also advisable to use some hysteresis on the threshold to force the overshoot that has already occurred to recover slightly before allowing it to start switching again, here shown by the use of the Schmitt triggers 1150 and 1158, although other implementations are possible.
An overvoltage protection substitute function in an LED driver or similar application may also be provided. Any application that has a boost loop with a variable reference voltage input to the loop can use the above overshoot protection to prevent a true OVP event from occurring, but stopping switching if Vout goes more than a fixed amount above the target. Additionally, systems that must report when their output voltage is within a certain range of the target value may use this system either to provide a “start up complete” signal, an indication of heavy load/transients, or fault conditions, that can use both the outputs to say if it is below or above the target reference voltage.
Referring now back to
Referring now to
Referring now to
It will be appreciated by those skilled in the art having the benefit of this disclosure that this GM amplifier or a similar implementation can be used to providing overshoot protection and light switching mode during zero load conditions for an LED driver circuit. It should be understood that the drawings and detailed description herein are to be regarded in an illustrative rather than a restrictive manner, and are not intended to be limiting to the particular forms and examples disclosed. On the contrary, included are any further modifications, changes, rearrangements, substitutions, alternatives, design choices, and embodiments apparent to those of ordinary skill in the art, without departing from the spirit and scope hereof, as defined by the following claims. Thus, it is intended that the following claims be interpreted to embrace all such further modifications, changes, rearrangements, substitutions, alternatives, design choices, and embodiments.
This application is a continuation-in-part of U.S. patent application Ser. No. 12/492,748, filed Jun. 26, 2009, entitled DYNAMIC HEADROOM CONTROL FOR LCD DRIVER, and this application claims priority to U.S. Provisional Patent Application No. 61/246,433, filed Sep. 28, 2009, entitled INTEGRATION FOR PROVIDING OVERSHOOT PROTECTION AND LIGHT SWITCHING MODE DURING NON-ZERO LOAD CONDITIONS FOR AN LED DRIVER CIRCUIT, both of which are incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| 61246433 | Sep 2009 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 12492748 | Jun 2009 | US |
| Child | 12730960 | US |
