Patent Application
20080238750
The present disclosure relates to digital processors having an intelligent power control peripheral, and more particularly, to an intelligent power control peripheral that provides communications among individual peripherals, e.g., analog-to-digital converter (ADC), pulse width modulation (PWM) generator, analog comparator, digital-to-analog converter (DAC), etc., independent of the digital processor.
There are many digital processors having digital signal processing (DSP) capabilities and stand alone peripheral devices such as analog-to-digital converter (ADC), pulse width modulation (PWM) generator, analog comparator, digital-to-analog converter (DAC), etc. But all of these peripheral devices require that software running on the processor/DSP be involved in coordinating all of the behavior of these separate peripherals. This coordination by the digital processor requires that significant processor resources be expended on scheduling and coordination thereof rather then on the task of actually controlling a process, e.g., switch mode power supply (SMPS), brushed motor, etc. For example, because processor control, using a software program running in the processor, is required to intervene in the operation of the peripheral devices, support for current mode control in SMPS applications is not feasible. Current mode control requires that the control system respond very quickly to changing conditions, e.g., voltage and/or current. Current mode control requires pulse width modulation (PWM) responses within nanoseconds.
Therefore there is need for ways to overcome the above-identified problems as well as other shortcomings and deficiencies of existing technologies by providing communications among individual peripherals, e.g., ADC, PWM generator, analog comparator, DAC, etc., necessary for high speed current control in SMPS applications that are independent from a digital processor. According to teachings of this disclosure, an intelligent power control peripheral (IPCP) may provide (e.g., facilitate) communications among the individual peripherals independent from the digital processor. The IPCP may be used for critical timing control of SMPS systems, brushed motor control, and a host of other applications. The IPCP is a “Meta-Peripheral” that may incorporate a configurable inter-peripheral module communications network with digital PWM generators and timing logic therefore, at least one ADC, analog comparators and at least one DAC that may be configured to provide an automatic power control structure that may also provide automatic digital processor/DSP task and workload scheduling. This Meta-Peripheral may further use a configurable control fabric in combination with the aforementioned specialized peripherals for the utmost in control configuration flexibility.
According to a specific example embodiment of this disclosure, an intelligent power control peripheral may comprise: an analog-to-digital converter (ADC) having a plurality of analog inputs and a plurality of sample and hold trigger inputs, wherein digital data outputs and interrupt outputs from the ADC are available for coupling to digital inputs of a digital processor; a plurality of analog comparators; and a pulse width modulation (PWM) generation module, wherein the PWM generation module has digital inputs available for coupling to digital outputs of the digital processor; whereby the ADC, the plurality of analog comparators and the PWM generation module interact with each other without substantial intervention from the digital process.
According to another specific example embodiment of this disclosure, an intelligent power control peripheral may comprise: a digital processor; an analog-to-digital converter (ADC) having a plurality of analog inputs and a plurality of sample and hold trigger inputs, wherein digital data outputs and interrupt outputs from the ADC are coupled to digital inputs of the digital processor; a plurality of analog comparators; a pulse width modulation (PWM) generation module, wherein the PWM generation module has digital inputs are coupled to digital outputs of the digital processor; and an ADC sample trigger circuit coupled to the ADC for determining when to take analog samples; whereby the ADC, the plurality of analog comparators, the PWM generation module and ADC sample trigger interact with each other without intervention from the digital process.
A more complete understanding of the present disclosure thereof may be acquired by referring to the following description taken in conjunction with the accompanying drawings wherein:
While the present disclosure is susceptible to various modifications and alternative forms, specific example embodiments thereof have been shown in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific example embodiments is not intended to limit the disclosure to the particular forms disclosed herein, but on the contrary, this disclosure is to cover all modifications and equivalents as defined by the appended claims.
Referring now to the drawings, the details of specific example embodiments are schematically illustrated. Like elements in the drawings will be represented by like numbers, and similar elements will be represented by like numbers with a different lower case letter suffix.
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The ADC 104 may comprise a plurality of analog input channels 136 coupled to either a multiplexer 124 or a plurality of sample and hold circuits 130. The multiplexer 124 output may be coupled to a time shared sample and hold circuit 126. The plurality of sample and hold circuits 130 may be controlled by a plurality of trigger control multiplexers 132. The output of the time shared sample and hold circuit 126 and outputs of the plurality of sample and hold circuits 130 may be coupled to inputs of a multiplexer 128. The multiplexer 128 may be used to couple a selected one of its inputs to an internal analog to digital converter 134. The digitized data sample from the analog to digital converter 134 may be sent to the digital processor 102 over the data-in bus 110. The interrupt bus 112 may be used for indicating when conversion of the digitized data samples are valid. The data-in bus 110 and the interrupt bus 112 may be coupled to inputs of the digital processor 102, and the data-out bus 114 may be coupled to outputs of the digital processor 102.
The analog comparators 106 may be comprised of a plurality of analog input multiplexers 150 having outputs coupled to respective ones of a plurality of analog comparators 152. The plurality of analog comparators 152 outputs may be coupled to inputs of a plurality of digital multiplexers 160. The PWM generation module 108 may comprise a single event trigger (SEVNT TRG) 162, a master time base (M-TIMEBASE) 164, a plurality of trigger generators 166, a plurality of PWM generators (PWM GEN) 168, override (OVR) logic 170 having PWM outputs 172, and the plurality of digital multiplexers 160. The plurality of digital multiplexers 160 may receive digital inputs (e.g., logic 1 and 0, logic high and low, on and off, etc.) from the outputs 142 of the analog comparators 106 and/or from external signals 144. The IPCP 100 may also include scheduling timers, e.g., in the PWM module for timing, and comparator output logic changes to initiate and coordinate ADC and processor (e.g., software) tasks.
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While embodiments of this disclosure have been depicted, described, and are defined by reference to example embodiments of the disclosure, such references do not imply a limitation on the disclosure, and no such limitation is to be inferred. The subject matter disclosed is capable of considerable modification, alteration, and equivalents in form and function, as will occur to those ordinarily skilled in the pertinent art and having the benefit of this disclosure. The depicted and described embodiments of this disclosure are examples only, and are not exhaustive of the scope of the disclosure.
