Claims
- 1. A method of allocating interface resources in a behavioral synthesis tool used to design an integrated circuit, comprising:
reading a programming language source code description associated with the integrated circuit into the behavioral synthesis tool; storing the source code description as a data structure within the behavioral synthesis tool; receiving user input to select interface resources associated with the source code description; and modifying the data structure within the behavioral synthesis tool to include the selected interface resources.
- 2. The method of claim 1, wherein the user input is received through a graphical user interface.
- 3. The method of claim 1, wherein the user input is received through one or more of the following: a command line entry, a file, a user interface, and a pragma entered into the source code description.
- 4. The method of claim 1, further including searching the data structure for input/output/inout variables and displaying the variables in a graphical user interface.
- 5. The method of claim 4, further including automatically analyzing each variable to determine a type of interface resource associated therewith and automatically assigning an interface resource to each variable.
- 6. The method of claim 4, wherein modifying includes dragging and dropping the variables to map the variables to interface resources.
- 7. The method of claim 1, further including displaying variables from the source code description and interface resources associated with the variables in a hierarchical format.
- 8. The method of claim 1, further including generating RTL code based on the modified data structure.
- 9. The method of claim 1, further including reading an interface resource library into the behavioral synthesis tool, the interface resource library having candidate interface resources that can be used in the design.
- 10. The method of claim 9, wherein the interface resource library is for a multi-reconfigurable logic element.
- 11. The method of claim 1, further including parsing the source code description.
- 12. The method of claim 1, wherein the interface resources include one or more of the following: a wire, a register, and a tri-state gate.
- 13. The method of claim 1, wherein the interface resources include components handling complicated communication protocols.
- 14. A computer-readable medium having computer-executable instructions for performing the method of claim 1.
- 15. The method of claim 1, wherein the source code description is in a programming language that does not include timing information.
- 16. The method of claim 1, wherein the user input is received on a client computer and the data structure is modified on a server computer
- 17. A synthesis tool that allows for interactive memory allocation in the design of integrated circuits, comprising:
a source code description file that describes functionality of an integrated circuit without timing information; memory that stores an intermediate database associated with a source code description file of the integrated circuit; and a user interface that allows a designer to interactively map interface resources for the integrated circuit to variables in the source code description by modifying the intermediate database and without modifying the source code description file.
- 18. The tool of claim 17, wherein the user interface is a graphical user interface including a window listing, in hierarchical format, input/output/inout variables and interface resources associated with the input/output/inout variables.
- 19. The tool of claim 18, wherein the input/output/inout variables are pointers in the source code description.
- 20. The tool of claim 18, wherein the graphical user interface allows for dragging and dropping to associate variables with interface resources.
- 21. The tool of claim 17, wherein the database is used to generate RTL code.
- 22. The tool of claim 17, wherein the source code description is in the programming language of C or C++.
- 23. The tool of claim 17, wherein multiple variables are mapped to the same interface resource.
- 24. The tool of claim 17, wherein the interface resource includes a handshaking protocol.
- 25. A system for allocating interface resources in a behavioral synthesis tool used to design an integrated circuit, comprising:
means for displaying, in a graphical user interface, variables associated with a source code description of the integrated circuit; means for displaying, in the graphical user interface, interface resources associated with the variables; and means for assigning the variables to the interface resources using the graphical user interface.
- 26. The system of claim 25, wherein the graphical user interface displays the variables and interface resources in hierarchical format.
RELATED APPLICATION DATA
[0001] This application claims priority to U.S. patent application Ser. No. 09/839,376, filed Apr. 20, 2001 which claims priority to U.S. Provisional Patent Application No. 60/257,923, filed Dec. 21, 2000.