Claims
- 1. An FPGA comprising:
- a plurality of logic elements, each logic element receiving logic element input signals from a plurality of logic element input lines and providing a plurality of logic element output signals;
- a plurality of output lines formed to propagate selected ones of the logic element output signals in a single direction, including at least a first output line and a second output line, said first output line being of a length sufficiently different from a length of said second output line as to extend past a different number of logic elements from said second output line; and
- for each output line,
- a plurality of programmable interconnection points (PIPs) that may be programmed to apply one of said logic element output signals to said output line; and
- at least one programmable interconnection point (PIP) that may be programmed to apply a signal on said output line to one of said logic element input lines.
- 2. A programmable logic device comprising:
- a plurality of programmable logic units, each logic unit adapted to receive input signals from a plurality of input lines and to provide a plurality of output signals;
- for each programmable logic unit:
- a first logic-unit output line of a first length extending from the programmable logic unit; and
- a second logic-unit output line of a second length extending from the programmable logic unit;
- wherein the first length is longer than the second length so that the first logic-unit output line extends past a different number of programmable logic units than does the second logic-unit output line; and
- a plurality of programmable interconnection points that may be programmed to connect at least one of the first and second logic-unit output lines to at least one of the plurality of input lines.
- 3. The device of claim 2, wherein each logic unit further comprises:
- a configurable logic element (CLE) connected to selected ones of the input lines and having at least one CLE output line; and
- an interconnect structure for interconnecting the at least one CLE output line to selected ones of the logic-unit output lines.
- 4. The device of claim 2, wherein the number of programmable interconnection points located along at least one of the first and second logic-unit output lines decreases as the distance from the programmable logic unit increases.
- 5. The device of claim 2, wherein the first and second logic-unit output lines drive approximately equal loads, and thereby exhibit approximately equal propagation delay.
Parent Case Info
This application is a division of application Ser. No. 08/368,692, filed Jan. 4, 1995, U.S. Pat. No. 5,581,199.
US Referenced Citations (14)
Non-Patent Literature Citations (1)
Entry |
"The Programmable Logic Data Book" 1994, pp. 8-46 through 8-52, available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124. |
Divisions (1)
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Number |
Date |
Country |
Parent |
368692 |
Jan 1995 |
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