Claims
- 1. A field programmable gate array comprising:
a plurality of configurable logic blocks, including a first configurable logic block (CLB) having an N-bit output and a second configurable logic block (CLB) having an N-bit input; a plurality of interconnects; a plurality of interconnect switches capable of coupling ones of said plurality of interconnects to each other and to inputs and outputs of said plurality of configurable logic blocks; and an interconnect switch controller capable of controlling said plurality of interconnect switches, wherein said interconnect switch controller in a first switch configuration causes a first group of interconnects coupled to said N-bit output of said first CLB to be coupled to a second group of interconnects coupled to said N-bit input of said second CLB according to a first connection mapping and wherein said interconnect switch controller in a second switch configuration causes said first group of interconnects to be coupled to said second group of interconnects according to a second connection mapping.
- 2. The field programmable gate array as set forth in claim 1 wherein said interconnect switch controller comprises a memory capable of storing said first and second switch configurations.
- 3. The field programmable gate array as set forth in claim 2 wherein said memory comprises a static read only memory.
- 4. The field programmable gate array as set forth in claim 3 wherein said interconnect switch controller comprises at least one configurable logic block in said field programmable gate array.
- 5. The field programmable gate array as set forth in claim 1 wherein said first connection mapping causes said N-bit output of said first CLB having a first endian format to be coupled to said N-bit input of said second CLB in said first endian format and wherein said second connection mapping causes said N-bit output of said first CLB having said first endian format to be coupled to said N-bit input of said second CLB in a second endian format.
- 6. The field programmable gate array as set forth in claim 1 wherein said first connection mapping causes a least significant bit of said N-bit output of said first CLB to be coupled to a least significant bit of said N-bit input of said second CLB and causes the remaining N−1 bits of said N-bit output in an increasing order of significance to be coupled to the remaining N−1 bits of said N-bit input in an increasing order of significance.
- 7. The field programmable gate array as set forth in claim 6 wherein said second connection mapping causes a least significant bit of said N-bit output of said first CLB to be coupled to a most significant bit of said N-bit input of said second CLB and causes the remaining N−1 bits of said N-bit output in an increasing order of significance to be coupled to the remaining N−1 bits of said N-bit input in a decreasing order of significance.
- 8. The field programmable gate array as set forth in claim 1 wherein said first connection mapping causes the bits in a least significant byte of said N-bit output of said first CLB to be coupled to corresponding ones of the bits in a least significant byte of said N-bit input of said second CLB and causes the bits in a most significant byte of said N-bit output of said first CLB to be coupled to corresponding ones of the bits in a most significant byte of said N-bit input of said second CLB.
- 9. The field programmable gate array as set forth in claim 8 wherein said second connection mapping causes the bits in said least significant byte of said N-bit output of said first CLB to be coupled to corresponding ones of the bits in said most significant byte of said N-bit input of said second CLB and causes the bits in said most significant byte of said N-bit output of said first CLB to be coupled to corresponding ones of the bits in said least significant byte of said N-bit input of said second CLB.
- 10. A system-on-a-chip integrated circuit comprising:
a main memory for storing main program instructions; a processing circuit capable of executing said main program instructions; a plurality of embedded circuit components; and a field programmable gate array comprising:
a plurality of configurable logic blocks, including a first configurable logic block (CLB) having an N-bit output and a second configurable logic block (CLB) having an N-bit input; a plurality of interconnects; a plurality of interconnect switches capable of coupling ones of said plurality of interconnects to each other and to inputs and outputs of said plurality of configurable logic blocks; and an interconnect switch controller capable of controlling said plurality of interconnect switches, wherein said interconnect switch controller in a first switch configuration causes a first group of interconnects coupled to said N-bit output of said first CLB to be coupled to a second group of interconnects coupled to said N-bit input of said second CLB according to a first connection mapping and wherein said interconnect switch controller in a second switch configuration causes said first group of interconnects to be coupled to said second group of interconnects according to a second connection mapping.
- 11. The system-on-a-chip integrated circuit as set forth in claim 10 wherein said interconnect switch controller comprises a memory capable of storing said first and second switch configurations.
- 12. The system on-a-chip integrated circuit as set forth in claim 11 wherein said memory comprises a static read only memory.
- 13. The system-on-a-chip integrated circuit as set forth in claim 12 wherein said interconnect switch controller comprises at least one configurable logic block in said field programmable gate array.
- 14. The system-on-a-chip integrated circuit as set forth in claim 10 wherein said first connection mapping causes said N-bit output of said first CLB having a first endian format to be coupled to said N-bit input of said second CLB in said first endian format and wherein said second connection mapping causes said N-bit output of said first CLB having said first endian format to be coupled to said N-bit input of said second CLB in a second endian format.
- 15. The system-on-a-chip integrated circuit as set forth in claim 10 wherein said first connection mapping causes a least significant bit of said N-bit output of said first CLB to be coupled to a least significant bit of said N-bit input of said second CLB and causes the remaining N−1 bits of said N-bit output in an increasing order of significance to be coupled to the remaining N−1 bits of said N-bit input in an increasing order of significance.
- 16. The system-on-a-chip integrated circuit as set forth in claim 15 wherein said second connection mapping causes a least significant bit of said N-bit output of said first CLB to be coupled to a most significant bit of said N-bit input of said second CLB and causes the remaining N−1 bits of said N-bit output in an increasing order of significance to be coupled to the remaining N−1 bits of said N-bit input in a decreasing order of significance.
- 17. The system-on-a-chip integrated circuit as set forth in claim 10 wherein said first connection mapping causes the bits in a least significant byte of said N-bit output of said first CLB to be coupled to corresponding ones of the bits in a least significant byte of said N-bit input of said second CLB and causes the bits in a most significant byte of said N-bit output of said first CLB to be coupled to corresponding ones of the bits in a most significant byte of said N-bit input of said second CLB.
- 18. The system-on-a-chip integrated circuit as set forth in claim 17 wherein said second connection mapping causes the bits in said least significant byte of said N-bit output of said first CLB to be coupled to corresponding ones of the bits in said most significant byte of said N-bit input of said second CLB and causes the bits in said most significant byte of said N-bit output of said first CLB to be coupled to corresponding ones of the bits in said least significant byte of said N-bit input of said second CLB.
- 19. A bit-swapping method for use in a field programmable gate array, the field programmable gate array comprising 1) a first configurable logic block (CLB) having an N-bit output and a second CLB having an N-bit input; 2) a, plurality of interconnects; and 3) interconnect switches for coupling ones of the interconnects to each other and to inputs and outputs of the first and second configurable logic blocks, the method comprising the steps of:
setting the interconnect switches to a first switch configuration in which a first group of interconnects coupled to the N-bit output of the first CLB are connected to a second group of interconnects coupled to the N-bit input of the second CLB according to a first connection mapping; and receiving a second switch configuration; setting the interconnect switches to the second switch configuration in which the first group of interconnects are connected to the second group of interconnects according to a second connection mapping.
- 20. The method as set forth in claim 19 wherein the field programmable gate array comprises a memory capable of storing the first and second switch configurations.
- 21. The method as set forth in claim 19 wherein the first connection mapping causes the N-bit output of the first CLB having a first endian format to be coupled to the N-bit input of the second CLB in the first endian format and wherein the second connection mapping causes the N-bit output of-the first CLB having the first endian format to be coupled to the N-bit input of the second CLB in a second endian format.
- 22. The method as set forth in claim 19 wherein the first connection mapping causes a least significant bit of the N-bit output of the first CLB to be coupled to a least significant bit of the N-bit input of the second CLB and causes the remaining N−1 bits of the N-bit output in an increasing order of significance-to be coupled to the remaining N−1 bits of the N-bit input in an increasing order of significance.
- 23. The method as set forth in claim 22 wherein the second connection mapping causes a least significant bit of the N-bit output of the first CLB to be coupled to a most significant bit of the N-bit input of the second CLB and causes the remaining N−1 bits of the N-bit output in an increasing order of significance to be coupled to the remaining N−1 bits of the N-bit input in a decreasing order of significance.
CROSS-REFERENCE TO RELATED APPLICATION
[0001] The present invention is related to that disclosed in U.S. patent application Ser. No. ______ [Docket No. 01-B-008], filed concurrently herewith, entitled “INTERCONNECT CIRCUITRY FOR IMPLEMENTING LOGIC FUNCTIONS IN A FIELD PROGRAMMABLE GATE ARRAY AND METHOD OF OPERATION”. U.S. patent application Ser. No. ______ [Docket No. 01-B-008] is commonly assigned to the assignee of the present invention. The disclosure of this related patent application is hereby incorporated by reference for all purposes as if fully set forth herein.
Divisions (1)
|
Number |
Date |
Country |
Parent |
09774891 |
Jan 2001 |
US |
Child |
10407100 |
Apr 2003 |
US |