Claims
- 1. A field programmable gate array comprising:
a plurality of configurable logic blocks (CLBs); a plurality of interconnects; a plurality of interconnect switches capable of coupling ones of said plurality of interconnects to each other and to inputs and outputs of said plurality of configurable logic blocks; and an interconnect switch controller capable of controlling said plurality of interconnect switches, wherein said interconnect switch controller in a first switch configuration causes a first interconnect to be coupled to an output of a first CLB, causes a second interconnect to be coupled to an output of a second CLB, causes said first and second interconnects to be coupled to a third interconnect, and causes said third interconnect to be coupled to a pull-up device coupled to a power supply source of said field programmable gate array, said first, second and third interconnects and said pull-up device thereby forming a two-input OR gate.
- 2. The field programmable gate array as set forth in claim 1 wherein said interconnect switch controller comprises a memory capable of storing said first switch configuration.
- 3. The field programmable gate array as set forth in claim 2 wherein said memory comprises a static read only memory.
- 4. The field programmable gate array as set forth in claim 3 wherein said interconnect switch controller comprises at least one configurable logic block in said field programmable gate array.
- 5. The field programmable gate array as set forth in claim 1 wherein said pull-up device is a pull-up transistor.
- 6. The field programmable gate array as set forth in claim 1 further comprising a buffer having an input coupled to said third interconnect and an output coupled to an input of a third CLB.
- 7. The field programmable gate array as set forth in claim 6 wherein said buffer is a non-inverting line driver.
- 8. The field programmable gate array as set forth in claim 6 wherein said buffer is an inverting line driver, said first, second and third interconnects, said pull-up device, and said buffer thereby forming a two-input NOR gate.
- 9. A system-on-a-chip integrated circuit comprising:
a main memory for storing main program instructions; a processing circuit capable of executing said main program instructions; a plurality of embedded circuit components; and a field programmable gate array comprising:
a plurality of configurable logic blocks (CLBs); a plurality of interconnects; a plurality of interconnect switches capable of coupling ones of said plurality of interconnects to each other and to inputs and outputs of said plurality of configurable logic blocks; and an interconnect switch controller capable of controlling said plurality of interconnect switches, wherein said interconnect switch controller in a first switch configuration causes a first interconnect to be coupled to an output of a first CLB, causes a second interconnect to be coupled to an output of a second CLB, causes said first and second interconnects to be coupled to a third interconnect, and causes said third interconnect to be coupled to a pull-up device coupled to a power supply source of said field programmable gate array, said first, second and third interconnects and said pull-up device thereby forming a two-input OR gate.
- 10. The system-on-a-chip integrated circuit as set forth in claim 9 wherein said interconnect switch controller comprises a memory capable of storing said first switch configuration.
- 11. The system-on-a-chip integrated circuit as set forth in claim 10 wherein said memory comprises a static read only memory.
- 12. The system-on-a-chip integrated circuit as set forth in claim 11 wherein said interconnect switch controller comprises at least one configurable logic block in said field programmable gate array.
- 13. The system-on-a-chip integrated circuit as set forth in claim 9 wherein said pull-up device is a pull-up transistor.
- 14. The system-on-a-chip integrated circuit as set forth in claim 9 further comprising a buffer having an input coupled to said third interconnect and an output coupled to an input of a third CLB.
- 15. The system-on-a-chip integrated circuit as set forth in claim 14 wherein said buffer is a non-inverting line driver.
- 16. The system-on-a-chip integrated circuit as set forth in claim 14 wherein said buffer is an inverting line driver, said first, second and third interconnects, said pull-up device, and said buffer thereby forming a two-input NOR gate.
- 17. A field programmable gate array comprising:
a plurality of configurable logic blocks (CLBs); a plurality of interconnects; a plurality of interconnect switches capable of coupling ones of said plurality of interconnects to each other and to inputs and outputs of said plurality of configurable logic blocks; and an interconnect switch controller capable of controlling said plurality of interconnect switches, wherein said interconnect switch controller in a first switch configuration couples N interconnects between N CLB outputs and a common interconnect, each of said N interconnects being coupled between one CLB output and said common interconnect, and wherein said interconnect switch controller couples said common interconnect to a pull-up device coupled to a power supply source of said field programmable gate array, said N interconnects, said common interconnect, and said pull-up device thereby forming an N-input OR gate.
- 18. The field programmable gate array as set forth in claim 17 wherein said interconnect switch controller comprises a memory capable of storing said first switch configuration.
- 19. The field programmable gate array as set forth in claim 18 wherein said memory comprises a static read only memory.
- 20. The field programmable gate array as set forth in claim 17 wherein said interconnect switch controller comprises at least one configurable logic block in said field programmable gate array.
CROSS-REFERENCE TO RELATED APPLICATION
[0001] The present invention is related to that disclosed in United States Patent Application Serial No. [Docket No. 00-B-008], filed concurrently herewith, entitled “INTERCONNECT CIRCUITRY FOR IMPLEMENTING BIT-SWAP FUNCTIONS IN A FIELD PROGRAMMABLE GATE ARRAY AND METHOD OF OPERATION”. Patent Application Serial No. [Docket No. 00-B-008] is commonly assigned to the assignee of the present invention. The disclosure of this related patent application is hereby incorporated by reference for all purposes as if fully set forth herein.