Interconnect For a GMR Memory Cells And An Underlying Conductive Layer

Abstract

A conductive plug located in a planar dielectric layer, under GMR memory cells, are used to directly connect the lower ferromagnetic layer of one of the GMR memory cell and a conductive layer under the planar dielectric layer.

Description

BACKGROUND

1. Field of Invention

The present invention relates to a static memory. More particularly, the present invention relates to a magnetoresistive random access memory (MRAM).

2. Description of Related Art

MRAM is a type of non-volatile memory with fast programming time and high density. A MRAM cell of giant magnetoresistance (GMR) type has two ferromagnetic layers separated by a nonmagnetic conductive layer. Information is stored as directions of magnetization vectors in the two ferromagnetic layers.

The resistance of the GMR memory cell indicates a minimum value when the magnetization vectors of the two ferromagnetic layers point in substantially the same direction. On the other hand, the resistance of the GMR memory cell indicates a maximum value when the magnetization vectors of the two ferromagnetic layers point in substantially opposite directions. Accordingly, a detection of changes in resistance allows information being stored in the MRAM cell.

In conventional MRAM architecture, MRAM cells are placed on intersections of cell lines and word lines. The cell lines and word lines connect to the peripheral circuits and/or logic circuits through metal lines and/or metal plugs disposed on the peripheral area surrounding the MRAM area. Hence, the integration density is limited.

SUMMARY

A conductive plug located in a planar dielectric layer, under GMR memory cells, are used to directly connect the lower ferromagnetic layer of one of the GMR memory cell and a conductive layer under the planar dielectric layer.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention can be more fully understood by reading the following detailed description of the preferred embodiment, with reference made to the accompanying drawings as follows:

FIGS. 1A-1C are cross-sectional diagrams showing a method of fabricating an interconnect structure according to an embodiment of this invention; and

FIG. 1D is a cross-sectional diagram showing a structure of the conductive interconnects between adjacent GMR memory cells according to an embodiment of this invention, for example.

DETAILED DESCRIPTION

Reference will now be made in detail to the embodiments of the invention, examples of which are illustrated in the accompanying drawings.

FIGS. 1A-1C are cross-sectional diagrams showing a method of fabricating an interconnect structure according to an embodiment of this invention. In FIG. 1A, a substrate 100 having a patterned conductive layer 110 thereon is provided. Then, a planar first dielectric layer 120 is formed on the conductive layer 110.

The patterned conductive layer 110 represents a conducting circuit, such as a source/drain of a transistor. A material of the patterned conductive layer 110 can be any conductive material, such as doped semiconductor, metal or metal alloy. For example, Cu or Al—Cu alloy are usually used to fabricate interconnects in semiconductor integrated circuits. A material of the first dielectric layer 120 can be silicon oxide, silicon nitride, silicon oxynitride, metal oxide, or other usable dielectric materials, for example. The thickness of the dielectric layer is about 1500-3500 Angstroms, for example.

In FIG. 1B, the first dielectric layer 120 is patterned, such as a photolithography process and an etching process performed sequentially, to form an first opening 125 therein. After depositing a metal in the first opening 125 and on the first dielectric layer 120, a planarization process, such as chemical mechanical polishing (CMP), is performed to planarize the metal layer until the first dielectric layer 120 is exposed. Thus, a first conductive plug 130 is formed in the first opening 125. A material of the first conductive plug 130 can be tungsten or other conductive metals, for example.

In FIG. 1C, a first ferromagnetic layer, a nonmagnetic conductive layer, and a second ferromagnetic layer are sequentially deposited on the first dielectric layer 120 and the first conductive plug 130 and then patterned to form GMR memory cells 140. Each of the GMR memory cells 140 comprises a lower ferromagnetic layer 140a, a nonmagnetic conductive layer 140b, and an upper ferromagnetic layer 140c. The lower ferromagnetic layer 140a of one GMR memory cells 140 directly contact the first conductive plug 130 to build electrical connection. The GMR memory cell 140 directly connecting the first conductive plug 130 is usually located in one end of a GMR memory byte, which includes more than one GMR memory cells.

Next, conductive interconnects between adjacent GMR memory cells are formed to connect the adjacent GMR memory cells for forming a GMR memory byte. FIG. 1D is a cross-sectional diagram showing a structure of the conductive interconnects between adjacent GMR memory cells according to an embodiment of this invention, for example. In FIG. 1D, a second dielectric layer 150 can be deposited over the substrate 100 and then patterned to form second openings 160 in the second dielectric layer 150 for exposing the upper ferromagnetic layer 140c of the GMR memory cells 140. Then, second conductive plugs 170 are formed to fill the second openings 160. A conductive layer is deposited and then patterned to form conductive lines 180 connecting adjacent second conductive plugs 170 respectively located on the adjacent GMR memory cells 140. Accordingly, the conductive interconnects connecting the upper ferromagnetic layers 140c of the adjacent GMR memory cells 140 include the second conductive plugs 170 and the conductive lines 180 in FIG. 1D.

According to the embodiment provided above, the first conductive plug is located in the first dielectric layer below the GMR memory cells to connect the underlying conducting circuit. Hence, more options in layout design utilizing the GMR memory cells are allowed. Moreover, since the dielectric layer is thin, the step coverage of metal deposition is good.

It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.

Claims

1. A method of fabricating an interconnect for a GMR memory cells, comprising: forming a planar dielectric layer on a patterned conductive layer, which is on a substrate;patterning the dielectric layer to form an opening therein;forming a conductive plug in the opening to electrically connect the patterned conductive layer; andforming GMR memory cells directly on the conductive plug and the dielectric layer, wherein a lower ferromagnetic layer of one of the GMR memory cells directly connect the conductive plug.

2. The method of claim 1, wherein the dielectric layer is silicon oxide, silicon nitride, or silicon oxynitride.

3. The method of claim 1, wherein the conductive plug is a tungsten plug.

4. The method of claim 1, further comprising forming conductive interconnects connecting upper ferromagnetic layers of the adjacent GMR memory cells to form a GMR memory byte.

5. An interconnect for a GMR memory cells and a underlying conductive layer, comprising: a patterned conductive layer on a substrate;a planar dielectric layer on the conductive layer;a conductive plug, which are electrically connecting to the patterned conductive layer, located in the dielectric layer; andGMR memory cells on the conductive plugs and the dielectric layer, wherein a lower ferromagnetic layer of one of the GMR memory cells directly connect the conductive plug.

6. The interconnect of claim 5, wherein the dielectric layer is silicon oxide, silicon nitride, or silicon oxynitride.

7. The interconnect of claim 5, wherein the conductive plug is a tungsten plug.

8. The interconnect of claim 5, wherein the patterned conductive layer is a source/drain of a transistor.

9. The interconnect of claim 5, further comprising conductive interconnects connecting upper ferromagnetic layers of the adjacent GMR memory cells.