Patent Application
20130159587
1. Field of the Invention
The present invention relates in general to integrated circuits. In one aspect, the present invention relates to the repair of input/output and signal connections in integrated circuit devices.
2. Description of the Related Art
With today's high performance integrated circuit devices, millions of components (e.g., transistors, interconnects, pads, etc.) are integrated into one or more die to provide smaller and more powerful semiconductor packages. With ongoing demand to improve chip performance by increasing the component density, individual packaged devices include not only additional transistor counts, but also more power supply and input/output (I/O) pins. For example, stacked semiconductor devices are proposed to achieve increased device density by connecting multiple die together in a single package, resulting in even larger input/output (I/O) connection counts. However, with increased density comes higher failure rates due to challenges associated with forming I/O conductors through multiple interconnect metal and packaging substrate layers, especially where the fabrication technology is immature.
Accordingly, a need exists for an improved integrated circuit device and method for manufacturing same which addresses various problems in the art that have been discovered by the above-named inventor where various limitations and disadvantages of conventional solutions and technologies will become apparent to one of skill in the art after reviewing the remainder of the present application with reference to the drawings and detailed description which follow, though it should be understood that this description of the related art section is not intended to serve as an admission that the described subject matter is prior art.
Broadly speaking, the present invention provides an integrated circuit device, architecture, system, method of operation and method of manufacture wherein one or more replacement I/O interconnect paths are provided in an integrated circuit device having a plurality of default I/O interconnect paths so that the replacement I/O interconnect path(s) may be used as replacement channels should there be any failures in a channel associated with the default I/O interconnect paths. In this context, a channel refers to an I/O conductor path that may include one or more microbumps, through-silicon vias, bumps, solder balls, and/or other conductors connected to provide a voltage or signal path. In addition, a failure refers to an open-circuit (e.g., a microbump that does not electrically contact a connector in the interposer), a short-circuit (e.g., two or more separate channels connected together), an interconnect path with partial connectivity leading to high resistivity, or any functional defect in an interconnect path, such as defects resulting in frequency loss of data. To provide a replacement path which avoids or bypasses a failed I/O interconnect path, the replacement I/O interconnect path(s) are allocated with the default I/O interconnect paths using an interleaved placement to define physical and logical channels to improve failure coverage. In selected embodiments, a replacement I/O interconnect path is assigned to a plurality of default I/O interconnect paths in a first group of I/O interconnect paths which is interleaved with a second group of I/O interconnect paths. Within each group, a repair is performed by shifting the data away from the failed I/O interconnect path to the immediate neighbor I/O interconnect path. In addition, a method for controlling channel repair is provided wherein both devices sharing a defective channel/path are programmed to use a replacement I/O interconnect path to replace the defective channel/path.
In selected example embodiments, a multi-interconnect integrated circuit device and method of operation are disclosed whereby an input/output (I/O) circuit is used to convey one or more data channel groups over a plurality of fixed interconnect signal paths. The multi-interconnect integrated circuit may be implemented as a system on a chip (SoC), a system in package (SIP), a multichip package (MCP), a package-on-package (PoP), or a multichip module (MCM), such as a memory controller circuit and stacked memory device. As disclosed, the I/O circuit operable to convey the data channel group(s) between first and second integrated circuit die, and may be configured operate in at least a first mode (if there are no connection failures in a first plurality of default interconnect signal paths) and a second mode (if there is at least one connection failure in the first plurality of default interconnect signal paths). In selected embodiments, each fixed interconnect signal path is formed from one or more patterned conductor lines, microbumps, or through-silicon via conductors for conveying a data channel signal. In a first operational mode, the I/O circuit may be configured to convey a first data channel group over a plurality of default fixed interconnect signal paths if there are no connection failures in the default fixed interconnect signal paths. In a second operational mode, the I/O circuit may be configured to convey the first data channel group over a second plurality of fixed interconnect signal paths if there is at least one connection failure in the default fixed interconnect signal paths, where the second plurality of fixed interconnect signal paths includes a redundant fixed interconnect signal path for replacing a failed interconnect signal path from the default fixed interconnect signal paths. To detect connection failures, the I/O circuit may include test circuitry for detecting any connection failure in the default fixed interconnect signal paths. The disclosed redundant fixed interconnect signal path may be separate from the default fixed interconnect signal paths and not connected to convey a data channel if there are no connection failures in the default fixed interconnect signal paths. Alternatively, the redundant fixed interconnect signal path may be one of the default fixed interconnect signal paths (e.g., (e.g., error correction code (ECC) that is repurposed as the redundant fixed interconnect signal path if there is at least one connection failure in the default fixed interconnect signal paths. In selected embodiments, the I/O circuit includes a plurality of input and output multiplexers which are configured to convey the first data channel group as input/output data over the default fixed interconnect signal paths in response to one or more selection control signals indicating that there are no connection failures in the default fixed interconnect signal paths. The plurality of input and output multiplexers may also be configured to convey the first data Channel group as input/output data over the second plurality of fixed interconnect signal paths in response to one or more selection control signals indicating that there is at least one connection failure in the default fixed interconnect signal paths. With the disclosed I/O circuit, first and second interleaved data channel groups may be assigned to the fixed interconnect signal paths in the first and second plurality of fixed interconnect signal paths so that channels from the first and second interleaved data channel groups alternate in a row of fixed interconnect signal paths.
The present invention may be better understood, and its numerous objects, features and advantages made apparent to those skilled in the art by referencing the accompanying drawings. The use of the same reference number throughout the several figures designates alike or similar element.
a)-(b) illustrate the operation of a redundancy multiplexer circuit in accordance with selected embodiments of the present invention.
A integrated circuit package and associated method of fabrication and operation are described wherein one or more integrated circuit die are provided with multiple data channels that are routed across bidirectional input/output (I/O) interconnect paths, as well as to unidirectional channels (e.g., pinput or output) interconnect paths, including one or more extra or redundant I/O interconnect paths that can be used as replacement I/O interconnect paths if any of the regular channel interconnect paths fail. In packaging solutions with multiple die (e.g., a processor die with stacked DRAM connected across an electrical interface routing of conductor lines and microbump conductors) having a large (e.g., 6k) number of connection channels, redundant I/O interconnect paths can be used in place of default I/O interconnect paths that fail for any reason, such as a short between neighboring microbumps or a failure to make electrical contact with a microbump. By switching one or more redundant I/O interconnect paths as replacement I/O interconnect paths using a fixed or programmable multiplexer circuit, interconnect failures in the integrated circuit package can be repaired. In addition, adjacent channel failures can be repaired by using an interleaved physical and logical placement of the I/O interconnect paths to provide redundant I/O interconnect paths. In selected embodiments, first and second I/O connection channel groups are interleaved together, where each I/O connection channel group includes at least one redundant I/O interconnect path and a plurality of regular or mission-mode I/O interconnect paths such that data is steered to a redundant path if a regular or mission-mode path fails. In other embodiments, the interleaved I/O connection channel groups each include one or more non-data interconnect paths (e.g., error correction code (ECC) interconnect paths) that are used as a redundant I/O interconnect path(s) if a mission-mode path fails. Thus, instead of including extra redundant I/O interconnect paths, the ECC interconnect path is used as a replacement path. To facilitate path repair, a redundancy control mechanism allows both sides of a defective interconnect path to be aware of the defect, repair, and associated logical shifting operation, such as by having a master device scan interconnect paths for connectivity failures and then program an associated slave device with an address of any failed path.
Various illustrative embodiments of the present invention will now be described detail with reference to the accompanying figures. While various details are set forth in the following description, it will be appreciated that the present invention may be practiced without these specific details, and that numerous implementation-specific decisions may be made to the invention described herein to achieve the device designer's specific goals, such as compliance with process technology or design-related constraints, which will vary from one implementation to another. While such a development effort might be complex and time-consuming, it would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure. For example, selected aspects are depicted with reference to simplified cross sectional and block diagram depictions without including every device feature or geometry in order to avoid limiting or obscuring the present invention. Some portions of the detailed descriptions provided herein are presented in terms of algorithms and instructions that operate on data that is stored in a computer memory. Such descriptions and representations are used by those skilled in the art to describe and convey the substance of their work to others skilled in the art. In general, an algorithm refers to a self-consistent sequence of steps leading to a desired result, where a “step” refers to a manipulation of physical quantities which may, though need not necessarily, take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. It is common usage to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like. These and similar terms may be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise as apparent from the following discussion, it is appreciated that, throughout the description, discussions using terms such as “processing” or “computing” or “calculating” or “determining” or “displaying” or the like, refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage, transmission or display devices.
Turning now to
One of the die may be a microprocessor die 102, such as a graphics processing unit (GPU) or central processing unit (CPU). As described more fully below, the processor die 102 may include a memory controller module having a redundancy multiplexer circuit 103 along with input/output interface test circuitry that may be used to detect and repair I/O interconnect channel failures using one or more replacement I/O interconnect channels. The processor die 102 also includes I/O external terminals formed on a first face (not shown) and positioned for connection to microbump connectors 127 or other I/O conductor elements for purposes of defining interconnect channels over which data and other control signal information is conveyed. After determining that the processor die 102 passes a wafer or die test, the die 102 may be mounted onto an interposer substrate 120 using the microbump connectors 127.
In addition or in the alternative, the integrated circuit device 100 may include another die, such as a stacked semiconductor device. The stacked semiconductor device may be implemented as a stacked device which includes a logic interface chip 110 and one or more memory die 112, 114, 116. In selected embodiments, the stacked semiconductor device includes two stacks of up to sixteen DRAM dice. Each memory die (e.g., 112) has one or more arrays of memory cells (e.g., DRAM cell arrays) and circuitry for storing and retrieving data at the memory cells, such as sense amplifier circuits, address decoders, and other control circuits. Each memory die also includes external terminal contacts formed on the top and/or bottom surfaces and positioned to make electrical contact with the logic interface chip 110 or other memory die via patterned metal layers 111, 113, 115. Further, each of the memory die 112, 114, 116 may have signal conductor lines extending between the external terminal contacts on the top and bottom surfaces. As depicted, the logic interface chip 110 includes a redundancy multiplexer circuit (R-MUX) and other input/output interface test circuitry that is used to detect and repair I/O interconnect channel failures using one or more replacement I/O interconnect channels. After determining that the logic interface chip 110 and memory dice 112, 114, 116 pass a wafer or die test, the individual die are sequentially mounted onto the interposer substrate 12.0 using microbump connectors 126 and patterned metal or die-to-die vias layers 111, 113, 115.
The interposer 120 provides electrical interface routing between the die by spreading electrical connections to a wider pitch. Though not explicitly shown, the interposer 120 has a first plurality of external terminals formed on a first face for making electrical contact with the processor die 102 via microbump connectors 127, and also includes a plurality of metal interconnect lines 124-125 formed with through-silicon via and conductor lines and electrically connected to a second plurality of external terminals formed on the first face of the interposer 120 and positioned to make electrical contact with the stacked semiconductor device 110-116 via microbump connectors 126. The interposer 120 may also include additional external terminals formed on the first face (not shown) and connected to one or more through-silicon via and conductor lines 121-123 formed in the interposer 120 for purposes of connecting the processor die 102 to an external circuit or signal line using one or more data channels. For example a first data channel for the processor 102 is formed over an I/O interconnect which includes the interposer TSV 121 and package substrate TSV 131 which are connected to selected microbump conductor 127a, bump conductor 134a, and solder ball conductor elements 140a. Likewise, a second data channel is formed over an I/O interconnect which includes the interposer TSV 122 and package substrate TSV 132 which are connected via microbump conductor 127b, bump conductor 134b, and solder ball conductor elements 140b, while a third data channel is formed over an I/O interconnect which includes the interposer TSV 123 and package substrate TSV 133 which are connected via microbump conductor 127c, bump conductor 134c, and solder ball conductor elements 140c.
By mounting a microprocessor die (e.g., a graphics processing unit (GPU) or central processing unit (CPU) with a stacked memory die 110-116 on an interposer 120, low latency signals may be exchanged across I/O interconnect channels formed from routing lines 124-125 in the interposer 120. In addition or in the alternative, the processor die 102 may exchange signals with one or more die in a separate package (not shown) using I/O interconnect channels formed from I/O through-silicon via conductors 121-123, 131-133, bump conductors 134, and solder ball conductors 140. Whether forming internal or external interconnect channels, the integration and stacking process used to assemble the packaged integrated circuit device 100 will result in an increased probability of connection failure as the electrical connection count increases. The connection failures can be caused by faults of through electrodes extending through a die, contact electrodes (e.g., microbumps) connecting or shorting together, and/or interconnect conductors (e.g., microbumps) failing to make electrical connection as intended. Any single interconnect failure in a multi-die assembly can result in an expensive loss of known-good silicon, thereby reducing yield.
To prevent yield losses from interconnect failures, the integrated circuit device 100 may be provided with extra I/O interconnect channels and associated switching circuitry which are used to recover from interconnect channel failures. In the example of
The integrated circuit device 100 may also include extra I/O interconnect channels for repairing defective external I/O interconnect channels to external circuits. For example, an open or short circuit in an external I/O interconnect channel (e.g., D10) could be repaired by using an extra I/O connection channels (e.g., R3) as a replacement channel. To make the repair, the redundancy multiplexer 103 at the processor die 102, reassigns or shifts the failed channel 1310 to the replacement channel R3. Thus, instead of using the failed interconnect path (127b, 122, 134b, 132, 140b), the processor 102 switches to exchange signal information over the I/O interconnect defined by microbump 127a, interposer TSV 121, bump 134a, package substrate TSV 131, and solder bump conductor 140a. As will be appreciated, a corresponding reassignment or shift will be made at the external circuitry.
As will be appreciated, the interconnect channel repair scheme may be implemented in any integrated circuit device having a plurality of signal interconnections to or from individual die, including but not limited to stacked semiconductor devices with multiple signal interconnects where a defective signal interconnect path can be replaced with a replacement signal interconnect path. In general terms, the integrated circuit device includes a parallel arrangement of one or more replacement signal paths and a multiplexer circuit which bypasses a defective signal path and shifts the signals to include one or more of the replacement signal paths. The multiplexer circuit may implement any desired fixed or programmable switching function to steer data away from the failed signal path and to the replacement signal path.
To control the path switching operations which provide path redundancy, the integrated circuit device a redundancy control mechanism for detecting and repairing broken communication channels. Any desired connection test mechanism can be used to detect failed or defective I/O interconnect paths, including but not limited to software and/or hardware features for performing link tests between devices. By way of example and not limitation, low speed boundary scan tests can be performed to detect short circuit and open circuit defects. Other types of path defects can be detected, such as by performing loopback tests to discover path defects that result in frequency loss over the paths.
The redundancy control mechanism should also allow both d s of the broken communication channel (e.g., processor die 102 and stacked semiconductor die (110-116) to be aware of the defect, repair, and associated logical shifting operation. The coordinated redundancy control may be implemented by having a master device (e.g., processor 102) that scans the channels (e.g., DQ0-DQ7 and DMI) for connectivity failures and then programs the master device and associated slave device (e.g., stacked semiconductor die 110-116) accordingly. The address of the failed interconnect 10 path can be programmed in each device (e.g., in a repair mask register 230) so that each device can shifts the data as agreed to in the redundancy scheme. In various embodiments, the repair address can be a set of fuses or registers, and can be set as permanent repair or a temporary repair. An advantage of providing a temporary repair is to allow for changes in path failure status so that repairs can be changed accordingly. An example of a change in path failure status is where a failure changes as temperatures change in the system, or as the system ages, due to thermal stress and corrosion. By enabling the redundancy control mechanism to periodically detect the presence of channel connectivity failures as temperatures change over time, and/or at system boot, the path failures can be dynamically repaired over time.
To illustrate an example multiplex switching function, reference is now made to
To connect the output data channels (e. D0-D3) to their corresponding output interconnect paths, each output channel multiplex circuit (e.g., 212) may include an output multiplexer and amplifier connected to receive a plurality of output data channel signals (e.g., D3 and D2) that are connected across signal conductors 203. Under control of a selection signal 231, the output channel multiplex circuit selects and outputs one of the received output data channel signals to the associated output interconnect path conductor (e.g., 222)). By forming the signal conductors 203 to simultaneously connect each output data channel signal (e.g., D2) to one or more adjacent input/output channel multiplex circuits (e.g., 212-213), the output data channel signal can be connected to any of the connected output interconnect path conductors (e.g., 222.223) based on the applied selection signals 231.
As illustrated in
As will be appreciated, additional multiplex circuit configurations can be used to selectively connect each output data channel to additional interconnect paths. For example, each output channel multiplex circuit may be configured as a three-to-one multiplex functionality which is controlled by selection signals to select from three adjacent output data channels for output to an associated interconnect path. In this way, an output data channel can be shifted from a mission-mode or default interconnect path to either of two adjacent interconnect paths, depending on the connection state of each path. In addition or in the alternative, the redundancy multiplexer circuit 202 may include input channel multiplex circuits for switching the interconnect paths to a designated input data channel under control of one or more input selection signals. To this end, a defective interconnect path is not used, and the input data channels are instead conveyed over the spare interconnect path 221 and the non-defective interconnect paths using the input channel multiplex circuits to switch the input data channels to the appropriate data channels 201.
Turning now to
As will be appreciated, any number of replacement I/O interconnect paths may be used with each repair channel group. In addition, the physical and logical placement of the repair channel groups can affect the available failure coverage. For example,
To improve failure coverage, data channels may be allocated into repair channel groups that are physically interleaved with one another. To provide an example illustration, reference is now made to
If there are no defects or failures (e.g., open or short circuits) in any of the interleaved repair channel groups, then the multiplexer assigns each mission-mode data channel to its default I/O interconnect path, and no path shifting is required. To illustrate the default channel assignment, reference is made to
In the event that a defect or failure is detected in any I/O interconnect path in the interleaved repair channel groups, the defect in that repair channel group can be repaired by shifting data from the failed I/O interconnect path DQ12 to the next adjacent I/O interconnect path in the repair channel group. To this end, the multiplexer repairs a failure in the I/O interconnect path for channel DQ12 by shifting the DQ12, data to the default DQ11 I/O interconnect path, with a corresponding shift of the DQ11, DQ10, DQ9, and DQ8 channel data to the default DQ10, DQ9, DQ8, and RED1 I/O interconnect paths, respectively. With only the failed I/O interconnect path DQ12 being repaired, the remaining channel assignments for DQ0-DQ7 and DQ13-DQ15 would not be changed, and only the replacement I/O interconnect path associated with the defective repair channel group (RED1) is used.
The interleaved repair channel groups also enable repair of two non-adjacent I/O interconnect paths from two different repair channel groups. To illustrate this example, reference is now made to
Failures in vertically adjacent failed I/O interconnect paths (e.g., a vertical short) from two different repair channel groups can also be repaired with the interleaved repair channel groups. To illustrate this example, reference is now made to
With interleaved repair channel groups, failures in horizontally adjacent I/O interconnect paths from two different repair channel groups (e.g., a horizontal short) can also be repaired. To illustrate this example, reference is now made to
As seen from the foregoing, the interleaved allocation of repair channel groups can use two replacement I/O interconnect paths RED1, RED2 to repair an open circuit defect in each of the repair channel groups, and can also be used to repair a horizontal or vertical short circuit between two I/O interconnect paths. The repair feature uses extra I/O interconnect paths in interleaved repair channel groups to protect against both vertical and horizontal shorts between the repair channel groups, and can also protect against an open circuit failure in each repair channel group. It will be appreciated that the path switching function used with the interleaved repair channel groups illustrated in
Due to cost or space constraints, it may not always be feasible to add extra replacement I/O interconnect paths to a design as described hereinabove. In such cases, the path repair benefits may still be obtained by re-purposing one or more I/O interconnect paths to provide the repair function. For example, one or more ECC I/O interconnect paths associated with a group of data channels may be re-purposed as a replacement I/O interconnect path in the event of a failure of one of the default I/O interconnect paths associated with a data channel. While the resulting repaired data channel group will not support ECC operations, this is a relatively small price to pay for benefit of repairing a data channel group that would otherwise not be functional.
To illustrate how selected I/O interconnect paths can be repurposed as replacement paths to improve failure coverage, reference is now made to
If there are no defects or failures (e.g., open or short circuits) in any of the interleaved channel groups, then the multiplexer assigns each mission-mode data channel to its default I/O interconnect path, and no path shifting is required.
In the event that a defect or failure is detected in any I/O interconnect path in the interleaved channel groups (e.g., DQ0-DQ7 or DQ8-DQ15), the defect(s) in the channel group(s) can be repaired by forming a repair channel group using the ECC I/O interconnect path as a replacement I/O interconnect path, and then shifting data from the failed I/O interconnect path to the next adjacent I/O interconnect path in the repair channel group. In this way, interleaved repair channel groups can be formed and used to repair defective I/O interconnect paths from two different repair channel groups. To illustrate this example, reference is now made to
The repurposed ECC I/O interconnect paths can also be used to repair failures vertically-adjacent I/O interconnect paths (e.g., a vertical short) from two different data channel groups. This is illustrated in
In addition, the repurposed ECC I/O interconnect paths can be used to repair failures in horizontally-adjacent I/O interconnect paths (e.g., a horizontal short) from two different data channel groups. This is illustrated in
Turning now to
At step 1406, the interconnect links are tested to detect any defect or failures. Any desired link test can be performed, such as using boundary scan test procedures to detect short circuit and open circuit failures. In addition or in the alternative, at-speed tests can be performed to detect functional defects in the interconnect links, such as defects resulting in frequency loss of data.
If the link test indicates that there are no failed or defective interconnect links (negative outcome to decision step 1408), then the multi-interconnect device uses the default data channel assignments to perform data operations at step 1409. In an example scenario, the default chain order for a first data channel group would include interconnect links RED (unused), DQ8, DQ7, DQ6, DQ5, DQ4, DQ3, DQ2, DQ1, DQ0, DMI, ECC0. A multiplexer circuit controlled by one or more selection control signals may be used to assign the default interconnect links to the mission-mode data channels for performing read and write operations. If there are no link defects, the multiplexer does not assign the RED link to a data channel.
However, if the link test indicates that there are one or more failed or defective interconnect links (affirmative outcome to decision step 1408), then the data channels for the multi-interconnect device are remapped to bypass the defective interconnect link(s) at step 1410, and the data operations are performed using remapped data channels at step 1411. In an example scenario where a defect is detected at default DQ6 link, the chain order for the first data channel group is remapped to RED (now DQ8), DQ8 (now DQ7), DQ7 (now DQ6), DQ6 (unused), DQ5, DQ4, DQ3, DQ2, DQ1, DQ0, DMI, and ECC0. The remapping may be implemented by applying the selection control signal(s) to the multiplexer circuit so that the data read and write operations are performed using the remapped data channels. In this way, the multiplexer is configured to implement a predetermined shift rule whereby any failed interconnect link is bypassed and not used, and all data channels up to the failed interconnect link are shifted “leftward” towards a replacement interconnect link. As described herein, the replacement interconnect link may be an extra or repurposed interconnect link.
In embodiments where the data channel remapping is performed once (e.g., at during manufacture test), the method ends (step 1414), as indicated by the dashed line 1412. However, the data channel remapping may also be iterated over time to dynamically update and adjust the channel mapping based on changing interconnect link conditions. In this case, a decision is periodically made at step 1413 to determine if another interconnect link test should be performed. This decision my be implemented by running a timer which determines when the next interconnect link test is performed. Upon detecting that another interconnect link test is to be performed (affirmative outcome to decision 1413), the method loops back perform the link test (step 1406). Otherwise, the method ends (step 1414).
By now it will be appreciated that there is disclosed herein a method and apparatus for conveying one or more data channel groups to or from a first multi-interconnect device. In the disclosed multi-interconnect device, data channels are conveyed using at least one spare interconnect path and a plurality of default interconnect paths initially allocated to each data channel group in a default allocation. In selected embodiments, spare interconnect path(s) may include a dedicated spare interconnect path or an interconnect path for a feature, such as an error correction code (ECC) feature, that can be programmatically disabled. Upon detecting a failed interconnect path in the plurality of default interconnect paths, the functional interconnect paths are identified, a data channel group is routed to or from the first multi-interconnect device using the plurality of functional interconnect paths and the spare interconnect path. The detection step may be performed once, or repeatedly at predetermined intervals to dynamically identify functional interconnect paths over time. In selected embodiments, the data channel group is routed by applying one or more selection control signals to a plurality of multiplexers connected, respectively, to the spare interconnect path and the plurality of default interconnect paths, where each multiplexer is connected between an interconnect path and a plurality of data channels from a data channel group and is controlled by the one or more selection control signals to route the data channel group to avoid the failed interconnect path. In other embodiments, the data channel group is routed by shifting a first initially allocated data channel away from the failed interconnect path and toward the spare interconnect path to use a first adjacent interconnect path with corresponding shifts of any affected initially allocated data channels so that the spare interconnect path is used. The data channel groups may include first and second interleaved data channel groups that arc initially allocated, respectively, to first and second rows of interconnect paths so that data channels from the first and second interleaved data channel groups alternate in each of the first and second rows of interconnect paths. In this case, the first interleaved data channel group may be routed to avoid the failed interconnect path using a predetermined shift pattern to shift a first initially allocated data channel away from the failed interconnect path and toward the first spare interconnect path. When exchanging data channel groups over the spare interconnect path and a plurality of default interconnect paths with a second multi-interconnect device, the first interconnect device may identifying the failed interconnect path to a second multi-interconnect device so that both the first and second multi-interconnect devices may be programmed to avoid the at least one failed interconnect path.
In another form, there is disclosed a stacked semiconductor device and associated method of fabrication. In the stacked semiconductor device, a memory controller circuit is connected to a stacked memory device over a plurality of fixed interconnect signal paths for conveying one or more data channel groups between the memory controller circuit and the stacked memory device. The memory controller circuit may include, for each data channel group, a plurality of multiplexer circuits connected to a spare interconnect signal path and a plurality of default interconnect signal paths initially allocated to a first data channel group. The multiplexer circuits are configurable to operate in at least a first mode (if there are no connection failures in the plurality of interconnect signal paths) and a second mode (if there is at least one connection failure in the plurality of interconnect signal paths). In this way, the multiplexer circuits, when configured in the first mode, convey the first data channel group over the plurality of default interconnect signal paths. And when configured in the second mode, the multiplexer circuits convey the first data channel group using the spare interconnect signal path to route the first data channel group to avoid a failed interconnect signal path detected in the plurality of default interconnect signal paths.
As described herein, selected aspects of the invention as disclosed above may be implemented in hardware or software. Thus, some portions of the detailed descriptions herein are consequently presented in terms of a hardware-implemented process and some portions of the detailed descriptions herein are consequently presented in terms of a software-implemented process involving symbolic representations of operations on data bits within a memory of a computing system or computing device. Generally speaking, computer hardware is the physical part of a computer, including its digital circuitry, as distinguished from the computer software that executes within the hardware. The hardware of a computer is infrequently changed, in comparison with software and hardware data., which are “soft” in the sense that they are readily created, modified or erased on the computer. These descriptions and representations are the means used by those in the art to convey most effectively the substance of their work to others skilled in the art using both hardware and software.
The particular embodiments disclosed above are illustrative only and should not be taken as limitations upon the present invention, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. Accordingly, the foregoing description is not intended to limit the invention to the particular form set forth, but on the contrary, is intended to cover such alternatives, modifications and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims so that those skilled in the art should understand that they can make various changes, substitutions and alterations without departing from the spirit and scope of the invention in its broadest form.
