Patent Application
20180269273
The invention relates generally to semiconductor device fabrication and, in particular, to methods for contacting a metal-insulator-metal (MIM) capacitor and structures including a MIM capacitor.
On-chip passive elements, such as MIM capacitors, are deployed in many types of integrated circuits, such as radiofrequency integrated circuits. A MIM capacitor may be integrated into one or more of the metallization levels of a back-end-of-line (BEOL) interconnect structure using materials that are commonly available in copper BEOL technologies. A two-electrode MIM capacitor includes top and bottom conductive plates, which operate as electrodes, and an interplate dielectric layer disposed between the top and bottom conductive plates as an electrical insulator. The capacitance, or amount of charge held by the MIM capacitor per unit of applied voltage, depends among other factors on the area of the top and bottom conductive plates, their separation, and the dielectric constant of the material constituting the interplate dielectric layer.
Over-etch may be used during via formation to reliably guarantee penetration through etch stop layers incorporated into a device structure. A problem that may be encountered with a MIM capacitor is that, during the over-etching process, a via may penetrate completely through one or both of the conductive plates of the MIM capacitor. If such a punchthrough event occurs, then a circuit reliability problem or even a catastrophic failure may result. As via heights are scaled downwardly, the height difference among the multiple depth vias is reduced. As a result, the sensitivity of the passive elements to over-etch may be exacerbated and a MIM capacitor may be more susceptible to punchthrough events. The marginality of landing vias of smaller dimensons on the conductive plates may also lead to reductions in yield and reliability if one or both of the vias are misaligned.
Improved methods for contacting a MIM capacitor, as well as improved structures including a MIM capacitor, are needed.
In an embodiment of the invention, a structure includes a dielectric layer on an electrode of a metal-insulator-metal capacitor, and a conductive plug in a via that extends vertically through the dielectric layer to contact the electrode. The dielectric layer is comprised of a polymer, such as polyimide.
In an embodiment of the invention, a method includes forming a dielectric layer on an electrode of a metal-insulator-metal capacitor, and forming a via that extends vertically through the dielectric layer to the electrode. The method further includes forming a conductive plug in the via that contacts the electrode. The dielectric layer is comprised of a polymer, such as polyimide.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various embodiments of the invention and, together with a general description of the invention given above and the detailed description of the embodiments given below, serve to explain the embodiments of the invention.
With reference to
A dielectric layer 20 is formed on the dielectric layer 18. In an embodiment, the dielectric layer 20 may be comprised of an organic polymeric material or polymer, such as a thermosetting polymer. In an embodiment, the dielectric layer 20 may be comprised of polyimide, which is chemically and thermally stabile, and which has a high mechanical strength. The dielectric layer 20 may be electrically insulating and, in that connection, may have a dielectric constant that is characteristic of a dielectric material. The dielectric layer 20 may be applied by spin-coating a poly(amic) acid solution onto the dielectric layer 18, and then curing at an elevated temperature (e.g., less than or equal to 400° C.) in an inert ambient. A thin layer of adhesion promoter, such as an organosilane, may be spin-coated on the top surface of the dielectric layer 18 before the dielectric layer 20 is formed on the dielectric layer 18.
With reference to
A dielectric layer 34, which is similar in composition to dielectric layer 20, is formed on the MIM capacitor 24 and dielectric layer 20 after the electrodes 28, 32 are patterned. In an embodiment, the dielectric layer 34 may be comprised of an organic polymeric material or polymer, such as a thermosetting polymer. In an embodiment, the dielectric layer 34 may be comprised of polyimide, which is chemically and thermally stabile, and which has a high mechanical strength. The dielectric layer 34 may be electrically insulating and, in that connection, may have a dielectric constant that is characteristic of a dielectric material. The dielectric layer 34 may be applied by spin-coating a poly(amic) acid solution onto the MIM capacitor 24 and dielectric layer 20, and then curing at an elevated temperature (e.g., less than or equal to 400° C.) in an inert ambient. A thin layer of adhesion promoter, such as an organosilane, may be spin-coated before the dielectric layer 34 is formed.
With reference to
The etching process that forms vertical sections of the vias 38, 40, 42 in the dielectric layer 34 and a vertical section of the via 38 in the dielectric layer 20 may rely on an etching process with high selectivity to the materials of the conductive wiring feature 16, top electrode 28, and bottom electrode 32. In an embodiment in which the dielectric layers 20, 34 are composed of polyimide, an oxygen-based etch using an O2 plasma may be used to form the sections of the vias 38, 40, 42 in the dielectric layers 20, 34. In an alternative embodiment, a small amount of fluorine-containing gas may be added to the etching mixture.
Via 38 is required to be taller than either via 40 or via 42, which leads to the need to over-etch via 40 and via 42 in order to extend via 38 in the vertical direction to the conductive wiring feature 16. Because of the high selectivity of the etch process removing the organic polymeric material of the dielectric layers 20, 34, the vias 40 and 42 have a lower probability of respectively punching through the bottom electrode 32 or the top electrode 28 in comparison with conventional processes in which the dielectric layers 20, 34 are replaced by inorganic materials. In addition, the process margin for opening the vias 38, 40, 42 to the desired locations is improved.
With reference to
A chemical-mechanical polishing (CMP) process may be used to remove excess liner material and conductor from the top surface of dielectric layer 34 and to planarize the conductive lines 48, 50, 52 to be flush with the top surface of dielectric layer 34. Conductive line 48 is electrically and physically connected by the conductive plug 54 with the top electrode 28. Conductive line 50 is electrically and physically connected by the conductive plug 56 with the bottom electrode 32. Conductive line 52 is electrically and physically connected by the conductive plug 58 with the conductive wiring feature 16 in dielectric layer 12.
The mechanical properties of the organic polymeric material (i.e., polymer) comprising the dielectric layer 20 and the dielectric layer 34 differ from the mechanical properties of inorganic dielectric materials, such as silicon dioxide (SiO2) or silicon nitride (Si3N4). In particular, the polymer comprising the dielectric layers 20, 34 may exhibit a lower elastic modulus and a higher Poisson's ratio than inorganic dielectric materials so that the dielectric layers 20, 34 are comparatively softer and less rigid. As examples, silicon dioxide is characterized by an elastic modulus of 66-73 GPa and a Poisson's ratio of 0.17, silicon nitride is characterized by an elastic modulus of 200 to 310 GPa and a Poisson's Ratio of 0.27, and polyimide is characterized by an elastic modulus of 2.5 to 3.2 GPa and a Poisson's Ratio of 0.35. For these exemplary materials, the elastic modulus of polyimide is an order of magnitude smaller than the elastic modulus of either silicon dioxide or silicon nitride, and the Poisson's Ratio of polyimide is at least 30% larger than the Poisson's Ratio of either silicon dioxide or silicon nitride. As a result, the organic polymeric material constituting the dielectric layers 20, 34 may operate as a stress reliever in subsequent processing operations.
In addition, the organic polymeric material constituting the dielectric layers 20, 34 may have a lower dielectric constant than inorganic dielectric materials, such as silicon dioxide (SiO2) or silicon nitride (Si3N4). For example, polyimide has a dielectric constant of 3.5, which is less than the dielectric constant (3.9 to 4.1) of silicon dioxide and the dielectric constant (9.5) of silicon nitride.
The methods as described above are used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (e.g., as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in a single chip package (e.g., a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (e.g., a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case, the chip may be integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either an intermediate product or an end product.
References herein to terms such as “vertical”, “horizontal”, “lateral”, etc. are made by way of example, and not by way of limitation, to establish a frame of reference. Terms such as “horizontal” and “lateral” refer to a direction in a plane parallel to a top surface of a semiconductor substrate, regardless of its actual three-dimensional spatial orientation. Terms such as “vertical” and “normal” refer to a direction perpendicular to the “horizontal” and “lateral” direction. Terms such as “above” and “below” indicate positioning of elements or structures relative to each other and/or to the top surface of the semiconductor substrate as opposed to relative elevation.
A feature “connected” or “coupled” to or with another element may be directly connected or coupled to the other element or, instead, one or more intervening elements may be present. A feature may be “directly connected” or “directly coupled” to another element if intervening elements are absent. A feature may be “indirectly connected” or “indirectly coupled” to another element if at least one intervening element is present.
The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
