Patent Grant
9592030
Field
The technology described herein relates to ultrasound devices and related methods and apparatus.
Related Art
Ultrasound imaging probes exist. Conventionally, distinct probes are required for imaging in two dimensions (2D) or three dimensions (3D). Separate design and manufacture of such distinct probes are required, which increases cost and limits versatility of the probes.
Also, conventional ultrasound probes are designed for connection to specialized control systems. The probes themselves include transducers but typically lack any control circuitry for controlling operation of the transducers or processing signals received by the transducers. Rather, control of the transducers and processing of signals received by the transducers is performed by the specialized control systems. The specialized control systems are available to only a select few. Such design further limits the versatility and accessibility of the ultrasound probes.
Aspects of the present application provide a highly integrated, microfabricated ultrasound transducer probe which may serve as a stand-alone ultrasound transducer probe and which is configured to be interconnectable with other such transducer probes to form ultrasound devices capable of two-dimensional (2D) and three-dimensional (3D) ultrasound imaging. In some embodiments, the ultrasound transducer probe includes microfabricated ultrasonic transducers integrated with integrated circuitry controlling operation of the ultrasonic transducers and providing multiple electronic interfaces for connecting the ultrasound transducer probe to one or more external devices. In some embodiments, the device is a complete ultrasound-on-a-chip containing all transducers and electronics to perform collection and processing of ultrasound signals. Final image processing may be performed on or off the chip.
The external devices may perform some processing and/or image generation with ultrasound data provided by the ultrasound transducer probe. In some embodiments, the ultrasonic transducers of the ultrasound transducer probe may be configured suitably to enable 2D imaging and the transducer probe itself may include a substrate with a suitable geometry to provide a 1D aperture or 1.5D aperture in some embodiments. A 1.5D aperture, and thus a 1.5D device (e.g., a 1.5D ultrasound transducer probe) is one in which focusing is provided along one dimension of the aperture. The integrated circuitry may be at least partially programmable to allow for coordinated operation between multiple such interconnected ultrasound transducer probes, for example when providing higher dimensional imaging functionality than that provided by a single instance of the ultrasound transducer probe.
The ultrasound transducer probes may be operated as sensors and/or sources of ultrasound energy. For example, the ultrasound transducer probes may be operated as ultrasound imaging probes in some embodiments, sensing ultrasound energy from a subject. The ultrasound energy may be emitted by the same ultrasound transducer probe detecting the ultrasound energy, or may be emitted by a distinct source. In some embodiments, the ultrasound transducer probe may be operated as a source, for example a source of high intensity focused ultrasound (HIFU).
Further aspects of the present application provide ultrasound devices making use of the microfabricated ultrasound transducer probe described above, ultrasound imaging techniques utilized by such devices, and methods of fabricating, operating, and/or interconnecting the microfabricated ultrasound transducer probe.
According to an aspect of the application, an apparatus is provided comprising a substrate, a plurality of ultrasonic transducers on the substrate, and control circuitry on the substrate, coupled to the plurality of ultrasonic transducers and configured to control operation of the plurality of ultrasonic transducers. The apparatus further comprises a first interface, the first interface being of a first type, and a second interface, the second interface being of a second type. The first and second interfaces may be individually configured to transfer electronic signals between the control circuitry and an external device.
According to an aspect of the application, an apparatus is provided comprising a single substrate ultrasound-on-a-chip imaging device comprising multiple different interface types supporting different data transfer rates.
According to an aspect of the application, an apparatus is provided comprising a substrate including a plurality of ultrasound elements, a first interface of a first type on the substrate, and a second interface of a second type that is different than the first type on the substrate.
According to an aspect of the application, a method is provided, comprising forming a plurality of ultrasonic transducers on a substrate, forming control circuitry on the substrate, coupled to the plurality of ultrasonic transducers, and forming a first interface of a first type on the substrate and a second interface of a second type on the substrate. The first and second interfaces may be individually configured to provide an electrical connection between the control circuitry and an external device.
According to an aspect of the application, an apparatus is provided, comprising a substrate, a plurality of ultrasonic transducers on the substrate, and control circuitry on the substrate, coupled to the plurality of ultrasonic transducers and configured to control operation of the plurality of ultrasonic transducers. The control circuitry comprises a waveform generator coupled to at least one ultrasonic transducer of the plurality of ultrasonic transducers, the waveform generator being configurable to generate different kinds of waveforms.
According to an aspect of the application, an apparatus is provided, comprising a substrate having a width and height, the width being at least twice as large as the height, and a plurality of ultrasonic transducers on the substrate. The apparatus further comprises control circuitry on the substrate, coupled to the plurality of ultrasonic transducers and configured to control operation of the plurality of ultrasonic transducers.
According to an aspect of the application, an apparatus is provided, comprising a plurality of ultrasound transducer probes tiled and interconnected to form an ultrasound imaging device. Each ultrasound transducer probe of the plurality of ultrasound transducer probes includes a plurality of ultrasonic transducers and control circuitry coupled to the plurality of ultrasonic transducers and configured to control, at least in part, operation of the plurality of ultrasonic transducers. The control circuitry includes interface circuitry configured to interface the ultrasound transducer probe to an external device.
According to an aspect of the application, an apparatus is provided, comprising at least one substrate having a first dimension and a second dimension that is perpendicular to the first dimension. The first dimension is at least twice as great as the second dimension. The apparatus further comprises a plurality of ultrasonic transducers on the substrate, the plurality of ultrasonic transducers being arranged along the first dimension and the second dimension of the substrate. The apparatus further comprises control circuitry coupled to the plurality of ultrasonic transducers and configured to control operation of the plurality of ultrasonic transducers.
According to an aspect of the application, a method of forming an ultrasound device is provided, comprising dicing at least first and second ultrasound transducer probes of a plurality of ultrasound transducer probes on a wafer, and tiling and interconnecting the at least first and second ultrasound transducer probes.
According to an aspect of the application, a device is provided comprising a plurality of complementary metal oxide semiconductor (CMOS) ultrasound transducer elements, and CMOS control circuitry coupled to the plurality of CMOS ultrasound transducer elements and configured to control the CMOS ultrasound transducer elements to support one-dimensional (1D), two-dimensional (2D), and three-dimensional (3D) ultrasound imaging.
According to an aspect of the present application, a complementary metal oxide semiconductor (CMOS) integrated circuit (IC) is provided comprising an array of ultrasound transducer elements and CMOS control circuitry coupled to the array of ultrasound transducer elements and configured to control operation of the array of ultrasound transducer elements to support both two-dimensional (2D) and three-dimensional (3D) ultrasound imaging.
According to an aspect of the application, an apparatus is provided, comprising a complementary metal oxide semiconductor (CMOS) substrate and a plurality of ultrasonic transducers on the CMOS substrate. The apparatus further comprises a CMOS integrated circuit (IC) on the CMOS substrate and coupled to the plurality of ultrasonic transducers, wherein the CMOS IC is configured to support a voltage signal that is greater than approximately 20 V.
According to an aspect of the application, an apparatus is provided, comprising a complementary metal oxide semiconductor (CMOS) substrate having a top metal layer configured to conduct a power signal. The apparatus further comprises an ultrasonic transducer disposed above the top metal layer and including an electrode, wherein the electrode is connected to the top metal layer by an electrically conductive via.
According to an aspect of the application an apparatus is provided comprising a complementary metal oxide semiconductor (CMOS) substrate having a top metal layer. The top metal layer has a thickness between approximately 0.5 microns and approximately 10 microns. The apparatus further comprises an ultrasonic transducer disposed above the top metal layer.
According to an aspect of the application, an apparatus is provided comprising a complementary metal oxide semiconductor (CMOS) substrate having a metal layer having a thickness between approximately 0.5 microns and approximately 10 microns. The apparatus further comprises an ultrasonic transducer having an electrode. The apparatus further comprises a via connecting the electrode to the metal layer of the CMOS substrate.
According to an aspect of the application, an apparatus is provided comprising a complementary metal oxide semiconductor (CMOS) substrate comprising a metallization layer and a wiring line. The apparatus further comprises an ultrasonic transducer on the CMOS substrate. The metallization layer is configured to distribute a power signal and is configured as an electrical shield between the ultrasonic transducer and the wiring line.
According to an aspect of the application, an apparatus is provided, comprising a complementary metal oxide semiconductor (CMOS) substrate and an ultrasonic transducer on the CMOS substrate. The ultrasonic transducer comprises a membrane sealing a cavity in the CMOS substrate and further comprises a thin film electrode. The cavity is between the thin film electrode and the membrane.
According to an aspect of the application, a method of fabricating an ultrasonic transducer is provided, comprising forming the ultrasonic transducer above a top metal layer of a complementary metal oxide semiconductor (CMOS) substrate, and connecting the ultrasonic transducer to the top metal layer with at least one electrically conductive via.
According to an aspect of the application a method of manufacturing an ultrasonic transducer is provided, comprising forming a complementary metal oxide semiconductor (CMOS) substrate, the CMOS substrate including a metal layer, and forming an electrically conductive via through a portion of the CMOS substrate. The method further comprises forming the ultrasonic transducer above the CMOS substrate, wherein at least a portion of the ultrasonic transducer is electrically coupled to the CMOS substrate through the electrically conductive via.
According to an aspect of the application, a method is provided, comprising printing a photolithography pattern on a wafer, rotating the wafer by approximately 180 degrees after printing the photolithography pattern on the wafer, and printing a copy of the photolithography pattern on the wafer after rotating the wafer by approximately 180 degrees such that the pattern on the wafer and the copy of the pattern on the wafer are aligned with each other.
According to an aspect of the application, a method is provided comprising printing a photolithography pattern on a wafer, rotating the wafer after printing the photolithography pattern on the wafer, and printing a copy of the photolithography pattern on the wafer after rotating the wafer such that the pattern on the wafer and the copy of the pattern on the wafer are aligned with each other.
According to an aspect of the application, a method is provided, comprising illuminating a reticle having a pattern thereon to print a pattern on a wafer, the pattern on the reticle having a first side substantially opposite a second side, and the pattern on the wafer having a first side substantially opposite a second side. The method further comprises rotating the wafer approximately 180 degrees, and aligning the second side of the pattern on the reticle with the second side of the pattern on the wafer. The method further comprises, subsequent to aligning the second side of the pattern on the reticle with the second side of the pattern on the wafer, illuminating the reticle.
According to an aspect of the application, a method is provided, comprising scanning a first portion of a reticle with a photolithographic scanner to print a first pattern on a wafer, the first portion being less than the entire reticle. The method further comprises stepping the wafer. The method further comprises, subsequent to stepping the wafer, scanning a second portion of the reticle with the photolithographic scanner to print a second pattern on the wafer in alignment with the first pattern, the second portion being less than the entire reticle and being different than the first portion.
According to an aspect of the application, a method is provided comprising tiling ultrasound transducer probes on a wafer by printing different patterns from one or more reticles on the wafer. Printing different patterns may comprise using a blade to obstruct at least a portion of at least one reticle during tiling.
According to an aspect of the application, a method is provided comprising scanning a first portion of a pattern mask with a scanner to print a first pattern on a wafer, the pattern mask including a first, second, third, and fourth alignment mark thereon. The first portion includes an area between the first alignment mark and the third alignment mark. The method further comprises moving the wafer, and scanning a second portion of the pattern mask with the scanner to print a second pattern on the wafer in alignment with the first pattern. The second portion includes an area between the second alignment mark and the fourth alignment mark.
Various aspects and embodiments of the application will be described with reference to the following figures. It should be appreciated that the figures are not necessarily drawn to scale. Items appearing in multiple figures are indicated by the same reference number in all the figures in which they appear.
Overview
Aspects of the present application provide a microfabricated ultrasound transducer probe which may represent a universal building block to construct various types of ultrasound imaging and/or HIFU devices operable in various modes by mere replication and suitable connection of multiple copies of the transducer probe. In some embodiments, the ultrasound transducer probe is suitable to operate as a standalone ultrasound transducer probe. One-dimensional (1D), one and a half dimensional (1.5D), two-dimensional (2D), and three-dimensional (3D) ultrasound imaging devices capable of implementing highly advanced ultrasound imaging techniques may be fabricated easily by replication of, suitable dicing of, and interconnection of the ultrasound transducer probe, with minimal or no redesign of the ultrasonic transducers and integrated circuitry of the ultrasound transducer probe. As a result, the ultrasound transducer probe is highly versatile, providing flexibility in achieving an ultrasound device of choice.
Various features of the microfabricated ultrasound transducer probe may contribute to its versatility and provide flexibility to an end user. One such feature is the inclusion of multiple types of interfaces for electrically connecting to different types of external devices. In some embodiments, higher speed and lower speed interfaces may be provided as part of the ultrasound transducer probe for communicating electrical signals with external devices at different rates. The higher speed interface(s) may facilitate connection of the ultrasound transducer probe to any desired external processing device, such as specialized field programmable gate arrays (FPGA), graphics processing units (GPU), or other devices suitable for receiving and processing ultrasound data, for example to form one or more ultrasound images. The higher speed interface(s) may be configured in some embodiments to maximize the output of ultrasound data, which may be in digital form, from the ultrasound transducer probe. In some embodiments, then, the higher speed interface(s) may be used when complex ultrasound applications are to be performed, such as 3D ultrasound imaging. The lower speed interface(s), by contrast, may be configured in some embodiments to allow for connection of the ultrasound transducer probe to a consumer electronics device with lesser processing capabilities than some types of devices to which the higher speed interface(s) may be connected, and thus may be suitable when performing ultrasound applications not requiring the amount of data provided by the higher speed interface(s). Such functionality may make the ultrasound transducer probe usable by a wide range of end users who lack access to more sophisticated graphics processing systems, thereby making an important medical diagnostic tool accessible to a large number of people. Thus, the interface configuration of the ultrasound transducer probe may enhance the transducer probe's versatility by allowing for connection to a wide range of external devices, and may provide a user flexibility in choosing to which external device(s) to connect.
Other features of an ultrasound transducer probe which may be provided according to some aspects of the present application and which may contribute to the transducer probe's versatility include the transducer probe's physical form and the architecture of the transducer probe circuitry. The ultrasound transducer probe may be microfabricated on a substrate (e.g., a chip, such as a semiconductor chip) having a geometry that provides for a suitable aperture. In some embodiments, for example, the substrate may allow for a suitable one-dimensional (1D) aperture, for instance being wider than it is tall (e.g., a wide aspect ratio substrate). Such a form factor may allow the transducer probe to function suitably as a 1D imaging device for performing 2D imaging while allowing for multiple replicas of the transducer probe to be tiled horizontally and/or vertically to provide enhanced 2D or 3D imaging functionality. As used herein, “tiled” means arranged next to each other to form, in combination, a larger device. In some embodiments, the ultrasound transducer probe may be a 1.5D device capable of tiling to provide enhanced 2D or 3D imaging functionality.
Interconnection of multiple tiled replicas of the ultrasound transducer probe in a manner suitable to form a larger ultrasound transducer probe may be facilitated by suitable relative physical positioning of the ultrasonic transducers and integrated processing or control circuitry on the substrate. As used herein, the term “control circuitry” may include, but is not limited to, circuitry that may control operation of the ultrasonic transducers and/or processing circuitry that processes signals transmitted to and/or received from the ultrasonic transducers. In some embodiments, a portion of the control circuitry may be positioned beneath an arrangement of ultrasonic transducers on the substrate, with other integrated circuitry including input/output (I/O) circuitry positioned on one or more peripheral regions (e.g., a tab in some embodiments) of the substrate. Such physical placement may facilitate tiling multiple copies of the ultrasound transducer probe by allowing for creation of a substantially continuous arrangement of ultrasonic transducers when tiled while providing suitable external access to the circuitry of the transducer probes, i.e., not obstructing the I/O circuitry when the transducer probes are tiled.
The integrated circuitry (e.g., integrated control circuitry) of the ultrasound transducer probe may also facilitate interconnection of the transducer probe with other such transducer probes, for example when tiled as described above. In some embodiments, the integrated circuitry may be at least partially programmable, thus allowing for the ultrasound transducer probe to be programmed to operate as a standalone transducer probe or in conjunction with one or more additional such transducer probes. The programmable circuitry may include programmable timing circuitry and/or a programmable waveform generator for generating (or producing) excitation signals to excite the ultrasonic transducers. The waveform generator may be programmable to generate a desired kind of waveform from among multiple possible kinds, including impulses, continuous waves, chirp waveforms (e.g., linear frequency modulation (LFM)) chirps), and coded excitations. Such flexibility in the waveform generated may also facilitate the use of highly advanced ultrasound imaging techniques, non-limiting examples of which are described further below.
The ultrasound transducer probe may include micromachined ultrasonic transducers having features which facilitate creation of a standalone ultrasound transducer probe, and which also facilitate formation of ultrasound devices by interconnection of multiple copies of the ultrasound transducer probe. In some embodiments, the ultrasound transducer probe may be formed on a complementary metal oxide semiconductor (CMOS) substrate. In some embodiments, the CMOS substrate may include a top metal layer, which in some embodiments may be a thick top metal layer (also referred to in some embodiments as an ultra-thick redistribution layer), which may be utilized for power distribution to the ultrasonic transducers. Such a configuration may facilitate suitable power distribution to all ultrasonic transducers of the transducer probe over the relatively large distances which the power signal may travel in some embodiments. When the thick top metal layer is used for power distribution, the ultrasonic transducers may be formed above the thick top metal layer, and may be connected to the thick top metal layer with a suitable electrically conductive via structure including one or more electrically conductive vias. In some such embodiments, one electrically conductive via may connect a bottom electrode of an ultrasonic transducer to the thick top metal layer of the CMOS substrate, and a second electrically conductive via may connect a membrane of the ultrasonic transducer to the thick top metal layer. Further details of such structures are described further below, along with methods of fabricating such structures.
Some aspects of the present application provide wafer-level fabrication techniques for fabricating ultrasound transducer probes of the types described herein. For example, interconnection of multiple copies of an ultrasound transducer probe may be achieved in multiple ways according to different embodiments by suitable positioning of the ultrasound transducer probes on a wafer and suitable dicing. In some embodiments, multiple copies of the ultrasound transducer probes may be suitably tiled and interconnected on a wafer and then diced together to form a single-substrate ultrasound device, for instance to meet certain performance specifications for the device. In other embodiments, individual copies of the ultrasound transducer probe or groups of multiple instances of the ultrasound transducer probe may be diced from a wafer and interconnected after dicing. According to aspects of the present application, scanning and/or stepping technologies may be used to suitably position multiple instances of an ultrasound transducer probe on a wafer.
In some embodiments, multiple instances of an ultrasound transducer probe may be aligned on a wafer by printing a pattern from a reticle on the wafer, rotating the wafer, and printing the pattern again. In some embodiments, an ultrasound transducer probe may be formed by printing portions of a pattern from a reticle on the wafer in alignment with each other. Blading techniques may be used to print desired portions of the reticle pattern, and stepping and/or scanning may be used to provide proper alignment of the various portions printed.
As described previously, some embodiments of the present application provide an ultrasound transducer probe which may serve as a building block (also referred to in some embodiments as a “repeatable unit” or simply a “unit,” a “module,” or by other similar terminology) for constructing ultrasound imaging devices with desired imaging capabilities. In some such embodiments, the ultrasound transducer probe may be a 1D ultrasound transducer probe, but not all embodiments are limited in this respect. For instance, the building block ultrasound transducer probe may be a 1.5D or 2D transducer probe in some embodiments.
The aspects and embodiments described above, as well as additional aspects and embodiments, are described further below. These aspects and/or embodiments may be used individually, all together, or in any combination of two or more, as the application is not limited in this respect.
Standalone and Tiled Ultrasound Transducer Probes
According to an aspect of the present application, different types of ultrasound devices with different ultrasound imaging and/or HIFU capabilities may be created utilizing a common, repeatable ultrasound transducer probe, which in some embodiments may be a 1D ultrasound transducer probe or a 1.5D ultrasound transducer probe.
The ultrasound device 100 may be a 1D ultrasound transducer probe, configured with a 1D aperture formed by a plurality of ultrasonic transducers which may be microfabricated on a substrate (e.g., a semiconductor substrate in some embodiments). The ultrasound device 100 may further include control circuitry configured to control, at least in part, the ultrasonic transducers. Non-limiting examples of suitable 1D ultrasound transducer probes which may serve as the ultrasound device 100 are described in further detail below, for example in connection with
The ultrasound device 100 may have any suitable dimensions, including a width W1 and height H1. In some embodiments, the ultrasound device 100 may be a 1D ultrasound transducer probe configured with a 1D aperture, and thus the width W1 may be greater than the height H1 in some such embodiments. In some embodiments, the width W1 may be between approximately 20 mm and approximately 40 mm, or any value within that range. In some embodiments, the height H1 may be between approximately 2 mm and approximately 10 mm, or any value within that range. In some embodiments, a square ultrasound device 100 may be provided having a width W1 equal to the height H1.
The external device 104 may be a device configured to receive and process ultrasound data provided by the ultrasound device 100. In some embodiments, the external device 104 may be a consumer electronics device (e.g., the illustrated smartphone) having a display 108 for displaying ultrasound data and/or ultrasound images based on ultrasound data produced by the ultrasound device 100. However, other types of external devices may be utilized as the various aspects described herein are not limited to the particular type of external device to which the ultrasound transducer probe is connected.
The ultrasound device 110 may be connected to an external device 112 via the wired connection 106. In the example shown, the external device 112 is a tablet computer having a display 114 for displaying ultrasound data and/or ultrasound images based on ultrasound data produced by the ultrasound device 110. However, other types of external devices may be used.
The ultrasound device 116 may be a 2D ultrasound transducer probe formed by suitable vertical tiling (also referred to herein as “stacking”) and interconnection of multiple copies of the ultrasound device 100. Thus, the ultrasound device 116 may have the same width W1 as ultrasound device 100 and a height H2 greater than the height H1 of ultrasound device 100. The height H2 may be, for example, N×H1, wherein N represents the number of ultrasound devices 100 tiled vertically to create the ultrasound device 116. In some embodiments, N may equal 2, 4, 8, may be between 2 and 10, or may assume any other suitable integer value.
The ultrasound device 116 may be connected to an external device 118 by the wired connection 106. The external device 118 may be any suitable external device, including any suitable consumer electronics device. In the non-limiting example illustrated, the external device 118 is a laptop computer having a display 120 for displaying ultrasound data and/or ultrasound images based on ultrasound data produced by the ultrasound device 116.
Although not shown, it should be appreciated that an ultrasound device may be constructed from horizontal and vertical tiling of multiple copies of the ultrasound device 100, thus effectively representing a combination of ultrasound device 110 and ultrasound device 116. For example, two of the ultrasound devices 100 may be tiled horizontally, defining a “row” that is two ultrasound transducer probes wide, and two or more such rows of two ultrasound transducer probes may be tiled vertically (e.g., 2 such rows, 4 such rows, 8 such rows, or any other suitable number of such rows). Thus, an ultrasound transducer probe having a desired size and aperture may be easily created by suitable tiling of an ultrasound transducer probe like ultrasound device 100. The ultrasound device 100 may therefore serve as a (universal) building block for building an ultrasound device with target size and aperture characteristics, and therefore specified imaging and/or HIFU capabilities.
A further example of an ultrasound device which may be formed utilizing multiple copies of the ultrasound device 100 of
The ultrasound devices 116 in
Also provided in
Thus,
The ultrasound devices illustrated in
It should be appreciated that the ultrasound transducer probes shown in
As previously described, the width W1 and height H1 may assume any suitable values. In some embodiments, the aspect ratio of the substrate 202, defined as the width relative to the height, may be greater than or equal to 1.5:1, greater than or equal to 2:1, greater than or equal to 3:1, greater than or equal to 4:1, greater than or equal to 5:1, between 2:1 and 16:1, between 4:1 and 10:1, or any range or value within such ranges, as non-limiting examples. The substrate 202 may be said to be a wide aspect ratio substrate when the aspect ratio is greater than or equal to 3:1. In some embodiments, the width W1 may be between approximately 20 mm and approximately 40 mm, or any value within that range. In some embodiments, the height H1 may be between approximately 2 mm and approximately 10 mm, or any value within that range. As a non-limiting example, the width W1 may be approximately 32 mm and the height H1 may be approximately 4 mm. In
It should be appreciated that the ultrasound transducer probes 200 and 210 may be 1.5D ultrasound transducer probes in some embodiments. For example, a suitable number of ultrasonic transducers may be provided along the height H1 to allow for focusing of ultrasound energy in the height dimension.
It should be appreciated from
It should be appreciated that alternative configurations of a repeatable ultrasound transducer probe to those shown in
As shown, the ultrasound transducer probe 300 may include a substrate 302 on which may be a plurality of ultrasonic transducers 304 and integrated circuitry 306, which may perform control and/or processing functions. Interfaces 308a and 308b may provide electrical communication between the ultrasound transducer probe 300 and an external device (e.g., any of the external devices illustrated in
The ultrasonic transducers 304 may be capacitive micromachined ultrasonic transducers (CMUTs), CMOS ultrasonic transducers (CUTs), which are monolithically integrated ultrasonic transducers and CMOS ICs, or other ultrasonic transducers compatible with a CMOS substrate. In some embodiments, the ultrasonic transducers 304 may be formed on the substrate 302 using microfabrication techniques, and in some embodiments may be monolithically integrated with the substrate 302. For example, the substrate 302 may be a CMOS substrate and the ultrasonic transducers 304 may be monolithically integrated with the CMOS substrate.
The plurality of ultrasonic transducers 304 may be arranged to form a 1D (or 1.5D) aperture on the substrate 302, and the integrated circuitry 306 may operate the plurality of ultrasonic transducers in a 2D mode. The integrated circuitry may, in such an example, include transmit and receive circuitry. The ultrasound transducer probe 300 may be considered an ultrasound system-on-a-chip in some embodiments.
Various features of the ultrasound transducer probe 300, as well as ultrasound transducer probes 200 and 210 are now described in further detail.
Interface
Aspects of the present application provide an ultrasound transducer probe having multiple types of interfaces for electrically connecting the transducer probe to external devices via corresponding wired or wireless links. For example, higher speed and lower speed interfaces may be provided to allow an end user flexibility in choosing a type of device to which to connect the ultrasound transducer probe.
The interfaces 308a and 308b may represent physical interfaces and may be considered part of the integrated circuitry 306. They may provide for electrical communication between the ultrasound transducer probe 300 and an external device. In some embodiments, the interfaces 308a and 308b may be of different types, configured to connect to different types of external devices. For example, the interface 308a may be of a type configured to connect to external devices capable of receiving and processing large amounts of ultrasound data, such as a specialized FPGA, a GPU, or other suitable device. By contrast, the interface 308b may be configured to operate with more widely available communication protocols used for consumer electronics devices, such as universal serial bus (USB) connections. Accordingly, the ultrasound transducer probe 300 may be highly versatile, allowing for the highest possible performance via connection to an external device with interface 308a or allowing for use with widely accessible consumer electronics via interface 308b, thus expanding the accessibility of ultrasound technology compared to current devices. The end user may choose between which interface to use in some embodiments.
When the interfaces 308a and 308b represent different types of physical interfaces, they may differ in the communication protocols supported and/or the speed of data communication supported (i.e., the data rate supported). For example, interface 308a may be a higher speed interface while interface 308b may be a lower speed interface. Thus, the interface 308a may be configured to maximize the amount of data which the ultrasound transducer probe 300 may provide to an external device, and thus may be used in situations in which advanced ultrasound imaging techniques are desirably implemented, high resolution is desired, fast frame rates are desired, or other imaging characteristics facilitated by high speed communication are desired. In some embodiments, a high speed interface may support data rates above approximately 4 gigabits per second (Gbps), above approximately 5 Gbps, above approximately 9 Gbps, above approximately 10 Gbps, above approximately 12 Gbps, above approximately 15 Gbps, above 30 Gbps, between approximately 9 Gbps and approximately 100 Gbps, between 15 Gbps and 50 Gbps, any data rate within those ranges, or any other suitable data rate. These data rates may represent maximum data rates in some embodiments.
By comparison, the interface 308b may be a relatively low speed interface suitable for supporting communication with consumer electronics (e.g., a portable device) or other external devices which may not be capable of performing the same level of ultrasound data processing as that provided by external devices connectable to the interface 308a, but which may be more widely available. When the interface 308b represents a relatively low speed interface, it may support less sophisticated ultrasound imaging techniques, may provide lower resolution ultrasound data, may provide lower frame rates, or otherwise provide a decrease in performance compared to that provided by interface 308a. In some embodiments, the interface 308b may be configured to support data rates less than approximately 10 Gbps, less than approximate 5 Gbps, less than approximately 4 Gbps, less than approximately 3 Gbps, less than approximately 2 Gbps, any data rate within those ranges, or any other suitable data rate. These data rates may represent maximum data rates in some embodiments.
Non-limiting examples of high speed interfaces, for example which may serve as interface 308a, include twisted pair interfaces, low voltage differential signaling (LVDS) interfaces, and optical fiber interfaces. Such high speed interfaces may implement high speed protocols such as SerDES, SONET, 10 GB Ethernet, 40 GB Ethernet, 100 GB Ethernet, PCI Express, HDMI, Infiniband, Thunderbolt, and JESD-204B, among others. External devices to which such an interface may connect may include high throughput devices, such as high throughput FPGAs.
In some embodiments, a high speed interface of an ultrasound transducer probe may connect to an FPGA which may perform some type of processing, such as packetization, compression, or other processing, before sending such data to a digital signal processor (DSP), central processing unit (CPU), or GPU. In some embodiments, the suitability of an external device for connection to a high speed interface of an ultrasound transducer probe (e.g., interface 308a) may be quantified by considering minimum memory and processing capacity targets. For example, a suitable external device may include over approximately 2 GB of random access memory (RAM) and/or over a particular number of processing cores, for example greater than 300 processing cores, greater than 400 processing cores, greater than 500 processing cores, between 200 and 600 processing cores, any number within that range, or any other suitable number. As non-limiting examples, the NVIDIA GTX 680 and NVIDIA Tesla K20, available from NVIDIA of Santa Clara, Calif., may be implemented in some embodiments as suitable external devices to which to connect a high speed interface of an ultrasound transducer probe of the types described herein.
Non-limiting examples of lower speed interfaces, for example which may be used for interface 308b, include USB 3.0, USB 2.0, firewire, and Gigabit Ethernet. The lower speed interfaces may be capable of connection to an external device via only a single cable in some embodiments (e.g., a USB cable).
In those aspects of the present application in which an ultrasound transducer probe includes different types of physical interfaces for interfacing with external devices, more than two different types of interfaces may be provided and/or more than two instances of one or more types of interfaces may be provided with an ultrasound transducer probe. For example, referring to
As previously described, the higher speed interfaces may be configured to maximize the amount of ultrasound data provided by the ultrasound transducer probe to an external device. The number of higher speed interfaces may be selected accordingly in some embodiments. The number of higher speed interfaces may be selected based on the number of receive signal channels of the ultrasound transducer probe, which will be described further below in connection with an example of the architecture of the ultrasound transducer probe. For example, the more receive channels included with the ultrasound transducer probe, the greater the number of higher speed interfaces which may be included. In some embodiments, the number of higher speed interfaces provided may scale linearly and proportionally with the number of receive channels of the ultrasound transducer probe.
When multiple interfaces of a single type are included on a transducer probe of the types described herein, not all such interfaces need be used in all embodiments. The point may be illustrated by consideration of the ultrasound transducer probe 200 of
Although not explicitly shown, the interfaces of ultrasound transducer probes 210, 220, 230, 240, 250, and 260 may also generally conform to the configuration of the interfaces of ultrasound transducer probe 300, including both higher and lower speed interfaces. The ultrasound transducer probe 210 may include the same interfaces 208a and 208b of ultrasound transducer probe 200, located on the peripheral region(s) 212a and/or 212b in some embodiments. For example, in a first embodiment, the peripheral region 212a may include the interfaces of ultrasound transducer probe 200 of
Because the ultrasound transducer probes 220, 230, 240, 250, and 260 represent multiple instances of the ultrasound transducer probe 200 or 210, the number of interfaces included may simply scale with the number of instances of the ultrasound transducer probe 200 or 210 making up the ultrasound transducer probes 220, 230, 240, 250, and 260.
The physical interfaces described herein may be suitable for wired connections (e.g., a cable) or wireless connection in some embodiments. Thus, the aspects of the present application relating to an ultrasound transducer probe having two or more different types of interfaces are not limited to whether the interfaces are configured for wired or wireless connection unless otherwise stated.
When a wired connection is made to the interfaces of an ultrasound transducer probe of the types described herein, such connection may be made in any suitable manner. In some embodiments, the ultrasound transducer probe may be enclosed within a package or housing, and one or more ports may be provided for connecting a wire/cable to the ultrasound transducer probe. In some such embodiments, one port for each type of interface of the ultrasound transducer probe may be provided, though alternative configurations are possible. A non-limiting example is illustrated in
The device 400 of
As a non-limiting example, the port 404b may be suitable for connecting to a USB cable (e.g., wired connection 106 or 124 may be a USB cable). As previously described, interface 208b may, in some embodiments, be a suitable interface for connecting the ultrasound transducer probe to a consumer electronics device. In some such embodiments, the interface 208b may be compatible with a USB connection, since many consumer electronics devices are configured to connect to other devices via USB cables. Thus, the port 404b may be a USB port. However, it should be appreciated that alternatives are possible.
As a non-limiting example, the port 404a may be suitable for connecting to a direct-attach cable, such as a quad small form-factor pluggable (QSFP) cable (e.g., wired connection 106 or 124 may be a QSFP cable). As previously described, the ultrasound transducer probe 200 may include multiple interfaces 208a (or, stated another way, multiple instances of the interface 208a), yet in some embodiments only a single cable may be needed to connect the interfaces to an external device, and thus only a single port 404a may be provided. For example, use of a QSFP cable may allow for connection of a single cable to four of the interfaces 208a. In this manner, the number of interfaces of the ultrasound transducer probe to which any external device is connected may be determined by the cable used to connect the ultrasound transducer probe 400 to the external device, which may render transparent the process of selecting how many interfaces to connect to.
In some embodiments, a single cable may be used for each interface of the ultrasound transducer probe to which an external device is to be connected. In such instances, the ultrasound transducer probe 400 may include a port corresponding to each of the physical interfaces 208a and 208b.
It should be appreciated that in operation the ultrasound transducer probe 400 may be connected to an external device by a single cable at a time. That is, the user may select whether to utilize the interface 208a or the interface 208b, and thus connect a single cable to the appropriate port 404a or 404b.
In some embodiments, the package or housing of an ultrasound device may limit accessibility to one or more interfaces of the ultrasound transducer probe. The point may be illustrated by considering the ultrasound transducer probe 200 of
Although some embodiments have been described in which multiple types of interfaces are provided with an ultrasound transducer probe, not all embodiments are limited in this respect. In some embodiments, only a single type of interface may be provided on the probe. For example, in some embodiments, an ultrasound transducer probe like that of
Architecture
As previously described, various features of an ultrasound transducer probe may facilitate use of the transducer probe as a stand-alone ultrasound transducer probe (e.g., a stand-alone or self-contained 1D, 1.5D or 2D ultrasound transducer probe) or as a component of a larger ultrasound device formed by tiling and interconnection of multiple instances of the transducer probe. One such feature is the physical architecture of the transducer probe, including the geometry of the transducer probe and the positioning of ultrasonic transducers and integrated circuitry of the transducer probe.
Form Factor of Ultrasound Transducer Probes
The geometry of the ultrasound transducer probe may be selected to provide a desired aperture, which may facilitate tiling and interconnection of multiple instances of the transducer probe to form a larger ultrasound device having a desired aperture. In some embodiments, an ultrasound transducer probe may have a first side longer than a second side, where the first side is substantially perpendicular to the second side. The sides may represent sides of a device surface on which ultrasonic transducers and/or circuitry are formed. As an example, the ultrasound device 100 of
As has been described, in some embodiments an ultrasound transducer probe includes a substrate, such as a semiconductor or CMOS substrate (e.g., substrate 202 of transducer probe 200). In any of those embodiments in which the transducer probe has one side longer than another perpendicular side (e.g., when the transducer probe is a wide aspect ratio transducer probe), the dimensions may refer to the dimensions of the substrate.
Referring to
In some embodiments the use of an ultrasound transducer probe having one side longer than a perpendicular side (e.g., a wide aspect ratio transducer probe) may provide benefits in terms of the aperture of the transducer probe. For example, such a configuration may facilitate creation of a suitable 1D transducer probe aperture. Thus, in some embodiments, the dimensions of an ultrasound transducer probe (e.g., ultrasound transducer probes 200 and 210) may be selected to provide a desired aperture (e.g., a desired 1D aperture or 2D aperture). In some embodiments, a transducer probe having a width of between approximately 30 mm and approximately 40 mm and having a height between approximately 2 mm and approximately 8 mm may provide a suitable 1D aperture, allowing for suitable focusing of an ultrasound beam in the height dimension.
The ultrasonic transducers of an ultrasound transducer probe may assume a configuration suitable for providing a desired aperture. For example, referring to
One or more lensing components may be provided with the ultrasound transducer probe to control the focus of the ultrasound transducer probe. For example, an acoustic lens may be provided overlying the ultrasonic transducers to focus transmitted and/or received acoustic signals. The acoustic lens may assume any suitable configuration for providing desired lensing functionality and may be formed of any suitable material. For example, referring to
Any suitable number of ultrasonic transducers may be provided on an ultrasound transducer probe, as the number is not limiting of the various aspects described herein. In some embodiments, tens, hundreds, thousands, hundreds of thousands, or millions of ultrasonic transducers may be provided on an ultrasound transducer probe. As a non-limiting example, the plurality of ultrasonic transducers 204 of ultrasound transducer probe 200 may include an array of sixteen rows (parallel to the width W1) of ultrasound elements with each row of ultrasound elements having 128 ultrasound elements. The same may be true for the ultrasound transducer probe 210 of
In some embodiments, the ultrasound elements (e.g., element 504) may include one or more ultrasonic transducers (also referred to herein as “transducer cells”). Stated differently, the ultrasonic transducers may be grouped together to form ultrasound elements. The concept is illustrated in connection with cluster 506 of ultrasound elements 508a-508d, enlarged in
The ultrasonic transducers 510 may be CMUTs, CUTs, or other suitable ultrasonic transducers. The ultrasonic transducers 510 are illustrated as being circular (from a top view) but may have any suitable geometry. The ultrasonic transducers 510 within an element 504 may be electrically interconnected to operate as a single element rather than as individually controllable transducers. For example, the transducers may have one or more common electrodes to provide unified operation.
The transducer cell pitch L1 of the ultrasonic transducers may be approximately 52 microns or any other suitable value. The length L3 of an ultrasound element of the type illustrated in
While
Such configurability may be utilized to facilitate certain operating modes. Examples of ultrasound imaging modes which may be implemented by ultrasound transducer probes according to aspects of the present application are described further below. A particular ultrasound element configuration (e.g., one of the configurations shown in
The physical placement of the circuitry of an ultrasound transducer probe of the types described herein may also facilitate the use of the ultrasound transducer probe as a stand-alone ultrasound transducer probe or as a component of a larger transducer probe formed by tiling and interconnection of multiple instances of the transducer probe. As previously described, in some embodiments the ultrasound transducer probe may include a CMOS substrate and integrated circuitry. In some embodiments, at least some circuitry of the ultrasound transducer probe may be positioned beneath the ultrasonic transducers of the transducer probe. In some embodiments, some of the integrated circuitry may be positioned on the peripheral region (or “tab”) of the ultrasound transducer probe. For instance, circuitry which is shared among two or more of the ultrasonic transducers or ultrasound elements may be positioned on the peripheral region. Yet, circuitry specific to an ultrasound element or to a particular ultrasonic transducer may be positioned beneath that ultrasound element or ultrasonic transducer in some embodiments. A non-limiting example is shown in
Placement of Ultrasonic Transducers and Circuitry
As shown, the ultrasound transducer probe of
In some embodiments, the integrated circuitry 602 may be arranged into IC cells corresponding to the ultrasonic transducers or to ultrasound elements of the type described in connection with
As shown, the integrated circuitry 604 may be positioned on the peripheral region 206 (indicated as being to the left of the vertical dashed line). In some embodiments, the integrated circuitry 604 may include circuitry which is not specific to any particular transducer of the ultrasound transducer probe. For example, timing circuitry, I/O circuitry, power conversion circuitry, or other circuitry which may be shared among multiple transducers or elements, or shared among all of the transducers may be positioned on the peripheral region 206 in some embodiments. Other circuit components may additionally or alternatively be included on the peripheral region 206. Furthermore, in some embodiments, all integrated circuitry of the ultrasound transducer probe may be positioned beneath the ultrasonic transducers, which may minimize the chip area required for the ultrasound transducer probe.
Ultrasound Transducer Probe Circuitry
The architecture of the ultrasound transducer probe circuitry may include further features facilitating the use of the ultrasound transducer probe as a stand-alone probe or as a component of a larger ultrasound device formed by tiling and interconnection of multiple instances of the transducer probe. For example, the circuitry of the transducer probe may include digitization circuitry (e.g., analog-to-digital converters (ADCs)). Such digitization circuitry may digitize signals from the ultrasonic transducers such that the ultrasound transducer probe may communicate the ultrasound data to an external device in digital form (e.g., via a USB cable or other interface of the types described herein). Thus, aspects of the present application provide digital ultrasound transducer probes. Examples of suitable digital circuitry are described further below and may include, for example, analog-to-digital converters (ADCs), multiplexers, re-quantizers, averaging circuits, and communication interfaces, among others.
Another feature of the ultrasound transducer probe circuitry which may facilitate the use of the ultrasound transducer probe as a stand-alone probe or as a component of a larger ultrasound device formed by tiling and interconnection of multiple instances of the transducer probe is the programmable nature of the circuitry. The use of programmable circuitry may allow the ultrasound transducer probe to be programmed to work suitably in combination with other such ultrasound transducer probes (e.g., when two or more ultrasound transducer probes are tiled to form a larger ultrasound transducer probe). Also, the use of programmable circuitry may support various ultrasound imaging modes. In some embodiments, the programmable circuitry may include a programmable waveform generator. Non-limiting examples of such waveform generators as well as other circuitry of an ultrasound transducer probe are described further below.
The control circuitry of an ultrasound transducer probe of the types described herein (e.g., integrated circuitry 306 of ultrasound transducer probe 300) may include any suitable circuitry for controlling, at least in part, transmission and/or receiving functions of the plurality of ultrasonic transducers of the transducer probe (e.g., ultrasonic transducers 304).
The ultrasound transducer probe 700 includes one or more transducer arrangements (e.g., arrays) 702, a transmit (TX) control circuit 704, a receive (RX) circuit 706, a timing and control circuit 708, a signal conditioning/processing circuit 710, and/or a power management circuit 718 receiving ground (GND) and voltage reference (VIN) signals. Optionally, a HIFU controller (not shown) may be included if the ultrasound transducer probe is to be used to provide HIFU. In the embodiment shown, all of the illustrated elements are formed on a single semiconductor die (or substrate or chip) 712, though not all embodiments are limited in this respect. In addition, although the illustrated example shows both a TX control circuit 704 and an RX circuit 706, in alternative embodiments only a TX control circuit or only an RX control circuit may be employed. For example, such embodiments may be employed in a circumstance in which the ultrasound transducer probe is operated as a transmission-only device to transmit acoustic signals or a reception-only device used to receive acoustic signals that have been transmitted through or reflected by a subject being ultrasonically imaged, respectively.
The ultrasound transducer probe 700 further includes a serial output port 714 which may represent an implementation of an interface of the types previously described herein (e.g., interface 308a or 308b). While only a single output port 714 is illustrated, it should be appreciated that multiple output ports may be provided, consistent with the ultrasound transducer probe 700 having multiple interface types.
The ultrasound transducer probe 700 may also include a clock input port 716 to receive and provide a clock signal CLK to the timing and control circuit 708.
It should be further appreciated from the components of ultrasound transducer probe 700 that a complete ultrasound system-on-a-chip may be provided in accordance with some embodiments. Not all embodiments are limited to such a configuration, however.
In some embodiments, the control circuitry of an ultrasound transducer probe may be configured to reduce the amount of data to be sent from the transducer probe to an external device. Reducing the amount of data may facilitate use of the ultrasound transducer probe for high end applications, such as high end ultrasound imaging applications. According to some embodiments, the amount of data provided externally from the ultrasound transducer probe may be reduced by including fewer receive signal channels than the probe contains ultrasound elements, such that multiple ultrasound elements share a receive signal channel. Thus, the receive circuit 706 and signal conditioning/processing circuit 710 may be shared among multiple ultrasound elements. A non-limiting example is illustrated in
As shown, the circuitry configuration 800 includes a plurality of ultrasound elements 802, which may be of the types previously described herein or any other suitable type. For example, the ultrasound elements 802 may each be like an ultrasound element 508a, previously described. A respective transmit excitation module 804 may be provided for each of the ultrasound elements 802. However, multiple ultrasound elements 802 share a single receive module 806. For example, the illustrated ultrasound elements 802 may each be coupled to the receive module 806 by a respective switch 808. In this manner, the amount of receive circuitry implemented on the ultrasound transducer probe may be reduced and the amount of data provided by the ultrasound transducer probe to an external device may be more readily reduced to an amount which can be communicated serially.
In those embodiments in which multiple ultrasound elements 802 share a single receive module 806, the number of ultrasound elements 802 sharing the receive module 806 may be any suitable number to provide a desired reduction in receive circuitry compared to providing a respective receive module for each ultrasound element. Referring to
The switches 808 may be operated in any suitable manner to provide desired receive functionality. For example, all the switches 808 may be open, disconnecting the receive module 806 from the ultrasound elements 802, when the ultrasound elements 802 are transmitting ultrasound signals. When the ultrasound elements 802 are receiving ultrasound signals, the switches 808 may be sequentially closed to read signals out of the ultrasound elements 802 sequentially, as a non-limiting example.
The ultrasound transducer probe 900 includes a plurality of ultrasound elements 901 which, for purposes of illustration, are described as being arranged in columns. For example, the ultrasound elements 901 may be arranged in columns in the manner previously described in connection with ultrasound transducer probe 210 as shown in
Certain circuitry of the ultrasound transducer probe 900 is associated with respective columns of the ultrasound elements 901 and thus is described as being part of a column module, each of which is shown as being divided into two half-columns. Other circuitry is more generally associated with the plurality of ultrasound elements 901 rather than any particular column of ultrasound elements and thus may be considered separate from the column modules.
The ultrasound transducer probe 900 includes column modules 902a, 902b . . . 902n, where n is the total number of columns of ultrasound elements. As a non-limiting example, n may be 128, may be between 50 and 150, any value within that range, or any other suitable value. The column modules 902a . . . 902n may each include a subset of the ultrasound elements 901, one or more transmit circuitry modules 904 and one or more receive circuitry modules 906. In the non-limiting example shown, each column module 902a . . . 902n may include 16 ultrasound elements 901, two receive circuitry modules 906 coupled to respective groups of eight ultrasound elements 901 (i.e., one receive circuitry module per 8 ultrasound elements), and 16 transmit circuitry modules 904 coupled to respective ultrasound elements 901 (i.e., one transmit circuitry module 904 per ultrasound element 901). The receive circuitry modules 906 may be coupled to each ultrasound element 901 of a respective group of ultrasound elements 901 by a switch in the manner previously illustrated in
The ultrasound transducer probe may operate by loading transmit parameters defining a sequencing operation into the transmit circuitry modules of the column circuitry. In some embodiments, the sequencing information may be pushed to each ultrasound element of the ultrasound transducer probe by pushing the sequencing information to the waveform generator associated with the ultrasound elements. The transmit parameters may be loaded in a daisy-chain configuration, being passed from one transmit circuitry module to the next, as indicated by the arrows 962. In some embodiments, the transmit parameters are loaded into the transmit circuitry modules when the ultrasound transducer probe is operating in a receive mode.
Control of the sequencing of transmit and/or receive functions performed by the ultrasound transducer probe 900 may be achieved with the sequence processing unit (SPU) 912, which may be a microcontroller or other suitable hardware. For example, the SPU 912 may provide a desired sequence of transmission and/or reception events.
Various components of the ultrasound transducer probe 900 may operate in conjunction with the SPU 912. For instance, an excitation parameter loader 914 is included and loads suitable control parameters into the transmit circuitry modules 904 in response to a control signal 958 from the SPU 912. A SPU memory 916 is also included to store the sequencing parameters for the SPU 912, including transmit and receive parameters and parameters for controlling other components (such as data interface components) of the ultrasound transducer probe. A program management unit (PMU) 917 may handle program loading into the SPU 912, and may be a dedicated piece of hardware. The PMU 917 and SPU 912 may communicate data and address information with the SPU memory 916 via control lines 954 and 952, respectively, with the help of a multiplexer 960. The PMU 917 may also provide a reset signal 956 to the SPU 912.
The SPU 912 may run a stored program to configure and sequence the actions of the ultrasound transducer probe 900. Thus, the details of an imaging mode of operation may be encoded into a reconfigurable stored program loaded into the SPU 912. As described previously, the PMU 917 may control loading of the program into the SPU 912. The PMU 917 may be directly accessible from the external device (e.g., a host computer) over the external data links 930 and 932 connected to the interface circuits 926 and 928, respectively. When commanded by the host computer, the PMU 917 may hold the SPU 912 in reset and take direct control of the SPU memory 916. Program code from the host computer may then be written directly into the SPU memory 916. After the program has been transferred, the PMU 917 may return the SPU memory 916 to the SPU 912 and release the SPU 912 from reset. The new program may then begin executing per the program's reset vector.
The SPU 912 may be loaded with a suitable program at any suitable times. In some embodiments, the SPU 912 may be loaded with a program at power-on and reset of the ultrasound transducer probe 900. In some embodiments, the stored SPU program may also be replaced during operation of the ultrasound transducer probe 900 as the host computer or other external device changes imaging modes. Thus, the SPU 912 may exhibit semi-autonomous operation. That is, The SPU 912 may operate without a constant stream of configuration data from the host computer, which may eliminate performance bottlenecks caused by latency and congestion on the external data links.
Various benefits may be realized by operation of the SPU 912 in the manner described. For example, when multiple instances of the ultrasound transducer probe 900 are tiled and interconnected, each may run its own unique copy of the SPU program. The programs may or may not be identical depending on what the host computer is trying to achieve. In this manner, coordinated operation of the multiple instances of the repeatable ultrasound building block may be achieved. Cascaded or common clocks and sync pulses may be used to coordinate execution between multiple such ultrasound transducer probes, described further below in connection with
The operation of the SPU 912 as described may also provide flexibility to the ultrasound transducer probe 900. For example, the ultrasound transducer probe is not restricted to the imaging modes encoded on the chip during the design phase. Additional imaging modes can be achieved simply by changing the stored program for the SPU.
Moreover, verification of operation of the ultrasound transducer probe 900 may be relatively simple. That is, accuracy of operation may be verified by ensuring the SPU 912 can communicate with any external imaging hardware through the designated interfaces, without the need to verify the operation of many hardware state machines.
The timing of operation of the ultrasound transducer probe 900 may be controlled in any suitable manner. In the example shown, the ultrasound transducer probe 900 includes a clock and reset control circuit 910 for controlling the clocking of the circuitry (e.g., the transmit and receive circuitry modules). For example, the clock and reset control circuit 910 may receive an input clock 934 (e.g., from an external oscillator), and provide a global clock 936 and/or a global reset signal 938. An external clock 940 may also be provided as an output.
The ultrasound transducer probe 900 also includes a reference voltage/current circuitry module 918 to monitor and provide reference voltages/currents to the column circuitry. The reference voltage/current circuitry module 918 may take any suitable form.
The ultrasound transducer probe 900 also includes interface circuitry for communicating electrical signals between the ultrasound transducer probe and an external device (e.g., a tablet computer or other host computer). The interface circuitry includes a first interface circuit 926 and a second interface circuit 928, which may be any of the types previously described herein or any other suitable types of interface circuits. An external communication module 924 may facilitate communication between the ultrasound transducer probe 900 and any external device, and may be coupled to the interface circuits 926 and 928. The external communication module 924 may be hardware and may take any suitable form.
The external communication module 924 may also be used in providing data from the receive circuitry modules 906 to an external device. As shown by the arrows, each of the receive circuitry modules 906 may be configured to provide data to the external communication module 924. Different operating modes for doing so are possible. In one mode, each of the receive circuitry modules 906 may provide its data to the external communication module, i.e., data for each half-column may be separately provided to the external communication module 924. In another mode, data from the two half-columns forming a column may be provided to the external communication module 924 using the adders 942. In particular, the data from the receive circuitry modules 906 of the two half-columns of a column may be combined by the adder 942 of that column and then provided to the external communication module 924. Thus, the adders 942 may optionally be used, and in some embodiments may be bypassed as shown by the arrows.
A time gain control (TGC) circuit 922 and TGC RAM 920 may also be included in the ultrasound transducer probe 900 to provide TGC functionality. The TGC RAM 920 may store data of a TGC curve to be implemented by the TGC circuit 922. The TGC circuit 922 may be coupled to the receive circuitry modules 906 to adjust them suitably to provide TGC functionality. For instance, a global gain setting 944 may be provided to all the columns. The slave line 946 may be the slave of the SPU 912. The SPU may send the time gain control to the TGC circuit 922 which may then send out the TGC information via the global gain setting 944.
The TGC circuit 922 and the TGC RAM 920 may exchange data 946 and addresses 948 of the appropriate ultrasound elements 901 may be provided by the TGC circuit 922 to the TGC RAM 920. The TGC RAM 920 may also receive data from the external communication module 924 via line 950.
The transmit circuitry modules and receive circuitry modules of
The waveform generator 1008 may be a programmable waveform generator. In some embodiments, the waveform generator 1008 may be configured to produce various kinds of waveforms, including continuous waves, impulses, coded excitations, and chirp waveforms. A non-limiting example of a suitable waveform generator is described further below in connection with
The pulser 1010 may be any suitable type of pulser, non-limiting examples of which are described further below, for example in connection with
In the example of
As illustrated in
When the ultrasound transducer probe operates in a transmit mode, the switches 1014 may all be opened, disconnecting the ultrasound elements 1002 from the receive circuitry module. When the ultrasound elements 1002 operate in a receive mode, the switches 1014 may be closed in any suitable sequence to connect the ultrasound elements 1002 to the receive circuitry module and thus read a signal out from one or more of the ultrasound elements 1002. It should be appreciated that switches 1014 provide a degree of configurability in determining whether the outputs from the ultrasound elements 1002 are provided by two ultrasound elements at a time, eight ultrasound elements at a time, or some number in between.
The switches 1014 couple the ultrasound elements 1002 to a multiplexing or summing circuit 1016. The multiplexing or summing circuit 1016 may couple an ultrasound element 1002 to a variable gain amplifier (VGA) 1018. In some embodiments, the VGA 1018 may include a filter, such as a second order low-pass filter. The output of the VGA 1018 may be coupled to an analog-to-digital converter (ADC) 1020 to digitize the output signals of the ultrasound elements 1002.
The TIAs 1004 and VGA 1018 may be configured in combination to provide target noise characteristics in view of the configurable nature of the illustrated circuit. That is, use of the VGA 1018 in combination with the TIAs 1004 may account for the fact that the switches 1014 may be operated to alter whether a single ultrasound element 1002 is providing its output at any given time or whether all eight ultrasound elements 1002 are providing their outputs simultaneously. The illustrated configuration of TIAs 1004 and VGA 1018 may also reduce the amount of chip area compared to if a single TIA or VGA was provided for each ultrasound element. In some embodiments, the TIAs 1004 (or, more generally, the LNAs) and/or VGA 1018 may be powered down when not used (e.g., during transmit modes). By powering down the TIAs 1004 and/or VGAs 1018 during idle and/or non-transmit modes, overall power consumption of the device may be reduced.
The VGA 1018 may function to adjust the gain of the signals received from the ultrasound elements 1002 to provide a substantially constant power level over the duration of the receive time window. For a given excitation event, the signals received by the ultrasound elements 1002 may generally decrease in magnitude as time progresses. If the magnitude becomes too low, the signal may fall below the threshold of the ADC 1020. By providing a time varying gain, the VGA 1018 may prevent such behavior, thus allowing for ultrasound analysis of a wider region within a subject. The time varying gain profile implemented by the VGA 1018 may be provided by, for example, the TGC circuit 922 of
Additional circuitry of the receive circuitry module 1006 may include a low pass filter (LPF) 1022, a multiplexer 1024, a maximum value detection circuit 1026, an output buffer 1028 and a re-quantizer 1030. Signals received by the receive circuitry module from one or more of the ultrasound elements 1002 may be digitized by the ADC 1020, then filtered by the LPF 1022, and re-quantized by the re-quantizer 1030. The LPF 1022 may be any suitable low pass filter for filtering a desired frequency range. In some embodiments, the LPF 1022 may be a decimating filter, and in some embodiments a ½ band decimating filter. Other types of low pass filters may alternatively be used.
The re-quantizer 1030 may reduce the amount of data to be sent externally from the ultrasound transducer probe. Any suitable re-quantizer for performing this function may be used. The re-quantizer may operate to discard data bits not of interest or not needed to produce ultrasound data of a desired quality. As a non-limiting example of the operation, the re-quantizer 1030 may determine a maximum data value from a set of received data. A count of the number of shifts (e.g., to the left) within the data set to get to a position at which the two most significant bits differ from those of the maximum data value may then be made. This determined count may be provided to an end user of the ultrasound transducer probe. Then, as the ultrasound data is sent externally from the ultrasound transducer probe, all the data values may be shifted (e.g., to the left) by the determined count and the upper N rounded bits may be sent. N represents an integer and may be set at a desired level (e.g., the upper five bits, upper seven bits, upper eight bits, or other suitable value) to achieve sufficient data reduction. It should be appreciated that this process of re-quantization is a lossy process, but that by suitable selection of N the ultrasound data sent externally from the ultrasound transducer probe may be of sufficiently high quality to enable desired applications (e.g., imaging applications) of the ultrasound transducer probe while providing data reduction.
The output 1032 of the receive circuitry module may represent the data from the ultrasound elements 1002 and may be provided, for example, to the external communication module 924 of
The circuitry of
The receive circuitry positioned downstream of the ADC 1020 may also be configured to perform cancellation of signals. For example, two pulse or three pulse cancellation techniques may be implemented. Other modes implementing techniques such as addition or averaging of signals, subtraction of signals, or bit shifting techniques may be used to facilitate cancellation of signals. Such cancellation may, for example, facilitate measurement of non-linear responses and scatterer velocities.
The waveform generator 1008 further comprises comparison circuits 1112 and 1114. The comparison circuit 1112 compares the phase of the generated waveform to ±VT. Comparison circuit 1114 compares the inverse phase of the generated waveform (θ+180°) to ±VT. The outputs of comparison circuits 1112 and 1114 are provided to multiplexers 1120 and 1122, which provide output signals V0 and V1 to the pulser 1010. The output signals V0 and V1 may be binary signals. VT represents the value the sine wave, as represented by the phase, needs to achieve before triggering the pulser 1010 to transition. VT may be tunable, thus representing an additional degree of freedom.
The waveform generator 1008 includes multiple components providing the ability to generate coded excitations (e.g., binary coded excitations). As shown, a multiplexer 1128, multiplexer 1132 and AND gate 1130 all receive an indication of whether a coded excitation is to be generated. The multiplexers 1128 and 1132 receive the indication as a control signal and each have one input configured to receive a zero. The AND gate 1130 receives the indication as an input.
A flip bit circuit is also provided, including a flip bit register 1124 configured to store a flip bit that flips the output signals V0 and V1, which is provided to an input of a XOR gate 1126 that also receives the output of the multiplexer 1128. Thus, the flip bit, which may be a static bit, may provide for inversion of the waveform generator waveform. AND gate 1136 is also provided and has an inverting input as shown. The output of summation circuit 1110 is provided to one input of the AND gate 1136 and is also delayed by delay element 1134 and then provided to the inverting input of the AND gate 1136, the output of which is provided as an input to the AND gate 1130.
The illustrated configuration allows for the turning on and off of various components depending on whether coded excitation is to be performed. In operation, the registers 1102, 1104, and 1106 are loaded. The waveform generator 1008 receives a clock signal 1116, for example from a clock generation circuit (not shown in
If coded excitation is to be performed, values from register 1102 may be fed through the multiplexer 1128 to the XOR gate 1126. Thus, the register 1102 may serve a dual purpose in providing values to set a chirp rate when a chirp is generated or to provide values to generate a binary coded excitation. When a coded excitation is to be generated, the output of multiplexer 1132 is the static value zero. The illustrated indication of the 2nd most significant bit (MSB) provided to the input of AND gate 1136 indicates the frequency of coding to be performed. Any number of significant bits may be provided from the output of summation circuit 1110 to provide a desired frequency of coding, as the 2nd MSB is an example.
Whether or not coded excitation is performed, the comparison circuits 1112 and 1114 may perform the described comparisons to generate the values of V0 and V1 which may then be provided to the pulser 1010.
Thus, it should be appreciated that the waveform generator 1008 is a programmable waveform generator which may be programmed to produce different kinds of waveforms by setting the registers 1102, 1104, and 1106 and controlling whether coded excitation is to be provided or not. In this manner, flexibility and versatility of the ultrasound transducer probe may be provided. High end imaging modalities may be implemented, taking advantage of the ability to generate continuous wave excitations, impulse excitations, coded excitations, and chirp excitations. Moreover, different kinds of waveforms may be generated for different ultrasound elements of an ultrasound transducer probe, or at different times of operation. In some embodiments, the same kind of waveform may be generated by two different waveform generators of the ultrasound transducer probe, but with different parameterizations, for example different amplitudes and/or delays (or any other characteristic of a waveform).
The registers of waveform generator 1008 may have any suitable sizes, as the exact sizes are not limiting of the various aspects of the present application. In some embodiments, the register sizes may be between approximately eight and approximately 32 bits, although other sizes may alternatively be implemented.
In some embodiments, Hadamard coding may be implemented in connection with waveform generation. Such coding may be used, for example, to facilitate apodization. The ultrasound transducer probe may include circuitry to implement the Hadamard coding.
The pulser 1010 may provide any suitable output voltages for a particular application. In some embodiments, the pulser may output voltages between approximately 5 V and approximately 20 V (e.g., 7.5 V), between approximately 20 V and approximately 120 V, any range or value within such ranges, or any other voltage.
The ultrasound element 1002 includes a first electrode 1302 facing a target subject (e.g., a medical patient). The first electrode 1302 may be configured to receive a voltage Vbias3. The ultrasound element 1002 further includes a second electrode 1304 that is distally positioned from the target subject. The second electrode 1304 may be coupled to the output of the pulser 1010 by the switch S1. The second electrode 1304 may also be coupled to the input of the amplifier 1305 by a switch S2. The input of the amplifier 1305 may also be biased by a bias signal Vbias2. The amplifier 1305 may receive reference voltages Vdd and Vss2.
The voltages illustrated in
According to some embodiments, Vbias1 and Vbias2 may be electrically grounded (e.g., set to 0 V). Vbias3 may bias the first electrode 1302, for example at a value between −30 V and −90 V (e.g., −75 V). Vcc and Vss1 may be set to approximately 18 V and −18 V, respectively, and Vdd and Vss2 may be set to approximately 5 V and −5 V, respectively. When Vbias3 is not grounded, the electrode 1402 may be covered with an insulating material to reduce the risk of shock. Voltages other than those listed may be implemented.
The generation of clock signals within an ultrasound transducer probe of the types described herein may be performed in a manner which facilitates tiling and coordinated operation of multiple instances of the ultrasound transducer probe. When ultrasound transducer probes are tiled and interconnected for coordinated operation, one of the ultrasound transducer probes may serve as a controller or master and the other probe(s) may serve as controlled probes. For example, considering
In the illustrated embodiment, the clock generation circuit 1403 may divide the clock signal 1404 by a desired amount and distribute the divided signal(s). For example, as shown, the clock generation circuit 1403 may include a SerDES module 1406, the output of which may be provided to a first division circuit 1408. The output of division circuit 1408 may represent a word clock in some embodiments, such as an internal USB word clock to be used internally on the ultrasound transducer probe. The clock signal 1404 may also be provided to a second division circuit 1410, the output of which may be provided to a multiplexer 1412. The multiplexer 1412 also receives an external digital clock signal 1424, which may represent a digital clock signal provided by another ultrasound transducer probe, for example when the illustrated probe is operating as a controlled probe.
The output of multiplexer 1412 may be used to produce both an internal digital clock signal 1420 to be used within the ultrasound probe and an external digital clock signal 1426 representing the output of buffer 1414. The external digital clock signal 1426 may be provided to another controlled ultrasound transducer probe as its external digital clock signal 1424.
The output of multiplexer 1412 may also be provided to a third division circuit 1427, the output of which may be provided to a multiplexer 1416. The multiplexer 1416 also receives an external ADC clock signal 1428 which may be provided by another ultrasound transducer probe when the illustrated ultrasound transducer probe is part of a tiled set of ultrasound transducer probes and is operated as a controlled probe within the set.
The output of multiplexer 1416 may serve as an internal ADC clock 1422 for clocking ADCs of the ultrasound transducer probe. The output of the multiplexer 1416 may also be sent to a buffer 1418 to produce an external ADC clock signal 1430 to be sent to other controlled ultrasound transducer probes.
Thus, it should be appreciated that the configuration of
Configurability of ultrasound transducer probes according to aspects of the present application may also be provided through configuration of the circuitry for offloading data from the ultrasound transducer probe to an external device.
The mesh 1500 includes receiver channels 1502 and external links 1504a-1504d. The illustrated embodiment includes 256 receiver channels, which may be utilized with an ultrasound transducer probe including 16×128 ultrasound elements with the columns of ultrasound elements being configured such that there are two receiver channels per column, for example as described in connection with
The mesh 1500 is configurable to shift data horizontally and/or diagonally to send the data external to the ultrasound transducer probe via one or more of the external links 1504a-1504d. As shown, the receiver channels 1502 are connected to nodes 1512 by signal paths 1508, which may include any number of signal lines (e.g., four as a non-limiting example). Data can be shifted horizontally from a node 1512 to an external link 1504a-1504d by signal paths 1506 and/or shifted diagonally to another node 1512 by signal paths 1510. The signal paths 1506 and 1510 may include any suitable number of lines. In some embodiments, the signal paths 1506 include four lines and the signal paths 1510 include two lines. Further detail is illustrated in
Two receiver channels 1502 are shown in
The signal paths 1510 interconnecting the nodes 1512 to allow diagonal data shifting may include any suitable number of lines. In the embodiment illustrated, two lines 1612a and 1612b make up the signal paths 1510 but alternatives are possible.
The nodes 1512, which may be shift registers in some embodiments, may be controllable to offer flexible operation depending on a desired operating mode. An example is shown in
For example, if all four external links 1504a-1504d are to be used (e.g., when the amount of data sent externally and frame rate are to be maximized in some embodiments), diagonal shifting and the associated data aggregation may be omitted. The data may be provided by the receiver channels to the respective nodes 1512 and shifted horizontally along lines 1506 to the respective external links 1504a-1504d.
By contrast, if only a single external link 1504a is to be utilized, whether it be a higher speed link or a lower speed link, data from the receiver channels coupled to nodes 1512 not on the horizontal signal path 1506 connected to external link 1504a may be shifted by the nodes 1512 diagonally to the horizontal signal path 1506 connected to external link 1504a. The data may then be shifted horizontally to the external link 1504a.
Two non-limiting examples of modes of operation of the mesh 1500 are shown in
At stage 1810 a determination is made whether the data has been offloaded from the ultrasound transducer probe. If not, the method returns to stage 1808 for further horizontal shifting. If yes, the method moves to stage 1812 at which a determination is made whether there is a next frame to be processed. If yes, the method returns to stage 1802. If not, the method is completed.
The method 1850 of
Thus, the circuitry configuration for offloading data from an ultrasound transducer probe may also be configurable. The described configurability may facilitate the use of the ultrasound transducer probe in a variety of applications with different requirements such as data frame rates, amount of data, and speed of operation.
Thus, it should be appreciated from the foregoing discussion that several aspects of the architecture of an ultrasound transducer probe according to embodiments of the present application, including probe geometry and circuitry positioning and programmability, may facilitate use of an ultrasound transducer probe as either a standalone ultrasound transducer probe or as a repeatable unit to tile and interconnect with other such ultrasound transducer probes in a larger ultrasound device. Further features of the architecture may facilitate operation of the ultrasound transducer probe(s) for particular applications, as now described.
High Voltage Circuitry
Aspects of the present application provide for integration of ultrasonic transducers with circuitry on a single substrate, such as a CMOS substrate or chip. The ultrasonic transducers may be used for ultrasound imaging applications, HIFU, or both. In some embodiments, the ultrasonic transducers may operate at voltages higher than those conventionally used for CMOS integrated circuitry, e.g., higher than voltages typically supported by deep and ultra-deep submicron CMOS circuitry. For example, such ultrasonic transducers may operate at voltages between 20 V and 120 V, between 30 V and 80 V, between 40 V and 60 V, at any voltage within those ranges, or at any other suitable voltages, depending on the application. HIFU applications typically utilize higher voltages than ultrasound imaging applications. In some embodiments, submicron nodes may refer to nodes that are smaller than approximately 1 micron. In some embodiments, deep submicron nodes may refer to nodes that are smaller than approximately 0.3 microns. In some embodiments, ultra-deep submicron nodes may refer to nodes that are smaller than approximately 0.1 micron.
Thus, in those embodiments in which ultrasonic transducers are integrated with circuitry on a single substrate it may be desirable for such circuitry to be configured to sustain or withstand voltages in the ranges listed above, for example by supporting those higher-than-typical voltages at deep submicron nodes of the integrated circuitry. The circuitry may be configured in some embodiments to account for typical limits on the operating voltage of NMOS and PMOS devices in CMOS circuits arising due to: (1) gate oxide breakdown, and (2) source and drain (diffusion) breakdown.
To increase the diffusion breakdown limit to enable operation at higher voltages, suitable doping of the source and drain regions of any field effect transistor (FET) may be implemented. For example, lowering doping levels in the source and drain regions may increase the diffusion breakdown voltage. In some embodiments doping levels below 1017 dopants/cm3 may be implemented.
With respect to gate oxide breakdown, which can arise as either gate-to-drain breakdown or gate-to-source breakdown, the maximum electric field applied across those points should be reduced. The standard gate-to-drain interface is a Lightly Doped Drain (LDD). The LDD may, for example, be doped to reduce the electric field but may be minimized in size to keep device length large enough to maintain gate control.
Aspects of the present application provide CMOS circuit designs suitable for use in ultrasound transducer probes of the types described herein and which exhibit breakdown voltages greater than those of conventional CMOS circuits. According to an aspect of the present application, mask logic operations and device layout are selected to provide suitable CMOS circuits for sustaining high voltages at deep submicron nodes.
CMOS circuitry may, for example, be turned into high-voltage CMOS circuitry by changing the diffusion scheme. For example, a mask-aligned source and drain using N-type well and P-type well regions may be employed. For NMOS implementations, the diffusion may be changed to an N-type well source/drain configuration with P-type substrate. For PMOS implementations, the diffusion may be changed to a P-type well source/drain configuration with N-type well and deep N-type well features. The sources and drains may be defined by Shallow Trench Isolation (STI). Alternatively, to sustain even larger voltages, the source and drain regions may be defined by gap space and thermal diffusion.
Examples of CMOS circuit layouts and associated structures that may be used to implement high-voltage CMOS circuits according to the various embodiments set forth herein are shown in
The NMOS transistor 1906 includes N+ source and drain regions 1908 and 1910, respectively. A source contact 1912 contacts the source region 1908 and a drain contact 1914 contacts the drain region 1910. An N+ gate 1916 is also included. The source region 1908 is formed in a P-type well (designated “PW”) 1918 which has a P+ contact region 1920 serving as a body contact for the transistor. The drain region 1910 is formed in an N-type well (designated “NW”) 1922. STI region 1924 is also included in the N-type well 1922.
Various features of the illustrated transistor 1906 may contribute to the ability to sustain high voltages. The configuration of the N-type well 1922 and the P-type substrate 1902 may contribute to the transistor 1906 having a large junction breakdown voltage. The N-type well 1922 and the P-type well 1918 may be lightly doped, and thus the region under the gate 1916 may be a LDD, thereby reducing the electric field between the gate 1916 and the source region 1908 and drain region 1910.
The PMOS transistor 1926 may also be configured to sustain high voltages. As shown, the PMOS transistor 1926 includes P+ source and drain regions 1928 and 1930, respectively. A source contact 1932 contacts the source region 1928 and a drain contact 1934 contacts the drain region 1930. A P+ doped gate 1936 is also included.
The source region 1928 is formed in an N-type well 1938 which includes an N+ contact region 1940 serving as a body contact for the transistor. The drain region 1930 is formed in a P-type well 1942, in which is also formed STI region 1944. An N-type well 1946 with a N+ contact region 1948 serving as a body contact for the transistor, as well as a deep N-type well (designated “DNW”) 1950, are also included as shown. The deep N-type well 1950 provides isolation from the substrate 1902. A deep well may have a depth between approximately 1 micron and 8 microns.
The configuration of P-type well 1942 and N-type well 1938 contribute to the transistor 1926 being able to support high voltages without experiencing junction breakdown. The N-type well 1938 and the P-type well 1942 may be lightly doped, and thus the region under the gate 1936 may be a LDD, thereby reducing the electric field between the gate 1936 and the source region 1928 and drain region 1930.
The spacing indicated by reference number 2010 represents an example of a mask defining the N+ doping implant region for the transistor 2002. It should be appreciated that only part of the gate 2008 is doped N+.
The PMOS transistor 2012 differs from PMOS transistor 1926 in that the N-type well 2014 and P-type well 2016 do not touch each other as do the N-type well 1938 and P-type well 1942. Thus, a portion 2020 of the P-type substrate is disposed between the N-type well 2014 and the P-type well 2016. The N-type well 2014 may be thermally diffused. Likewise, the P-type well 2016 may be thermally diffused.
The spacing indicated by reference 2022 represents an example of a mask defining the P+ doping implant region of the transistor 2012. It should be appreciated that only part of the gate 2018 is doped P+.
The PMOS transistor 2110 includes an N-type well 2114 with a N+ contact region 2112 adjacent a P-type well 2116 in which is formed the source region 1928 and STI region 2118. The N+ contact region 2112 serves as a body contact for the transistor. An N-type well 2020 separates P-type well 2116 from P-type well 1942. The P-type well 2116 represents a well for the source region 1928 and also a gate extension. P-type well 1942 operates as a well for the drain region 1930 and also as a gate extension.
The PMOS transistor 2110 also includes an N-type well 2120 and N+ contact region 2122 serving as a body contact for the transistor.
The pattern illustrated by reference 2216 represents an example of a mask pattern for the N+ implant region. As shown, only part of the gate 2212 is doped N+.
A body contact for the NMOS transistor 2202 is not explicitly shown but may be included and may be formed, for example, by a P-type well with a P+ diffusion region.
The PMOS transistor 2218 includes a deep N-type well 2220 formed in the P-type substrate 1902. N-type wells 2222, 2250 and 2238 may be formed in the deep N-type well 2220. An N+ contact region 2224 serving as a body contact for the transistor may be formed in the N-type well 2222. Similarly, an N+ contact region 2236 serving as a body contact for the transistor may be formed in the N-type well 2238. N-type well 2250 represents an optional well which may increase the threshold voltage at which the transistor 2218 breaks down.
The transistor 2218 also includes P-type wells 2228 and 2234. A source region 2226 may be formed in the P-type well 2228 and a drain region 2232 may be formed in the P-type well 2234. A source contact 2230 contacts the source region 2226 and a drain contact 2240 contacts the drain region 2232. The transistor 2218 also includes P-type wells 2246, 2248, 2252, and 2254.
The pattern represented by reference 2244 is an example of a mask pattern for the P+ implant process for forming transistor 2218. As shown, only part of the gate 2242 is doped P+.
The ultrasound transducer probes described herein may implement various types of circuit components, at least some of which may be constructed using the high voltage designs described in connection with
The transistors 2302 and 2306 are connected in series between a high voltage VH and a reference potential, such as GND. Likewise, transistors 2304 and 2308 are connected in series between the voltage VH and the reference potential. Transistors 2302 and 2304 are controlled by respective enable signals Txp and Txn.
The output Vout of the pulser may be provided to an electrode of an ultrasound element, for example ultrasound element 1002. A second electrode of the ultrasound element 1002 may be connected to a reference potential, such as electrical ground. The ultrasound element 1002 may be connected to a receive circuitry module 2312 of the types previously described herein via a transistor switch 2310. The transistor switch 2310 may be a high voltage transistor switch and may be controlled by an enable signal rx_en to isolate the receive module 2312 from the high voltage.
The pulser 2300 may be disabled by setting Txp=0, Txn=1. Then, the value of Txn may be set to Txn=0. The PMOS transistors 2306 and 2308 will hold state as long as the Vout node stays within the low voltage rails of the circuit.
To produce a pulser which can sustain four times the voltage VH, i.e., to sustain 4VH, the pulser 2410 shown in
The first electrode of the ultrasound element 1002 in
As shown, the ADC 2600 may include a plurality of sample & hold circuits 2602a, 2602b, 2602c . . . corresponding to different receive channels of an ultrasound transducer probe. The sample and hold circuits may receive a plurality of switching signals, illustrated collectively as S(*) via a switch signal input bus. The switching signals may control the sample and hold circuits to generate multiple (in this case five) samples per receive channel. The five samples per receive channel may be output from the sample and hold circuits to a comparator block 2604, which may also receive a ramp signal from a ramp circuit 2606. The ramp circuit 2606 is enabled by a signal ramp_en.
The comparator block 2604 compares the sampled values from the sample and hold circuits to the ramp signal and generates five corresponding output values provided in parallel per receive channel. The outputs of the comparator block 2604 are provided to latches 2608, which are latched by a counter 2610. The counter 2610 is enabled by a signal count_en. The latches 2608 output digital signals corresponding to the respective channels, i.e., dout0 for channel 0, dout1 for channel 1, dout22 for channel 2, etc. The digital signals represent serial digital outputs.
Switches 2704 may also be provided and are closed in any specified sequence to provide the values from the capacitors 2706 to an input of the comparators 2708. The comparators 2708 also receive the ramp signal of
As shown, the ADC 2802 may be configured to receive data from a plurality of channels (i.e., receive channels of an ultrasound transducer probe) including channel 0 and channel 1. A capacitor C0 may be coupled between a switch SW0, controlled by signal S5, and ground. Switch SW1, controlled by signal S0, may be operable to connect the ADC 2802 suitably to receive data from channel 0.
Channel 1 may be coupled to the ADC 2802 via switches SW2 and SW3, controlled by signals S5 and S1, respectively. A capacitor C1 may be coupled between the switch SW2 and a reference voltage, such as ground. A switch SW4, controlled by signal S3, may also be provided to connect the input of the ADC 2802 directly to the reference voltage, e.g., ground.
The high voltage CMOS circuitry described herein may be configured to drive voltages higher than those conventionally attainable with CMOS circuitry, and to provide high voltages at deep submicron nodes. In some embodiments, voltages up to approximately 10 V may be supported or driven, up to approximately 20 V may be supported or driven, up to approximately 30 V may be supported or driven, up to approximately 40 V may be supported or driven, up to approximately 50 V may be supported or driven, up to approximately 60 V may be supported or driven, voltages between 20 V and 120 V may be supported or driven, between 30 V and 80 V, between 40 V and 60 V, or any other suitable voltage within those ranges, or other suitable voltages, as non-limiting examples.
As described previously, embodiments of the present application provide an ultrasound transducer probe having one or more pulser circuits. When operating an ultrasound transducer probe at high voltages, such as those described in connection with
As shown, the circuit 2900 includes the ultrasound element 1002, the waveform generator 1008 and two pulsers 2902a and 2902b. Pulser 2902a is coupled to a first electrode of the ultrasound element 1002 and pulser 2902b is coupled to a second electrode of the ultrasound element 1002. An inverting amplifier 2906 is coupled to the input of the pulser 2902b to provide an inverted version of the waveform from waveform generator 1008. The circuit 2900 also includes a TIA 2904 and impedances Z1 and Z2. A T/R switch 2908 couples the TIA 2904 to the ultrasound element 1002.
By utilizing the pulser configuration of
The operation of the pulsers 2902a and 2902b can be further understood by reference to
Operating Modes
According to some aspects of the present application, the ultrasound transducer probes described herein may be used for ultrasound imaging, and when so used may be configured to operate in various imaging modes. Some embodiments provide for 2D and 3D imaging. When 2D ultrasound imaging is performed, alternative manners may be utilized. According to one manner of 2D operation, the ultrasound transducer probe may collect a time domain signal echo across one dimension of the arrangement of ultrasonic transducers. An alternative method may involve collecting ultrasound intensity data across two dimensions of the arrangement of ultrasonic transducers, but not measuring a time dimension. In some embodiments, a spectral domain signal may be used. In some embodiments, tomographic imaging may be utilized. The mode may be selected by a user in some embodiments. Non-limiting examples of imaging modes which may be utilized are now described.
One example of an imaging mode which may be exhibited is B-mode imaging. Plane wave imaging, virtual source imaging, all-pairs imaging, and focused beam imaging are all examples of B-mode imaging which may be implemented according to various embodiments.
Another imaging mode which may be used is M-mode imaging. This includes single line and multi-line M-mode imaging according to some embodiments.
Doppler imaging may also be performed with the ultrasound transducer probes according to various embodiments. Pulsed and vector flow Doppler imaging are examples of Doppler modes which may be implemented.
Shear wave imaging is another example of an imaging mode which may be implemented.
Harmonic imaging is another example of an imaging mode which may be implemented. Pulse inversion, 3-pulse inversion, and coded excitation operating schemes are enhancements to harmonic imaging which may also be implemented.
Verberation flow imaging (V-flow) may also be used in some embodiments.
The ability to exhibit such varied imaging modes may be due at least in part to the configurability of the ultrasound transducer probes. The transmit operation of an ultrasound transducer probe of the types described herein may be flexible. For example, the transmit operation may be controlled by parameters which are selectable, such as the parameters of a programmable waveform generator of the types described herein. For instance, the delay, amplitude, length, initial phase, initial frequency, and/or ramp rate of a desired excitation may be programmed into a waveform generator. In some embodiments, the parameterization may be substantially or fully arbitrary. Control over the start and stop of transmit operations may be provided in any suitable manner, such as with an enable signal. The transmit voltages may be adjustable.
The receive operation of ultrasound transducer probes of the types described herein may also be flexible, exhibiting significant configurability. For example, as described in connection with
The use of external links for communicating between an ultrasound transducer probe and an external device may be configurable according to aspects of the present application and may be selected based on an intended imaging mode. For example, the maximum number of available links may be utilized in embodiments in which it is desirable to maximize data output from the ultrasound transducer probe, and may allow for large quantities of data to be offloaded from the ultrasound transducer probe without averaging or other data reduction processing. Alternatively, fewer than the maximum number of links available may be utilized in embodiments in which maximum data is not needed. For example, half the links or only a single link may be utilized. In such embodiments, averaging of data may be implemented to facilitate offloading of a sufficient amount of data to support desired end user applications, such as ultrasound imaging.
The data format processed by the ultrasound transducer probe may also be configurable. For example, full waveforms may be processed in some embodiments. Alternatively, peak values may be processed, which may allow for a reduction in the data processing requirements of the ultrasound transducer probe.
Various additional parameters of the ultrasound transducer probe operation may be configurable. Such parameters include the receive window, channel subselection, the TGC configuration, data reduction parameters such as averaging or data dropping parameters, pulse repetition intervals, event sequencing intervals, quantizer configurations, and filter taps, among others.
Thus, it should be appreciated that the architecture of the ultrasound transducer probe in terms of the ultrasound transducers and control circuitry may facilitate use of the ultrasound transducer probe in a variety of modes of operation for a variety of applications. Accordingly, ultrasound transducer probes according to one or more aspects of the present application may represent sophisticated and versatile ultrasound devices configurable to create an ultrasound transducer probe geometry of choice.
Moreover, as has been described previously, for example in connection with
Transducer
The ultrasonic transducers of ultrasound transducer probes of the types described herein may be any suitable ultrasonic transducers, and in some embodiments may have features which facilitate creation of stand-alone ultrasound transducer probes exhibiting a high degree of integration. In some embodiments, the ultrasonic transducers may be compatible with a CMOS substrate, thus allowing them to be monolithically formed on a CMOS substrate with CMOS ICs. In this manner, an integrated device (e.g., an ultrasound system-on-a-chip) may be formed.
In some embodiments, the ultrasonic transducers may be CMOS ultrasonic transducers (CUTs). A CUT may, for example, include a cavity formed in a CMOS wafer, with a membrane (or diaphragm) overlying the cavity, and in some embodiments sealing the cavity. Electrodes may be provided to create a transducer cell from the covered cavity structure. The CMOS wafer may include integrated circuitry to which the transducer cell may be connected. The transducer cell and CMOS wafer may be monolithically integrated, thus forming an integrated ultrasonic transducer cell and IC on a single substrate (the CMOS wafer).
CUTs are not the only type of ultrasonic transducer which may allow for integration of the transducer with an IC. In some embodiments, the ultrasonic transducers may be capacitive micromachined ultrasonic transducers (CMUTs).
Not all embodiments are limited to employing CUTs or CMUTs in an ultrasound transducer probe of the types described herein. Some aspects of the present application apply to ultrasound transducer probes irrespective of the type of ultrasonic transducer implemented.
According to an aspect of the present application, ultrasonic transducers are formed above a thick top metal layer of a CMOS substrate. Ultrasound transducer probes according to aspects of the present application may include an arrangement of ultrasonic transducers on a CMOS substrate. The arrangement of ultrasonic transducers may span a distance which is relatively long in terms of signal transmission properties, which may run a risk of exhibiting relatively high impedances, and thus performance degradation. The problem may be enhanced if the ultrasound transducer probe comprises a CMOS substrate which is wider than it is tall (e.g., a wide aspect ratio substrate), which, as previously described, may be used in some embodiments. Use of a thick top metal layer of the CMOS substrate for power and ground signal distribution may at least partially mitigate the difficulties associated with long signal paths on the CMOS substrate. A metal layer may be “thick” when having a thickness greater than approximately 0.5 microns, for example having a thickness between approximately 0.5 microns and approximately 10 microns. A thick top metal layer may be referred to in some embodiments as an ultra-thick redistribution layer.
When a thick top metal layer of the CMOS substrate is reserved for power and ground signal distribution, an ultrasonic transducer formed above such a thick top metal layer may be connected to the thick top metal layer using vias or other suitable structures. CUTs and CMUTs often employ two or more electrodes. Connection of the electrode(s) of the ultrasonic transducer to the thick top metal layer may be made with one or more vias.
While some aspects of the present application implementing a metal layer for power and ground signal distribution utilize a thick top metal layer for such distribution, not all aspects are limited in this respect. For example, a top metal layer which is not necessarily thick may be employed in some embodiments. Moreover, the metal layer need not be the top metal layer in all embodiments. Various examples of ultrasonic transducers according to aspects of the present application are now illustrated and described. Each is described as including a top metal layer, which may be thick in any of the illustrated embodiments.
Transducer Example 1
Several examples of ultrasonic transducers integrated with a CMOS substrate and formed above a (top) metal layer of the CMOS substrate are now described.
The CMOS substrate 3002 represents a non-limiting example of a suitable CMOS substrate, and it should be appreciated that alternative CMOS substrates may be utilized. In the example of
A top metal layer 3014 is included with the CMOS substrate 3002, having a thickness Tm. The top metal layer 3014 may be a thick metal layer in some embodiments, and in such embodiments the thickness Tm may be between approximately 0.5 microns and approximately 10 microns, between approximately 2 microns and approximately 5 microns, any range or value within such ranges, or any other suitable value for providing decreased resistivity to facilitate functioning of the top metal layer 3014 as a signal distribution layer. The top metal layer 3014 may be patterned to create an island 3017, described further below. In addition, stress relieving openings or cuts may optionally be formed in the top metal layer 3014.
In some embodiments, the top metal layer 3014 may have liner layers above and below, such as liners 3013a and 3013b. For example, the top metal layer 3014 may be formed of aluminum with a TiN liner above and below. In some embodiments, a liner may be a multi-layer structure, for example being formed of two or more metals. As a non-limiting example, liner 3013b may include a first layer of titanium nitride (TiN) and a second layer of silicon oxynitride (SiON). SiON may be used in some embodiments as a top layer of a metallization layer since it may serve as an anti-reflective coating for photolithography purposes. Any liner included below and/or above the top metal layer may be a thin film.
The CMOS substrate 3002 further comprises an insulating layer 3016. The insulating layer 3016 may be formed of any suitable insulating material, a non-limiting example of which is SiO2.
The ultrasonic transducer 3004 includes several components. A membrane 3018 overlies a cavity 3020 in the CMOS substrate 3002. In some embodiments, the membrane 3018 seals the cavity 3020, for instance providing a vacuum. A conductive layer 3030 formed of any suitable conductive material to provide electrical connection to a bottom side of the membrane 3018 is also provided. As a non-limiting example, the conductive layer 3030 may be formed of a thin film, for example being formed of TiN.
The cavity 3020 overlies an electrode 3022 which may be considered a bottom electrode of the ultrasonic transducer 3004. The electrode 3022 may be formed of any suitable conductive material. In some embodiments, the electrode 3022 may be formed of a thin film material, such as TiN. In some embodiments, TiN may be used as an etch stop for etching the cavity 3020 in the CMOS substrate 3002. Alternatives are possible.
The sidewalls of the cavity 3020 are formed by conductive spacers 3024, which may perform various functions. For example, the conductive spacers 3024 may at least partially define the depth of the cavity 3020. The conductive spacers, sometimes in combination with other structures, may electrically connect the membrane 3018 to the top metal layer 3014. The conductive spacers 3024 may be formed of any suitable conductive material. In some embodiments, the conductive spacers 3024 may be formed of TiN, although other conductive materials may alternatively be used.
The device 3000 also includes multiple vias, disposed in the insulating layer 3016. Three such vias 3026a-3026c are illustrated. The vias 3026a-3026c may be formed of any suitable conductive material, a non-limiting example of which is tungsten (W). The vias 3026a and 3026c may provide electrical connection between the top metal layer 3014 and conductive contacts 3028a-3028b, respectively, on which the conductive spacers 3024 are disposed. The conductive contacts 3028a-3028b may be formed of any suitable conductive material, a non-limiting example of which is TiN. The via 3026b electrically connects the electrode 3022 to the island 3017 of the top metal layer 3014.
As shown, additional insulating layers 3032 and 3034 are included in the device 3000. The insulating layer 3034 may substantially cover the bottom electrode 3022 and may provide electrical insulation. Insulating layers 3032 and 3034 may be formed of any suitable insulating material, a non-limiting example of which is SiO2.
Additional structures of the device 3000 may provide electrical connection between the substrate 3006 and the electrode 3022. For instance, vias 3007 and 3009 may connect the electrode 3022 to the substrate 3006 by way of the conductive layer 3010. The vias 3007 and 3009 may be formed of any suitable conductive materials, a non-limiting example of which is tungsten.
The device 3000 may have any suitable dimensions. For example, the cavity 3020 may have a depth DC between approximately 0.05 microns and approximately 10 microns, between approximately 0.1 microns and approximately 5 microns, between approximately 0.5 microns and approximately 1.5 microns, any depth or range of depths in between, or any other suitable depth.
The width WC of the cavity 3020 may be between approximately 5 microns and approximately 500 microns, between approximately 20 microns and approximately 100 microns, may be approximately 30 microns, approximately 40 microns, approximately 50 microns, any width or range of widths in between, or any other suitable width. In some embodiments, the width may be selected to maximize the void fraction, i.e., the amount of area consumed by the cavity compared to the amount of area consumed by surrounding structures. The width dimension may also be used to identify the aperture size of the cavity, and thus the cavities may have apertures of any of the values described above or any other suitable values.
It can be seen from
The membrane thickness T1 (e.g., as measured in the direction generally parallel to the depth DC) may be less than 100 microns, less than 50 microns, less than 40 microns, less than 30 microns, less than 20 microns, less than 10 microns, less than 5 microns, less than 1 micron, less than 0.1 microns, any thickness or range of thicknesses in between, or any other suitable thickness. The thickness may be selected in some embodiments based on a desired acoustic behavior of the membrane, such as a desired resonance frequency of the membrane.
In some embodiments, the cavity dimensions and/or the membrane thickness of any membrane overlying the cavity may impact the frequency behavior of the membrane, and thus may be selected to provide a desired frequency behavior (e.g., a desired resonance frequency of the membrane). For example, it may be desired in some embodiments to have an ultrasonic transducer with a center resonance frequency of between approximately 20 kHz and approximately 200 MHz, between approximately 1 MHz and approximately 10 MHz, between approximately 2 MHz and approximately 5 MHz, between approximately 50 kHz and approximately 200 kHz, of approximately 2.5 MHz, approximately 4 MHz, any frequency or range of frequencies in between, or any other suitable frequency. For example, it may be desired to use the devices in air, gas, water, or other environments, for example for medical imaging, materials analysis, or for other reasons for which various frequencies of operation may be desired. The dimensions of the cavity and/or membrane may be selected accordingly.
Also, it should be appreciated that the cavity 3020, and more generally the cavities of any embodiments described herein, may have various shapes, and that when multiple cavities are formed not all cavities need have the same shape or size. For example, when considering a top view of the cavity 3020, the cavity may have a square aperture, a circular aperture (e.g., as in
It should be appreciated from
As previously described, the conductive layer 3010 may be patterned to form a plurality of signal lines. The top metal layer 3014 may, in some embodiments, shield the signals lines from the ultrasonic transducer 3004. Such a configuration may facilitate transmission of signals on the CMOS substrate 3002.
It should be appreciated that device 3000 illustrates an example of a device including embedded conductive structures in a CMOS substrate providing electrical connection to the membrane of an ultrasonic transducer. For example, vias 3026a-3026c are embedded in the CMOS substrate and form at least part of respective electrical paths from conductive layers of the CMOS substrate 3002 to electrodes of the ultrasonic transducer 3004.
Transducer Fabrication Example
Various processes may be used to form devices including ultrasonic transducers integrated with a CMOS substrate of the types described herein.
At stage 3704, the CMOS wafer may be processed to form one or more vias extending above the top metal layer. Such vias may be used to provide electrical connection between the top metal layer and an electrode of a subsequently formed ultrasonic transducer.
At stage 3706, the CMOS wafer may be prepared for wafer bonding with a transfer wafer. Such preparation may involve, for example, planarization and surface treatment.
At stage 3708, the CMOS wafer and the transfer wafer may be bonded using a low temperature bonding process. The transfer wafer may include one or more layers forming a membrane of an ultrasonic transducer of the bonded device. In some embodiments, the bonding may seal one or more cavities in the CMOS wafer.
At stage 3710, the transfer wafer may be thinned from the backside to leave the desired membrane.
It should be appreciated that variations on the method 3700 are possible. For example, stage 3704 may be performed after wafer bonding in some embodiments.
A process for fabricating the device 3000 consistent with the method 3700 is now illustrated and described, beginning with
Subsequently, insulating layer 3012 may be formed, for example by suitable deposition and planarization. The insulating layer 3012 may then be patterned and filled with conductive material (e.g., tungsten) to form via 3009. An etch back step or other planarization step may then be performed to provide a substantially planar upper surface.
The liner 3013a may then be deposited, followed by deposition of the top metal layer 3014. The liner 3013b may then be deposited.
As shown in
Referring to
The conductive material may then be etched back to have an upper surface substantially even with an upper surface of the insulating layer 3016, thus completing the structure shown in
As shown in
Next, referring to
Then, insulating layer 3034 may be deposited conformally and etched back to provide a desired thickness. The insulating layer 3034 may cover the bottom electrode 3022 and conductive contacts 3028a-3028b at this stage of processing. The thickness of insulating layer 3034 may assume any suitable value for covering the bottom electrode 3022 to provide electrical insulation between the bottom electrode 3022 and the conductive layer 3030 of
Referring now to
Surface treatment may then be performed as appropriate to prepare the CMOS substrate for bonding to a transfer wafer. Referring to
The wafer 3042 may include the membrane 3018 and conductive layer 3030, and thus may function as a transfer wafer to transfer the membrane 3018 to the CMOS substrate 3002. The wafer 3042 may additionally include a substrate or other base layer 3044 and an insulating layer 3046.
Non-limiting examples of suitable transfer wafers are described further below. In general, the second wafer may be any suitable type of wafer, such as a bulk silicon wafer, a silicon-on-insulator (SOI) wafer, or an engineered substrate including a polysilicon or amorphous silicon layer (e.g., membrane 3018) with an insulating layer between a single crystal silicon layer (e.g., substrate 3044) and the polysilicon or amorphous silicon layer. For example, the substrate 3044 may be a bulk silicon substrate and the insulating layer 3046 may be SiO2. The insulating layer 3046 may represent a buried oxide (BOX) layer. The membrane 3018 may be single crystal silicon, polysilicon, or amorphous silicon, as non-limiting examples, and in some embodiments may be doped to provide desired conductivity. In some embodiments, the membrane 3018 may be degeneratively doped, and in some embodiments may be P+ doped. As previously described, the conductive layer 3030, when included, may be formed of TiN as a non-limiting example.
The bonding process used for bonding the CMOS substrate 3002 and the wafer 3042 may be a low temperature bonding process suitable to preserve structures such as silicon circuitry on the CMOS substrate. For example, the bonding may not exceed 450° C. In some embodiments, the temperature of the bonding process may be between approximately 200° C. and 450° C., between approximately 300° C. and approximately 400° C., less than 250° C., any temperature(s) within those ranges, any other temperature described herein for low temperature bonding, or any other suitable temperature. Thus, damage to the metallization layers on the CMOS substrate, and any ICs on the CMOS substrate, may be avoided.
The completed device 3000 of
While
Transducer Example 2
The center portion 3106 may be formed of any suitable material. As a non-limiting example, the center portion 3106 may be formed of TiN. However, other conductive, semiconductor, or insulating materials may be used. In some embodiments, it may be desirable for the center portion 3106 to be formed of a different material than membrane 3018 to allow for the piston membrane to exhibit target behavior with respect to characteristics such as flexibility, capacitive operation, and robustness, among other possible characteristics relevant to operation of the transducer.
In addition, the device 3100 includes a membrane stop 3108. In some embodiments, the membrane stop, which may be formed of any suitable material, such as an insulating material (e.g., SiO2), may function as an isolation post and may provide various benefits. Membrane stops may effectively alter the depth of a cavity such that a membrane may contact the bottom of the cavity (referred to as collapse) more easily, and may alter the frequency behavior of an ultrasonic transducer. Namely, when the membrane is pulled down far enough, it makes contact with the bottom of the cavity. Such operation may be advantageous since having the membrane hit or contact the bottom of the cavity can dampen certain resonant modes, thereby broadening the frequency response of the transducer. However, there is a “charge trapping” effect, in which charge may end up deposited on the electrodes of the transducer, thereby altering the operating characteristics of the transducer (e.g., increasing the necessary bias voltage), and causing hysteresis. Membrane stops may provide the benefit of “bottoming out” the membrane, while substantially reducing the charge trapping effect and problems with hysteresis. Ultrasonic transducers with membrane stops may be more reliable after collapse than ultrasonic devices lacking such membrane stops. Moreover, because the membrane stop may prevent the membrane from contacting the bottom-most part of the cavity, insulation need not be formed on the bottom surface of the cavity in all embodiments, which can therefore reduce processing steps and time in fabricating an ultrasonic transducer. However, the insulator on the bottom surface of the cavity may be used in case of unanticipated contact between the membrane and the bottom of the cavity (despite any membrane stop) and/or to prevent electrical discharge across the cavity.
Membrane stops may be formed in different locations of an ultrasonic transducer. For example, membrane stops may be formed on the bottom of a cavity of an ultrasonic transducer. In some embodiments, membrane stops may be formed on the bottom of a membrane of the ultrasonic transducer (e.g., on the bottom side of a membrane transferred from a transfer wafer). In other embodiments, membrane stops may be formed on both the bottom of a cavity and the bottom of a membrane of an ultrasonic transducer.
The membrane stop 3108 may control how far the membrane 3018 can move relative to the bottom electrode 3022, and may have any suitable thickness for providing such control. For example, the membrane stop 3108 may have a thickness between approximately 5% and 30% of the cavity depth, between approximately 10% and 20% of the cavity depth, or any value within such ranges. An insulating layer 3110, for example formed of SiO2, may substantially cover the membrane stop 3108 in addition to the bottom electrode 3022.
The ultrasonic transducer 3102 also differs from the ultrasonic transducer 3004 in that the conductive spacers 3024 are replaced by conductive spacers 3112 that are formed by multiple distinct portions 3114 and 3116. The conductive spacers 3112 provide electrical connection from the membrane 3018 to the top metal layer 3014 together with the conductive contacts 3028a-3028b and the vias 3026a and 3026c. The portions 3114 and 3116 may be formed of TiN or other suitable conductive materials.
It should be appreciated that the device 3100 therefore represents another example of a device configuration including embedded conductive structures in a CMOS substrate providing electrical connection to the membrane of an ultrasonic transducer.
An example of a process for fabricating the device 3100 is now described. The process may proceed in substantially the same manner as that previously described in connection with device 3000 up to the formation of insulating layer 3032. Then, an insulating layer may be conformally deposited and patterned to form membrane stop 3108. Next, insulating layer 3110 may be deposited and patterned to form openings above the conductive contacts 3028a and 3028b.
A conductive material may then be deposited, patterned and planarized as appropriate to form portion 3116 of the conductive spacers 3112. Surface treatment may be performed as appropriate to prepare the CMOS substrate for bonding to a transfer wafer.
Subsequently, as shown in
Then, the wafer 3118 may be processed in any suitable manner to remove the substrate 3044 and insulating layer 3046. For example, any of the techniques described with respect to processing of such layers of the transfer wafer 3042 may be utilized. In this manner, the final structure illustrated in
Thus, it should be appreciated from
Transducer Example 3
As shown, the piston membrane 3204 includes a center region 3206 and a peripheral region 3208. The center region 3206 may be thicker than the peripheral region 3208, as illustrated, with the relative thicknesses of the two regions assuming any suitable value to provide desired operation of the ultrasonic transducer 3202.
The piston membrane 3204 may be formed of any suitable material. As a non-limiting example, the piston membrane 3204 may be formed of silicon, which may be doped in some embodiments to provide desired electrical conductivity. For example, in those embodiments in which the piston membrane 3204 is formed of silicon, the silicon may be doped with a positive dopant, such as phosphorus. As also shown, the center region 3206 may have a width Wp substantially corresponding to the width Wb of the bottom electrode 3022, which may provide beneficial capacitive behavior of the ultrasonic transducer. However, alternative configurations are possible.
An example of a process for fabricating the device 3200 is now described. The process may proceed in substantially the same manner as that previously described in connection with formation of device 3000 up through the point illustrated in
The insulating layer 3212 may be formed of any suitable material. As a non-limiting example, the insulating layer 3212 may be formed of SiO2 or any other suitable dielectric insulating material. In some embodiments, the insulating layer 3212 may be formed via tetraethyl orthosilicate (TEOS), though alternative processes may be used.
The bonding of CMOS substrate 3002 and transfer wafer 3210 may involve any suitable bonding process. For instance, a low temperature bonding process of the types described herein may be utilized.
Subsequently, substrate 3044, insulating layer 3046, and insulating layer 3212 may be removed in any suitable manner to arrive at the structure of
Devices 3000-3200 represent non-limiting examples of devices including ultrasonic transducers having conductive sidewalls. Several examples of ultrasonic transducers formed on CMOS substrates and having non-conductive sidewalls are now illustrated and described.
Transducer Example 4
As shown, the membrane 3018 makes direct contact with an upper surface of the via 3308. Thus, an electrical path from the membrane 3018 to the top metal layer 3014 is provided by a combination of via 3308, conductive contact 3028a, and via 3026a.
An example of a process for fabricating the device 3300 is now described. The process may proceed in substantially the same manner as that previously described in connection with the formation of device 3000 up through the point illustrated in
Subsequently, an insulating layer may be deposited or otherwise formed and planarized in preparation of forming non-conductive spacers 3306. The insulating layer may be conformally deposited to cover the surface of the CMOS substrate, and then may be patterned to create trenches or other openings for the vias 3308. Then, the liner 3310 may be deposited in the trenches and the trenches filled with conductive material to form the vias 3308. A planarization or etch back may optionally be performed. The insulating layer deposited to form the non-conductive spacers 3306 may then be suitably patterned to form the non-conductive spacers.
Then, insulating layer 3312 may be deposited and the structure may be planarized and treated in preparation for bonding, to remove the insulating layer 3312 from the upper surfaces of the non-conductive spacers 3306. Next, a transfer wafer similar to the transfer wafer 3042, but lacking conductive layer 3030, may be aligned with and bonded to the CMOS substrate 3304. The substrate 3044 and insulating layer 3046 may then be removed to achieve the device 3300.
Transducer Example 5
Another example of a device including an ultrasonic transducer above a top metal layer of a CMOS substrate is illustrated in
The device 3400 further includes layers 3410 and 3412 which may serve multiple functions in the illustrated embodiment. For instance, the layers 3410 and 3412 may passivate the upper surface of the via 3406. Additionally, the layers 3410 and 3412 may be patterned as shown to create a piston membrane in combination with membrane 3018. The thicknesses of layers 3410 and 3412 may be selected to provide desired operating characteristics to the ultrasonic transducer 3402.
The layers 3410 and 3412 may be formed of any suitable materials, and in some embodiments are formed of insulating materials. For example, layer 3410 may be SiO2 and layer 3412 may be silicon nitride (Si3N4) according to a non-limiting example. However, alternative passivation materials may be used.
An example of a process for fabricating the device 3400 is now described. The process may proceed in substantially the same manner as that previously described in connection with fabrication of device 3300 except that formation of the vias 3308 may be omitted. Thus, the membrane 3018 may be bonded with the CMOS substrate 3404 without vias in place connecting the membrane 3018 to the conductive contacts 3028a and 3028b. The bonding may be a low temperature bond, for example of the types described previously herein.
Then, after the bonding, the membrane 3018 and non-conductive spacers 3306 may be etched to form trenches which may be lined with liner 3408 and filled with conductive material to form vias 3406. The upper surface of the structure may be planarized as appropriate and layers 3410 and 3412 may be deposited and patterned to arrive at the device 3400.
Transducer Example 6
The contacts 3506 may be passivated with layers 3510 and 3512. Layer 3510 may be the same material as previously described layer 3410 but may be thicker. Layer 3512 may be the same material as previously described layer 3412 but may be thicker. Layers 3510 and 3512 may be patterned as shown to form a piston membrane configuration in combination with membrane 3018.
An example of a process for fabricating the device 3500 is now described. A transfer wafer including the membrane 3018 may be aligned with and bonded to the substrate 3504. Then the transfer wafer may be thinned as desired (e.g., to remove any bulk substrate and buried oxide layer) and the contacts 3506 formed. Layers 3510 and 3512 may then be deposited and patterned in the manner previously described in connection with layers 3410 and 3412 to arrive at the device 3500.
It should be appreciated from the foregoing discussion of examples of ultrasonic transducers integrated with CMOS substrates that the processes used to fabricate such devices may be low temperature processes. The temperatures of all steps performed involving the CMOS substrate once circuit structures are formed on the substrate, including wafer bonding to a transfer wafer, anneals, or other steps, may be kept below temperatures which would cause damage to such circuit components.
Various examples of ultrasonic transducers integrated with a CMOS substrate have been described. It should be appreciated that such devices may have any suitable dimensions. Non-limiting examples of suitable dimensions have been described at least in connection with
Transfer Wafers
Various examples of transfer wafers have been described herein for use with various embodiments. In some embodiments, traditional SOI wafers may be used, having a silicon bulk wafer as a handle layer, buried oxide layer, and monocrystalline silicon layer. However, as previously described, some embodiments implement alternative types of transfer wafers, including transfer wafers having polysilicon or amorphous silicon layers, for example when such materials are to be used as the membrane 3018. Applicants have appreciated that transfer wafers having such materials may be implemented in some embodiments instead of traditional SOI wafers, and that such alternative types of transfer wafers may be fabricated with significantly less effort and cost than required to form traditional SOI wafers.
Wafers Including Multiple Ultrasonic Transducers
The examples of
When multiple ultrasonic transducers are formed on a CMOS substrate, they may optionally be electrically interconnected in various manners to form a desired device. For example, multiple ultrasonic transducers may be electrically tied by way of the top metal layer 3014 previously described. Other manners of providing electrical interconnection are also possible.
Forms of Integration of Ultrasonic Transducers with Substrates and Circuitry
While various aspects and embodiments have been described as providing monolithically integrated ultrasonic transducers and CMOS wafers having ICs formed therein, not all aspects and embodiments are limited in this respect. For example, some aspects of the present application may also apply to flip-chip bonded and multi-chip configurations. For example, making electrical contact to the bottom side of a membrane may be performed in flip-chip bonded configurations. Other aspects may also apply to non-monolithic devices.
As described previously, an aspect of the present application provides an ultrasonic transducer cell integrated with CMOS circuitry where the circuitry is disposed beneath the transducer.
As shown, the device 3600 may include the ultrasonic transducer of
As shown, both the electrode 3022 and the conductive contacts 3028a and 3028b may be connected to the integrated circuit 3602, for example by respective vias. For instance, the electrode 3022 may be connected to the integrated circuit 3602 by vias 3007. 3009, and 3026b. The conductive contact 3028b may be connected to the integrated circuit 3602 by vias 3604, 3606, and 3026c. The via connecting the electrode 3022 may, for example, directly contact a doped source/drain terminal of a MOS transistor in the substrate 3006.
As shown in
In some embodiments, the membrane of the ultrasonic transducer may be biased. In such situations, the membrane may be connected to the integrated circuit 3602 via a capacitor (not shown) for providing or maintaining a desired bias level. Other biasing configurations are also possible.
In some embodiments, the electrode 3022 may be driven, and thus the integrated circuit 3602 may be suitably connected to drive the electrode 3022. In some embodiments, the electrode 3022 may be biased, rather than the membrane.
Transducer Fabrication Technology
The various non-limiting examples of ultrasonic transducers fabricated on CMOS substrates described herein may be fabricated with any suitable feature sizes. According to an embodiment, 0.18 micron technology may be utilized for fabricating such ultrasonic transducers. In some embodiments, 0.13 micron technology may be used. In some embodiments, 90 nm fabrication technology may be used. In some embodiments, 0.35 micron technology may be utilized. Other feature sizes may be used, as those listed represent non-limiting examples.
Various non-limiting examples of ultrasonic transducers which may be used in an ultrasound transducer probe according to one or more aspects of the present application have been described. It should be appreciated, however, that not all aspects of the present application are limited to using such ultrasonic transducers.
The illustrated examples of devices 3000, 3100, 3200, 3300, 3400, and 3500 have been described primarily as utilizing aluminum metal processing techniques. However, other techniques of forming ultrasonic transducers integrated with CMOS substrates may alternatively be used. For example, copper processing techniques, such as damascene or dual damascene processing may be used in some embodiments. For such processing, the interlayer dielectrics used may include SiO2 or other low-K materials, where K represents the dielectric constant. Barrier layers used in combination with copper metallization may include tantalum (Ta), tantalum nitride (TaN), and TiN. Thus, according to aspects of the present application an integrated device may include one or more ultrasonic transducers integrated with a CMOS substrate including CMOS integrated circuitry having copper metallization, and formed using damascene or dual damascene processing.
In some embodiments, a combination of aluminum processing and copper processing techniques may be implemented. For example, referring to the device 3000, the underlying CMOS substrate may be formed using copper-based dual damascene processes. The top metal layer 3014 may be aluminum or aluminum-copper. Thus, a combination of copper processing techniques and aluminum processing techniques may be utilized to fabricate such devices.
Process
As described previously, aspects of the present application provide an ultrasound transducer probe which may be tiled and interconnected by suitably replicating the ultrasound transducer probe. According to some aspects, such replication may be performed using a common photolithography mask or reticle with appropriate stepping and/or scanning functions. Various examples are now described.
According to an aspect of the present application, an ultrasound transducer probe may be fabricated by suitably rotating and printing a pattern from a photolithography mask (also referred to herein as a “pattern mask”) to create two side-by-side (or horizontally tiled) instances of the pattern. Referring to
An ultrasound transducer probe of the type 220 illustrated in
Another manner of horizontally tiling ultrasound transducer probes of the types described herein involves printing portions of a reticle in alignment with each other, and is described in connection with
The reticle 3900 may be considered to have multiple portions defined by the positions A-D. For example, position A to B represents a portion, position A to C another portion, position B to C another portion, position B to D another portion, and so on for all combinations of positions A-D. Printing appropriate portions and aligning them may result in creation of an ultrasound transducer probe. Alignment marks may be provided at the positions A-D to facilitate printing of the portions and aligning them.
The double-wide ultrasound transducer probe 4000 of
Next, the reticle 3900 may be stepped such that position B on the reticle aligns with position C on the printed pattern. A second portion of the reticle 3900 may then be scanned from position B to position D. The result is shown as pattern 4004 in
Thus, it should be appreciated that the ultrasound transducer probe 4000 may include I/O circuitry on opposing ends and a central region comprising ultrasonic transducers. Also, such horizontal tiling may be achieved with a single photolithographic mask, thus greatly simplifying the process and cost compared to if multiple masks were used.
When scanning only a portion of a reticle (e.g., from position A to position C of reticle 3900, from position B to position C of reticle 3900, and from position B to position D of reticle 3900), blading techniques or other suitable techniques may be used to obstruct or otherwise avoid printing undesired portions of the reticle pattern.
It should be appreciated from the foregoing that multiple instances of an ultrasound transducer probe may be horizontally tiled on a wafer to form an ultrasound transducer probe of desired dimensions using a common reticle. Vertical tiling may be accomplished by stepping the reticle vertically and suitably aligning it. Thus, multiple instances of an ultrasound transducer probe may be tiled horizontally and/or vertically.
Moreover, it should be appreciated that blading techniques may be used to facilitate tiling of ultrasound transducer probes having peripheral regions on the top and/or bottom side of the transducer probe while still providing a contiguous region of ultrasonic transducers. For example, peripheral regions of an ultrasound transducer probe located on the top and bottom sides of the transducer probe and having only contact pads may be vertically tiled while still creating a contiguous region of ultrasonic transducers by blading one or more of such peripheral regions.
The aspects of the present application may provide one or more benefits, some of which have been previously described. Now described are some non-limiting examples of such benefits. It should be appreciated that not all aspects and embodiments necessarily provide all of the benefits now described. Further, it should be appreciated that aspects of the present application may provide additional benefits to those now described.
Some aspects of the present application provide ultrasound transducer probes which are configured to be tiled and interconnected, thus providing an ultrasound probe designer great flexibility in designing an ultrasound probe of choice by mere replication and suitable placement of a common building block ultrasound unit. Some aspects provide ultrasound transducer probes which are connectable to different types of external devices via different physical interfaces, thus increasing usability and accessibility of the devices. Some aspects provide an ultrasound transducer probe that is configurable to operate in various modes, including various ultrasound imaging modes. In some aspects, the ultrasound transducer probes may be highly integrated, including ultrasound transducers and ICs monolithically integrated on a common substrate, providing a compact form factor.
Ultrasound transducer probes according to aspects of the present application may be worn, and used in-situ. Thus, the usefulness of such devices may be greater than conventional ultrasound probes.
Having thus described several aspects and embodiments of the technology of this application, it is to be appreciated that various alterations, modifications, and improvements will readily occur to those of ordinary skill in the art. Such alterations, modifications, and improvements are intended to be within the spirit and scope of the technology described in the application. For example, those of ordinary skill in the art will readily envision a variety of other means and/or structures for performing the function and/or obtaining the results and/or one or more of the advantages described herein, and each of such variations and/or modifications is deemed to be within the scope of the embodiments described herein. Those skilled in the art will recognize, or be able to ascertain using no more than routine experimentation, many equivalents to the specific embodiments described herein. It is, therefore, to be understood that the foregoing embodiments are presented by way of example only and that, within the scope of the appended claims and equivalents thereto, inventive embodiments may be practiced otherwise than as specifically described. In addition, any combination of two or more features, systems, articles, materials, kits, and/or methods described herein, if such features, systems, articles, materials, kits, and/or methods are not mutually inconsistent, is included within the scope of the present disclosure.
The above-described embodiments can be implemented in any of numerous ways. One or more aspects and embodiments of the present application involving the performance of processes or methods may utilize program instructions executable by a device (e.g., a computer, a processor, or other device) to perform, or control performance of, the processes or methods. In this respect, various inventive concepts may be embodied as a computer readable storage medium (or multiple computer readable storage media) (e.g., a computer memory, one or more floppy discs, compact discs, optical discs, magnetic tapes, flash memories, circuit configurations in Field Programmable Gate Arrays or other semiconductor devices, or other tangible computer storage medium) encoded with one or more programs that, when executed on one or more computers or other processors, perform methods that implement one or more of the various embodiments described above. The computer readable medium or media can be transportable, such that the program or programs stored thereon can be loaded onto one or more different computers or other processors to implement various ones of the aspects described above. In some embodiments, computer readable media may be non-transitory media.
The terms “program” or “software” are used herein in a generic sense to refer to any type of computer code or set of computer-executable instructions that can be employed to program a computer or other processor to implement various aspects as described above. Additionally, it should be appreciated that according to one aspect, one or more computer programs that when executed perform methods of the present application need not reside on a single computer or processor, but may be distributed in a modular fashion among a number of different computers or processors to implement various aspects of the present application.
Computer-executable instructions may be in many forms, such as program modules, executed by one or more computers or other devices. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types. Typically the functionality of the program modules may be combined or distributed as desired in various embodiments.
Also, data structures may be stored in computer-readable media in any suitable form. For simplicity of illustration, data structures may be shown to have fields that are related through location in the data structure. Such relationships may likewise be achieved by assigning storage for the fields with locations in a computer-readable medium that convey relationship between the fields. However, any suitable mechanism may be used to establish a relationship between information in fields of a data structure, including through the use of pointers, tags or other mechanisms that establish relationship between data elements.
When implemented in software, the software code can be executed on any suitable processor or collection of processors, whether provided in a single computer or distributed among multiple computers.
Further, it should be appreciated that a computer may be embodied in any of a number of forms, such as a rack-mounted computer, a desktop computer, a laptop computer, or a tablet computer, as non-limiting examples. Additionally, a computer may be embedded in a device not generally regarded as a computer but with suitable processing capabilities, including a Personal Digital Assistant (PDA), a smart phone or any other suitable portable or fixed electronic device.
Also, a computer may have one or more input and output devices. These devices can be used, among other things, to present a user interface. Examples of output devices that can be used to provide a user interface include printers or display screens for visual presentation of output and speakers or other sound generating devices for audible presentation of output. Examples of input devices that can be used for a user interface include keyboards, and pointing devices, such as mice, touch pads, and digitizing tablets. As another example, a computer may receive input information through speech recognition or in other audible formats.
Such computers may be interconnected by one or more networks in any suitable form, including a local area network or a wide area network, such as an enterprise network, and intelligent network (IN) or the Internet. Such networks may be based on any suitable technology and may operate according to any suitable protocol and may include wireless networks or wired networks.
Also, as described, some aspects may be embodied as one or more methods. The acts performed as part of the method may be ordered in any suitable way. Accordingly, embodiments may be constructed in which acts are performed in an order different than illustrated, which may include performing some acts simultaneously, even though shown as sequential acts in illustrative embodiments.
All definitions, as defined and used herein, should be understood to control over dictionary definitions, definitions in documents incorporated by reference, and/or ordinary meanings of the defined terms.
The indefinite articles “a” and “an,” as used herein in the specification and in the claims, unless clearly indicated to the contrary, should be understood to mean “at least one.”
The phrase “and/or,” as used herein in the specification and in the claims, should be understood to mean “either or both” of the elements so conjoined, i.e., elements that are conjunctively present in some cases and disjunctively present in other cases. Multiple elements listed with “and/or” should be construed in the same fashion, i.e., “one or more” of the elements so conjoined. Elements other than those specifically identified by the “and/or” clause may optionally be present, whether related or unrelated to those elements specifically identified. Thus, as a non-limiting example, a reference to “A and/or B”, when used in conjunction with open-ended language such as “comprising” can refer, in one embodiment, to A only (optionally including elements other than B); in another embodiment, to B only (optionally including elements other than A); in yet another embodiment, to both A and B (optionally including other elements); etc.
As used herein in the specification and in the claims, the phrase “at least one,” in reference to a list of one or more elements, should be understood to mean at least one element selected from any one or more of the elements in the list of elements, but not necessarily including at least one of each and every element specifically listed within the list of elements and not excluding any combinations of elements in the list of elements. This definition also allows that elements may optionally be present other than the elements specifically identified within the list of elements to which the phrase “at least one” refers, whether related or unrelated to those elements specifically identified. Thus, as a non-limiting example, “at least one of A and B” (or, equivalently, “at least one of A or B,” or, equivalently “at least one of A and/or B”) can refer, in one embodiment, to at least one, optionally including more than one, A, with no B present (and optionally including elements other than B); in another embodiment, to at least one, optionally including more than one, B, with no A present (and optionally including elements other than A); in yet another embodiment, to at least one, optionally including more than one, A, and at least one, optionally including more than one, B (and optionally including other elements); etc.
As used herein, the term “between” is to be inclusive unless indicated otherwise. For example, “between A and B” includes A and B unless indicated otherwise.
Also, the phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting. The use of “including,” “comprising,” or “having,” “containing,” “involving,” and variations thereof herein, is meant to encompass the items listed thereafter and equivalents thereof as well as additional items.
In the claims, as well as in the specification above, all transitional phrases such as “comprising,” “including,” “carrying,” “having,” “containing,” “involving,” “holding,” “composed of,” and the like are to be understood to be open-ended, i.e., to mean including but not limited to. Only the transitional phrases “consisting of” and “consisting essentially of” shall be closed or semi-closed transitional phrases, respectively.
This application claims the benefit under 35 U.S.C. §119(e) of U.S. Provisional Patent Application Ser. No. 61/857,682, filed on Jul. 23, 2013 and entitled “INTERCONNECTABLE ULTRASOUND TRANSDUCER PROBES AND RELATED METHODS AND APPARATUS”, which is hereby incorporated herein by reference in its entirety.
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