Claims
- 1. An interconnected array of semiconductor devices, said array comprising:
- a plurality of semiconductor devices arrayed on a substrate each spaced apart from each one adjacent thereto in that said plurality of semiconductor devices by a separating space having therein intervening material means, said plurality of semiconductor devices each having therein a support layer of a first conductive material and a corresponding layer of semiconductor material with first and second major surfaces such that said semiconductor material layer is separated at said second major surface thereof from said substrate by its corresponding support layer, said plurality of semiconductor devices each having a penetrating terminal therein of a second conductive material spaced apart from any said separating space and extending from said support layer therein through said semiconductor material layer therein to emerge at said first major surface of that said semiconductor material layer which remains a unitary electrically conductive body with that said penetrating terminal therethrough; and
- a plurality of interconnection layer means comprising at least a third conductive material which is transparent to visible light, said plurality of said interconnection layer means each being in electrical contact with said first major surface of said semiconductor material layer of one of said plurality of semiconductor devices and each further being in electrical contact with a said penetrating terminal where it emerges from said first major surface of said semiconductor material layer in an adjacent one of said plurality of semiconductor devices by having a selected one of that interconnection layer means and that penetrating terminal extend over said intervening material means across a said separating space to to thereby form an electrical interconnection, said third conductive material having an outer surface on a side thereof opposite said semiconductor material layer which is free of any of said intervening material means.
- 2. The apparatus of claim 1 wherein each of said plurality of interconnection layer means, in electrically interconnecting said first major surface of said semiconductor layer in one of said plurality of semiconductor devices ends before coming into electrical contact with said penetrating terminal thereof.
- 3. The apparatus of claim 2 wherein each of said plurality of interconnection layer means, in electrically interconnecting said first major surface of said semiconductor material layer in one of said plurality of semiconductor devices ends on a protective insulating material formed on said first major surface of said semiconductor material layer in that one of said plurality of semiconductor devices.
- 4. The apparatus of claim 3 wherein each of said plurality of interconnection layer means, in electrically interconnecting a said penetrating terminal, also ends on said protective insulating material formed on said first major surface of said semiconductor material layer in that one of said plurality of said semiconductor device in which said penetrating terminal is formed, with each of those ones of said plurality of interconnection layer means ending in common on a said protective insulating material being spaced apart from one another.
- 5. The apparatus of claim 1 wherein each said penetrating terminal is of a material comprising metal.
- 6. The apparatus of claim 1 wherein each said intervening material means is an electrical insulating material.
- 7. The apparatus of claim 6 wherein said intervening material is a polymer material.
- 8. The apparatus of claim 1 wherein said substrate is a material which is an electrical insulating material.
- 9. The apparatus of claim 8 wherein said substrate is a polyimide material.
- 10. The apparatus of claim 1 wherein each said semiconductor material comprises amorphous, hydrogenated silicon doped to have a p-n junction therein.
- 11. The apparatus of claim 10 wherein each said semiconductor material layer has a p-n junction therein with said support layer corresponding to that said semiconductor material layer being in electrical contact with said second major surface of that said semiconductor material layer on one side of said p-n junction, and with each of said plurality of interconnection layer means in electrical contact with said first major surface of that said semiconductor material layer being in such contact on an opposite side of said p-n junction.
- 12. The apparatus of claim 1 wherein said semiconductor material layer comprises amorphous, hydrogenated silicon doped to have a p-type conductivity layer and an n-type conductivity layer separated by an intrinsic layer.
- 13. The apparatus of claim 1 wherein each said support layer comprises a metal material.
- 14. The apparatus of claim 1 wherein each said interconnection layer is transparent to visible light.
- 15. The apparatus of claim 14 wherein each said interconnection layer comprises indium tin oxide.
Parent Case Info
This is a division of co-pending application Ser. No. 07/131,416, filed Dec. 10, 1987, now U.S. Pat. No. 4,873,201.
INTERCONNECTED SEMICONDUCTOR DEVICES
The Government of the United States of America has rights in this invention pursuant to Subcontract ZB-4-03056-2 awarded by the United States Department of Energy.
US Referenced Citations (14)
Foreign Referenced Citations (1)
Number |
Date |
Country |
0119979 |
Jun 1987 |
JPX |
Divisions (1)
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Number |
Date |
Country |
Parent |
131416 |
Dec 1987 |
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