Patent Application
20080200046
Memory cells of memory arrays such as volatile or non-volatile memory arrays use an interconnection structure to connect the memory cells of the array to support circuits (e.g., sense amplifiers, decoders and wordlines). Future technologies aim for smaller minimum feature sizes to increase the storage density and to reduce the cost of memory products. When scaling memory arrays down to smaller minimum feature sizes, interconnection structures also have to be scaled down. Scaling down of interconnection structures such as bitlines and bitline contacts comprising minimum feature sizes is crucial and challenging in view of feasibility of lithography, taper of contact edge or resistance of fill materials, for example.
An interconnection structure is described herein, which can, for example, be used in a memory cell array such as a volatile or non-volatile memory cell array. A memory device, a memory card comprising the memory device and an electric device configured to be connected to the memory card are also described herein. In addition, a method of manufacturing an interconnection structure is described herein.
An interconnection structure comprises two staggered rows of evenly spaced contact openings, wherein each contact row extends along a first direction. The interconnection structure further comprises conductive lines, which extend along a second direction intersecting the first direction, as well as intermediate contacts, wherein each intermediate contact is in contact with one of the contacts and one of the conductive lines.
The accompanying drawings are included to provide a further understanding of the embodiments of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate the embodiments of the present invention and together with the description serve to explain the principles of the invention. Other embodiments and many of the intended advantages will be readily appreciated as they become better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts.
In the following detailed description reference is made to the accompanying drawings, which forms a part hereof and in which are shown by way of illustration specific embodiments. In this regard, directional terminology such as “top”, “bottom”, “front”, “back”, “leading”, “trailing”, etc., is used with reference to the orientation of the Figures being described. Since components of embodiments may be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and in no way limiting. It is to be understood that further embodiments may be utilized and structural or logical changes may be made. The following detailed description, therefore, is not to be taken in a limiting sense.
According to an embodiment an interconnection structure comprises two staggered rows, i.e., first and second rows, of evenly spaced contact openings, wherein each contact row extends in a first direction. The interconnection structure further comprises conductive lines, which extend along a second direction intersecting the first direction, as well as intermediate contacts, wherein each intermediate contact is in contact with one of the contacts and one of the conductive lines. The interconnection structure further comprises an insulating layer, which adjoins a bottom side of the conductive lines and a sidewall of the intermediate contacts.
The conductive lines, intermediate contacts and contacts may form bitlines and bitline contacts connecting memory cells to support circuits. However, the conductive lines, intermediate contacts and contacts may also be used to connect any kind of functional region of an integrated circuit to a further functional region of the integrated circuit. The conductive lines, intermediate contacts and contacts may be formed of any conductive material such as metal, noble metal, metal alloys or doped semiconductors. Although a common material may be used to realize the conductive lines, intermediate contacts and contacts, material compositions of these parts may also entirely or partly differ from each other. Exemplary materials include: W, TiN, WN, TaN, Cu, Ta, Al, metal silicides, doped silicon or any combination thereof. The conductive lines, intermediate contacts and contacts may be surrounded by a liner, for example. The insulating layer being in direct contact with a bottom side of the conductive lines and a sidewall of the intermediate contacts may be formed of any material suitable to electrically isolate conductive regions from each other. Exemplary materials include oxides and nitrides, e.g., silicon oxide and silicon nitride. The second direction may be perpendicular to the first direction, for example.
According to a further embodiment the contacts of the two staggered rows are shifted by one half contact pitch to each other. According to an exemplary embodiment the contacts of one row are equally spaced by four times a minimum feature size, wherein the contacts of the two staggered rows are shifted by twice the minimum feature size to each other.
A further embodiment provides an interconnection structure, wherein a dimension of the intermediate contacts along the first direction is smaller than a largest dimension of the contacts along the first direction. As the contacts are connected to the conductive lines by the intermediate contacts, it is possible to dimension a top side of the contacts along the first direction larger than a bottom side of the conductive lines. Thus, requirements with regard to a critical dimension on top of the contacts can be relaxed.
According to a further embodiment, the intermediate contacts are formed as a trimmed part of the respective contacts shortened along the first direction. As the trimmed part may be fabricated by an etch process, sidewalls of the intermediate contact along the first direction will not be covered by a liner in case the contacts below are surrounded by such a liner.
A further embodiment relates to an interconnection structure wherein the intermediate contacts are intermediate contact lines, which extend along the second direction and are at least part of a line array. The line array offers benefits in view of feasibility of lithography when realizing interconnection structures involving components having minimum feature sizes.
According to a further embodiment of the interconnection structure, each intermediate contact line in contact with a respective contact of one of the two staggered rows is absent in an intersection region with regard to the other one of the two staggered rows. By leaving out the intermediate contact line in the intersection region undesirable shorts to contacts of the other one of the two staggered contact rows, which may be caused by process variations, are prevented.
The line array may further comprise intermediate contact lines and further lines. The further lines may be appropriately positioned to achieve a line array that is beneficial with regard to feasibility of lithography during manufacture of the line array.
A further embodiment relates to an interconnection structure comprising two staggered contact rows of evenly spaced contacts, i.e., first and second contact rows, wherein each contact row extends along a first direction. The interconnection structure further comprises conductive lines, which extend along a second direction intersection the first direction, as well as intermediate contacts, wherein each intermediate contact is a trimmed upper part of a respective contact that adjoins one of the conductive lines.
The interconnection structure may further comprise an insulating layer, which adjoins a bottom side of the conductive lines and a sidewall of the intermediate contact regions. The insulating layer may be a single layer, for example.
According to a further embodiment, an interconnection structure comprises two staggered contact rows of evenly spaced contacts, i.e., first and second contact rows, wherein each contact row extends along a first direction. The interconnection structure further comprises conductive lines, which extend along a second direction intersecting the first direction, as well as intermediate contacts, wherein each intermediate contact is an intermediate contact line extending along the second direction, and wherein each intermediate contact line is in contact with one of the contacts and one of the conductive lines.
The interconnection structure may further comprise an insulating layer, which adjoins a bottom side of the conductive lines and a sidewall of the intermediate contact lines.
A further embodiment relates to an interconnection structure, wherein the intermediate contact lines are at least part of a line array.
According to a further embodiment of the interconnection structure, each intermediate contact line in contact with a respective contact of one of the two staggered rows is absent in an intersection region with regard to the other one of the two staggered rows.
A further embodiment relates to an interconnection structure, wherein a dimension of the intermediate contact lines along the first direction is smaller than the largest dimension of the contacts along the first direction.
According to a further embodiment, a non-volatile semiconductor memory device comprises a memory cell array of non-volatile memory cells and an interconnection structure as defined by any of the above described embodiments, wherein the conductive lines define bitlines and the contacts and respective intermediate contacts define bitline contacts. The non-volatile memory cells may be memory cells of a floating gate NAND array, for example. The interconnection structure may, for example, also be included in: a NROM (Nitrided Read Only Memory), DRAM (Dynamic Random Access Memory), charge trapping NAND memory, SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) memory, SANOS (Silicon-AI2O3-Nitride-Oxide-Silicon) memory, TANOS (Oxide-SiN—Al2O3—TaN) memory.
A further embodiment relates to an electric memory card comprising a non-volatile semiconductor memory device as defined above.
A further embodiment relates to an electric device comprising an electric card interface, a card slot connected to the electric card interface and the electric memory card as defined above, wherein the electric memory card is configured to be connected and removed from the card slot. The electric device may be a cellular phone, a personal computer (PC), a personal digital assistant (PDA), a digital still camera, a digital video camera or a portable MP3 player, for example.
A further embodiment relates to a method of forming an interconnection structure comprising providing a substrate, providing a first insulating layer on the substrate, etching, into the first insulating layer, two staggered rows of evenly spaced contact openings, i.e., first and second rows, wherein each row extends along a first direction, filling the contact openings with a conductive material to provide contacts, providing a second insulating layer on the first insulating layer and the contacts, etching intermediate contact openings into the second insulating layer, providing intermediate contacts by filling the intermediate contact openings with a conductive material and providing conductive lines on the second insulating layer and the intermediate contacts, wherein the conductive lines extend along a second direction intersecting the first direction.
The substrate may be a semiconductor substrate such as a silicon substrate, which may be pre-processed to fabricate a semiconductor memory device therein, for example. The above method features may be included in a semiconductor memory process. Thus, above described method features may be simultaneously used for fabrication of further components outside of the interconnection structure.
It should be noted that, generally, for patterning material layers by etching, a photolithographic method may be used in which a suitable photo resist material is provided. The photo resist material is photolithographically patterned using a suitable photo mask. The patterned photo resist layer can be used as a mask during subsequent process steps. For example, as is common, a hardmask layer or a layer made of a suitable material such as silicon nitride, polysilicon or carbon may be provided over the material layer to be patterned. The hardmask layer is photolithographically patterned using an etching process, for example. Taking the patterned hardmask layer as an etching mask, the material layer is patterned. A patterning of the material layer by etching may also be carried out by using the patterned photo resist material as an etching mask.
According to a further embodiment, a dimension of each of the intermediate contact openings along the first direction is smaller than a largest dimension of each of the contacts along the first direction.
A further embodiment comprises a method of forming the interconnection structure, wherein, when filling the intermediate contact openings with the conductive material, the conductive material is additionally applied on the second insulating layer. The conductive material on the second insulating layer is then etched to provide the conductive lines. Thus, the conductive material for the intermediate contacts and the conductive lines is applied by a common process step.
According to a further embodiment, the feature of providing the conductive line comprises providing a conductive layer on the second insulating layer and the intermediate contacts and etching the conductive layer to provide the conductive lines. This embodiment utilizes separate steps for providing the material of the intermediate contacts and the conductive lines.
A further embodiment comprises a method of forming the interconnection structure, wherein the features of providing the intermediate contacts and the conductive lines comprise etching the second insulating layer to provide conductive line trenches and filling the intermediate contact openings and the conductive line trenches to provide the intermediate contacts and the conductive lines. Here, the intermediate contacts and the conductive lines are formed in a dual damascene process.
According to a further embodiment of the method of forming the interconnection structure, the feature of providing the conductive lines comprises providing a third insulating layer on the second layer and the intermediate contacts, etching the third insulating layer to provide conductive line openings and filling the conductive line openings with a conductive material to provide the conductive lines. This embodiment relates to a damascene process with regard to the conductive lines, wherein the process is integrated into the method of forming the interconnection structure.
A further embodiment relates to a method of forming an interconnection structure comprising providing a substrate, providing a first insulating layer on the substrate, etching, into the first insulating layer, two staggered rows of evenly spaced contact openings, wherein each row extends along a first direction, filling the contact openings with a conductive material to provide contacts, providing a mask structure on the first insulating layer and the contacts, wherein the mask structure partly covers the contacts, etching uncovered portions of the contacts, thereby generating voids and trimming a dimension of the contacts along the first direction in upper contact regions defining intermediate contacts, wherein a lower contact region remains unaltered, filling the voids with an insulating material and providing conductive lines on the first insulating layer and the intermediate contacts, wherein the conductive lines extend along a second direction intersecting the first direction.
According to yet another embodiment of the method of forming an interconnection structure, when filling the voids with the second insulating layer, the second insulating layer is also applied on the first insulating layer and the intermediate contacts. The feature of providing conductive lines comprises etching the second insulating layer to provide conductive line openings and filling the conductive line openings with a conductive material to provide the conductive lines. This embodiment relates to a damascene process with regard to the fabrication of the conductive lines.
A further embodiment comprises a method of forming the interconnection structure, wherein the feature of providing the conductive lines comprises providing a conductive layer on the first insulating layer, the second insulating layer and the intermediate contacts as well as etching the conductive layer to provide the conductive lines.
Exemplary embodiments of the device and method are described in connection with the figures.
The interconnection structure to be formed may serve as bitlines and bitline contacts of a non-volatile memory device, for example. The first insulating layer 1 is applied on a surface of the substrate 4, followed by etching of contact openings into the insulating layer 1 down to the active areas 6. The contact openings are then filled with a conductive material to provide the contacts 2. By way of example, the contact openings may be filled by tungsten CVD (tungsten chemical vapor deposition) followed by CMP (chemical mechanical polishing) to remove tungsten material applied on the surface of the insulating layer 1. As can be gathered from
Referring to
While the invention has been described in detail with reference to a specific embodiment of an arrangement of two contact rows of evenly spaced contacts, i.e., first and second contact rows, it is to be understood that, to one of ordinary skill in the art, the invention further relates to a plurality of first and second contacts rows without departing from the spirit and scope of the appended claims and their equivalents.
Referring to
Next, referring to
A cross-sectional view along the intersection line A-A′ of
Referring to
Referring to
Next,
Referring to
With regard to the cross-sectional view of
Referring to
Turning now to the cross-sectional view of
Referring to
Referring to
Turning now to
Thereafter, as is illustrated in the cross-sectional view of
Referring to
Referring to
A cross-sectional view along the intersection line A-A′ is shown in
Next, referring to
Referring to
Referring to
Referring to the cross-sectional views of
Referring to
In the following, embodiments of a method of forming an interconnection structure will be briefly explained with reference to flowcharts illustrated in
Turning now to
While the invention has been described in detail with reference to specific embodiments thereof, it will be apparent to one of ordinary skill in the art that various changes and modifications can be made therein without departing from the spirit and scope thereof. Accordingly, it is intended that the present invention covers the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.
