Patent Application
20180218666
The present disclosure relates to interface manufacturing technology, and more particularly to an interface device and a liquid crystal device (LCD) with the same.
With the evolution of optical and semiconductor technology, flat panel display (FPD) has been greatly development. Among the FPDs, the LCDs have been adopted in various applications due to the attributes, such as high space utilization rate, low power consumption, no radiation, and low electromagnetic interference.
With respect to the liquid crystal display technology, high-resolution LCDs, such as 8K or 4K, are now available. Among current high resolution LCDs, the interface devices are defined according to the actual needs of manufacturers. However, data signals and control signals may be mixed among the various interface devices, such that the signal quality may be affected, and so does the display performance of the LCDs.
To overcome the above problem, the present disclosure relates to an interface device and the LCD with the same to prevent the signals from being mixed so as to enhance the signal quality.
In one aspect, an interface device for high resolution liquid crystal device (LCD) includes: a first connector configured to receive low voltage differential signals (LVDS) provided for a left-half active area of the LCD, a second connector configured to receive the LVDS provided for a right-half active area of the LCD, and a third connector configured to receive operational voltage signals and control signals provided for the LCD.
Wherein the left-half active area includes N number of left active areas along a direction from left to right in sequence, the first connector includes N number of left-positive-negative-pole-pin pairs, each of the left-positive-negative-pole-pin pairs includes a left-positive-pole-pin and a left-negative-pole-pin, each of the left-positive-pole-pins is configured to receive the positive LVDS provided for the corresponding left active area, and each of the left-negative-pole-pins is configured to receive the negative LVDS provided for the corresponding left active area.
Wherein the first connector further includes grounding pins configured before the N number of the left-positive-negative-pole-pin pairs, the grounding pins configured after the N number of the left-positive-negative-pole-pin pairs, and grounding pins configured between two adjacent left-positive-negative-pole-pin pairs.
Wherein the first connector further includes at least one no-load (NC) pin configured before the grounding pins, wherein the grounding pins are arranged before the N number of the left-positive-negative-pole-pin pairs.
Wherein the right-half active area includes N number of right active areas along a direction from left to right in sequence, the second connector includes N number of right-positive-negative-pole-pin pairs, each of the right-positive-negative-pole-pin pairs includes a right-positive-pole-pin and a right-negative-pole-pin, each of the right-positive-pole-pins is configured to receive the positive LVDS provided for the corresponding right active area, and each of the right-negative-pole-pins is configured to receive the negative LVDS provided for the corresponding right active area.
Wherein the second connector further includes the grounding pins configured before the N number of the right-positive-negative-pole-pin pairs, the grounding pins configured after the N number of the right-positive-negative-pole-pin pairs, and grounding pins configured between two adjacent right-positive-negative-pole-pin pairs.
Wherein the second connector further includes at least one NC pin configured before the grounding pins, wherein the grounding pins are arranged before the N number of the right-positive-negative-pole-pin pairs.
Wherein the third connector includes a plurality of voltage pins and a plurality of signal control pins arranged in sequence, each of the voltage pins is configured to receive the operational voltage signals for the LCD, and each of the signal control pins is configured to receive the control signals for the LCD.
Wherein the third connector further includes at least one NC pin and at least one grounding pin arranged between the voltage pins and the signal control pins in sequence.
In another aspect, the LCD includes the above interface device.
In view of the above, regarding the interface device, the data signals and the control signals are prevented from being mixed. In this way, the received signal quality may be enhanced, and the display performance of the LCD may not be affected.
Various example embodiments will now be described more fully with reference to the accompanying drawings in which some example embodiments are shown. In the drawings, the thicknesses of layers and regions may be exaggerated for clarity. In the following description, in order to avoid the known structure and/or function unnecessary detailed description of the concept of the invention result in confusion, well-known structures may be omitted and/or functions described in unnecessary detail. The same reference numerals in the drawings refer to like elements throughout.
It should be understood that, although the possible use of the terms first, second, etc. are used to describe various components, but the components are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of example embodiments, the first component may be named as a second component, similarly, the second component may be named as the first member.
Referring to
In one embodiment, the active area (AA) is divided into two portions along a direction from left to right, and dimensions of the two portions are the same, however, the present disclosure is not limited to such division. In another example, the active area (AA) is divided into two portions along the direction from top to down, and the dimensions of the two portions are the same.
The left portion is defined as a left-half active area 10, and the right portion is defined as a right-half active area 20.
In the embodiment, the left-half active area 10 is divided into N number of left active areas along the direction from left to right in sequence, and the right-half active area 20 is divided into N number of right active area along the direction from right to left, however, the present disclosure is not limited to such division. In an example, the left-half active area 10 is divided into N number of left active areas along the direction from top to down, and the right-half active area 20 is divided into N number of right active area along the direction from down to top.
In the embodiment, N equals to 16, but the present disclosure is not limited thereto. In an example, N may be a positive integer not smaller than one. As such, the 16 left active areas include a first-left active area 101, a second-left active area 102, a third-left active area 103, a fourth-left active area 104, a fifth-left active area 105, a sixth-left active area 106, a seventh-left active area 107, an eighth-left active area 108, a ninth-left active area 109, a tenth-left active area 110, an eleventh-left active area 111, a twelfth-left active area 112, a thirteenth-left active area 113, a fourteenth-left active area 114, a sixteenth-left active area 115, and a sixteenth-left active area 116. The 16 right active areas include a first-right active area 201, a second-right active area 202, a third-right active area 203, a fourth-right active area 204, a fifth-right active area 205, a sixth-right active area 206, a seventh-right active area 207, an eighth-right active area 208, a ninth-right active area 209, a tenth-right active area 210, an eleventh-right active area 211, a twelfth-right active area 212, a thirteenth-right active area 213, a fourteenth-right active area 214, a sixteenth-right active area 215, and a sixteenth-right active area 216.
Referring to
Specifically, the first connector 30 is configured to receive low voltage differential signals provided for the left-half active area 10 of the LCD, the second connector 40 is configured to receive the low voltage differential signals (LVDS) provided for the right-half active area 20 of the LCD, and the third connector 50 is configured to receive the operational voltage signals and control signals provided for the LCD.
The first connector 30 includes N number of left-positive-negative-pole-pin pairs. Each of the left-positive-negative-pole-pin pairs includes a left-positive-pole-pin and a left-negative-pole-pin. Each of the left-positive-pole-pins is configured to receive the positive LVDS provided for the corresponding left active area, and each of the left-negative-pole-pins is configured to receive the negative LVDS provided for the corresponding left active area.
In an example, the first connector 30 further includes grounding pins configured before the N number of the left-positive-negative-pole-pin pairs, the grounding pins configured after the N number of the left-positive-negative-pole-pin pairs, and grounding pins configured between two adjacent left-positive-negative-pole-pin pairs.
In an example, the first connector 30 further includes at least one no-load (NC) pin configured before the grounding pins, wherein the grounding pins are arranged before the N number of the left-positive-negative-pole-pin pairs.
In one example, N equals to 16. That is, the first connector 30 includes 16 left-positive-negative-pole-pin pairs, which include 16 left-positive-pole pin and 16 left-negative-pole pin. In addition, in one example, the NC pins configured before the grounding pins (GND) that are arranged before the N number of the left-positive-negative-pole-pin pairs.
Table. 1 shows the configuration of the first connector 30 in accordance with one embodiment.
The first left-positive-pole pin 301P through the sixteenth left-positive-pole pin 316P respectively corresponds to the positive LVDS provided to the first-left active area 101 through the sixteenth-left active area 116, and the first left-negative-pole pin 301N through the sixteenth left-negative-pole pin 316N respectively corresponds to the negative LVDS provided to the first-left active area 101 through the sixteenth-left active area 116.
The second connector 40 includes N number of right-positive-negative-pole-pin pairs. Each of the right-positive-negative-pole-pin pairs includes a right-positive-pole-pin and a right-negative-pole-pin. Each of the right-positive-pole-pins is configured to receive the positive LVDS provided for the corresponding right active area, and each of the right-negative-pole-pins is configured to receive the negative LVDS provided for the corresponding right active area.
In an example, the second connector 40 further includes the grounding pins configured before the N number of the right-positive-negative-pole-pin pairs, the grounding pins (GND) configured after the N number of the right-positive-negative-pole-pin pairs, and grounding pins (GND) configured between two adjacent right-positive-negative-pole-pin pairs.
In an example, the second connector 40 further includes at least one no-load (NC) pin configured before the grounding pins (GND), wherein the grounding pins (GND) are arranged before the N number of the right-positive-negative-pole-pin pairs.
In one example, N equals to 16. That is, the second connector 40 includes 16 right-positive-negative-pole-pin pairs, which include 16 right-positive-pole pin and 16 right-negative-pole pin. In addition, in one example, two NC pins are configured before the grounding pins (GND) arranged before the N number of the right-positive-negative-pole-pin pairs, but the present disclosure is not limited thereto.
Table. 2 shows the configuration of the second connector 40 in accordance with one embodiment.
The first right-positive-pole pin 401P through the sixteenth right-positive-pole pin 416P respectively corresponds to the positive LVDS provided to the first-right active area 201 through the sixteenth-right active area 216, and the first right-negative-pole pin 401N through the sixteenth right-negative-pole pin 416N respectively corresponds to the negative LVDS provided to the first-right active area 201 through the sixteenth-right active area 26.
The third connector 50 includes a plurality of voltage pins and a plurality of signal control pins. Each of the voltage pins is configured to receive the operational voltage signals for the LCD, and each of the signal control pins is configured to receive the control signals for the LCD. In one embodiment, the first connector 30 includes 20 voltage pins and 9 signal control pins.
The third connector 50 further includes at least one NC pin and at least one grounding pin (GND) arranged between the voltage pins and the signal control pins in sequence. In one embodiment, the first connector 30 includes two NC pins and 10 grounding pin (GND).
Table. 3 shows the configuration of the third connector 50 in accordance with one embodiment.
Each of the voltage pins 501 is configured to receive the operational voltage signals provided for the LCD, and each of the signal control pins 502 is configured to receive the control signals provided for the LCD.
In view of the above, regarding the interface device, the data signals and the control signals are prevented from being mixed. In this way, the received signal quality may be enhanced, and the display performance of the LCD may not be affected.
It is believed that the present embodiments and their advantages will be understood from the foregoing description, and it will be apparent that various changes may be made thereto without departing from the spirit and scope of the invention or sacrificing all of its material advantages, the examples hereinbefore described merely being preferred or exemplary embodiments of the invention.
| Number | Date | Country | Kind |
|---|---|---|---|
| 201610377836.2 | May 2016 | CN | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CN2016/090513 | 7/19/2016 | WO | 00 |
