Patent Application
20140350891
The disclosed embodiments generally relate to techniques for communicating data between electronic devices. More specifically, the disclosed embodiments relate to techniques for transferring time-sampled sensor data from a sensor device to a host system.
As mobile computing devices (such as smartphones) become increasingly more sophisticated, they are beginning to incorporate a variety of sensors for gathering different types of data, such as accelerometer data, gyroscope data, ambient-light sensor data, GPS data, and even barometer data. However, existing techniques for transferring data from sensors to associated processing circuitry are not well-suited for portable computing devices because they use extra wires, consume unnecessary power, and have problems synchronizing timing between a jittery sensor clock and a more stable application-processor clock.
Hence, what is needed is a technique for transferring sensor data to associated processing circuitry without the above-described problems.
The disclosed embodiments relate to a system for transmitting data from a sensor to a host. During operation, the system periodically samples data at the sensor with reference to a sensor clock. Next, the system uses the sensor clock to transmit the data from the sensor to the host, wherein the host operates with reference to a host clock, which is different than the sensor clock. During this transmission process, the system embeds a clock in the data, wherein the embedded clock can be extracted at the host and used to receive the transmitted data.
In some embodiments, transmitting the data involves using voltage-mode signaling to transmit the data.
In some embodiments, the voltage-mode signaling involves using an interface with three lines, including a power line, a ground line, and a data-carrying line.
In some embodiments, transmitting the data involves using current-mode signaling to transmit the data.
In some embodiments, the current-mode signaling involves using an interface with two lines, including a ground line and a data-carrying line, which also serves as a power line.
In some embodiments, the sensor receives power from the host through a power line that is part of an interface between the sensor and the host.
In some embodiments, transmitting the data involves scrambling the data prior to transmission to ensure that a frequency spectrum of the transmitted signals is evenly distributed across a range of frequencies. In some embodiments, this scrambling is accomplished by using a Linear Feedback Shift Register (LFSR).
In some embodiments, transmitting the data involves transmitting three channels of sensor data using a frame format that supports two channels of data.
Table 1 illustrates various preamble definitions in accordance with the disclosed embodiments.
The following description is presented to enable any person skilled in the art to make and use the disclosed embodiments, and is provided in the context of a particular application and its requirements. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the disclosed embodiments. Thus, the disclosed embodiments are not limited to the embodiments shown, but are to be accorded the widest scope consistent with the principles and features disclosed herein.
The data structures and code described in this detailed description are typically stored on a computer-readable storage medium, which may be any device or medium that can store code and/or data for use by a system. The computer-readable storage medium includes, but is not limited to, volatile memory, non-volatile memory, magnetic and optical storage devices such as disk drives, magnetic tape, CDs (compact discs), DVDs (digital versatile discs or digital video discs), or other media capable of storing code and/or data now known or later developed.
The methods and processes described in the detailed description section can be embodied as code and/or data, which can be stored on a non-transitory computer-readable storage medium as described above. When a system reads and executes the code and/or data stored on the non-transitory computer-readable storage medium, the system performs the methods and processes embodied as data structures and code and stored within the non-transitory computer-readable storage medium.
Furthermore, the methods and processes described below can be included in hardware modules. For example, the hardware modules can include, but are not limited to, application-specific integrated circuit (ASIC) chips, field-programmable gate arrays (FPGAs), and other programmable-logic devices now known or later developed. When the hardware modules are activated, the hardware modules perform the methods and processes included within the hardware modules.
The disclosed embodiments provide an interface to support unidirectional digital data transfer with an embedded clock between a sensor device, such as an accelerometer, and a host device, such as a smartphone. In typical applications, the interface uses a length of wire to connect the sensor and the host, wherein the sensor and the host do not reside on the same PCB. Moreover, power nets on the sensor device PCB are derived from corresponding power nets on the host device PCB. This interface was designed with a number of goals in mind, including: (1) synchronizing clock domains between the sensor and the host; (2) low wire count between the sensor and the host; (3) ensuring that the frequency spectrum of the transmitted signals is evenly distributed across a range of frequencies; (4) transferring power for the host to the sensor; and (5) low power consumption. Various embodiments of the interface are described in more detail below.
Within sensor device 102, a sensor 104, such as an accelerometer, outputs a signal that is periodically sampled by a sampler circuit 105 to produce a stream of data values, which is sent to a transmitter 106. Transmitter 106 communicates this stream of data values through a cable 130 to a receiver 126 in host 110, wherein cable 130 includes two or more lines as is described in more detail below. Sampler 105 and transmitter 106 operate with reference to a sensor clock 101, which is generated locally by circuitry within sensor device 102.
Within host 110, receiver 126 can perform various synchronization and sample-rate-conversion operations on the stream of data, and then communicates the stream of data values to an application processor 127, which can process the stream of data values. Receiver 126 and application processor 127 operate with reference to a host clock 128, which is generated locally by circuitry within host 110.
In some embodiments, transmitter 106 and receiver 126 are configurable to provide either voltage-mode signaling or current-mode signaling as is described in more detail below.
To support voltage-mode signaling, transmitter 106 can function as a single-ended voltage-signaled interface with push-pull drivers. More specifically,
In some embodiments, because of the unidirectional architecture of the interface, host 110 uses the power path to sensor device 102 to change the state of the device. In these embodiments, sensor device 102 can be enabled or disabled by simply applying or removing power.
In
Yet another embodiment is illustrated in
Another optimization that appears in the top right-hand corner of
Some of the disclosed embodiments use biphase mark code (BMC) to encode the data on the bus. In this encoding, each time slot (encoded-bit period) is guaranteed to have one transition (H to L or L to H), which occurs at the start of the time slot. A ‘0’ is encoded as having only one transition in one time slot, while a ‘1’ is encoded as having two transitions. The extra transition that an encoded ‘1’ uses occurs at the midpoint of the time slot. Thus, if a single time slot is represented by two unit interval bus states (H or L), the bit string “000” can be encoded as “LLHHLL”. Similarly, the bit string “111” can be encoded as “LHLHLH”.
One exception to the rule outlined above regarding the guarantee of one transition per time slot is the use of preambles. In some embodiments, there are two preambles, denoted X and Z. Each of these preambles is four time slots in length and employs two violations of BMC (two time slots are started with no transition) so that the receiver may easily acquire a lock on the bit stream. Because these are violations of BMC, they cannot be represented as a bit string, but can instead be represented by the bus state per unit interval. (See Table 1 above, which defines these preambles.)
The exemplary frame format illustrated in
The control sequence at the end of channel B is a 4-bit cyclic redundancy check (CRC), which is calculated based on the unscrambled 48-bits of data contained in the combined channels in a frame. This CRC is appended directly after the 24 bits of data in Channel B. The following generating polynomial can be used to calculate this CRC:
Q(x)=x4+1
Note that CRCs are calculated LSB-first and transmitted LSB-first, due to the LSB-first nature of the interface.
The AES3 standard provides for sending 24-bits of data on a single channel, and the disclosed embodiments adapt this 24-bit frame to allow for three channels of 16-bit data to be repackaged into two channels of 24-bit data. The least significant bytes (LSBs) from each of the three 16-bit channels are concatenated to form the 24-bit data payload of Channel A. Similarly, the most significant bytes (MSBs) from each of the three 16-bit channels are concatenated to form the 24-bit data payload of Channel B. The orientation of the samples is least significant bit first.
If the device produces N-bit samples that are less than 16 bits in length, the samples are zero-padded from the LSB to produce 16-bit samples, wherein the N-bit sample occupies the N-most significant bits of the 16-bit output sample.
During operation, it is possible for the data pattern to cause the frequency content on the interface to be clustered around a specific frequency (i.e., a stream of zeros from the device). Therefore, the data is scrambled prior to BMC encoding to ensure that the frequency content on the interface remains evenly distributed.
As specified in the IEEE 1394b-2002 standard, the system can employ a side stream scrambler that uses the following generating polynomial:
G(x)=x11+x9+1.
This generating polynomial defines a linear feedback shift register (LFSR) that operates at the bit clock rate of the interface and continuously generates the kth value of the scrambler shift register. The scrambler shift register also operates at the bit clock rate of the interface and has an output value defined by Scr(k:k+7). Based on the generating polynomial, the output of the LFSR and input to the scrambler shift register can be defined as follows:
Scr(k)=Scr(k−9)XOR Scr(k−11).
This scrambling occurs before both the framing and BMC encoding is done on the sensor device side of the interface. Note that the bytes of data to be placed in a frame are first passed through the side-stream scrambler in the order that they will be transmitted.
Even though preambles and the SS and CRC sequences are not scrambled, the clock of the portion of the scrambler that operates at the bit clock rate of the interface is still running during the times preambles and the SS/CRC are being transmitted.
The 4-bit SS control sequence, which is transmitted after Channel A's 24 data bits are transmitted, is used to send a snapshot of a portion of the device's scrambler to the host so that the host can reconstruct the state of the scrambler. The four bits to send are defined as follows:
SS[3:0]={Scr[k],Scr[k+2],Scr[k+4],Scr[k+6]}.
As with the data and the CRC, the SS sequence is sent LSB-first.
Then, the system receives data from the sensor at a host (step 608), and extracts the embedded clock from the received data (step 610). The system subsequently uses the extracted clock to receive data from the sensor (step 612).
Next, the system reorders these bytes to produce a byte ordering 702 for input to the scrambler (710, 720, 730, 711, 721 and 731). The system then performs a CRC computation 740 and performs a pre-framing operation to generate a frame-in-process 703. Finally, the system performs a scrambling operation 750 on data values in this frame-in-process (using an LFSR), and also generates the preambles X and Z to produce a frame-to-be-transmitted 704 prior to encoding for transmission.
When the transmitted frame is ultimately received at the host, the process illustrated in
The foregoing descriptions of disclosed embodiments have been presented only for purposes of illustration and description. They are not intended to be exhaustive or to limit the disclosed embodiments to the forms disclosed. Accordingly, many modifications and variations will be apparent to practitioners skilled in the art. Additionally, the above disclosure is not intended to limit the disclosed embodiments. The scope of the disclosed embodiments is defined by the appended claims.
