Patent Application
20160274612
The subject matter herein generally relates to power supply circuits.
Some interfaces are mounted in a motherboard. A power supply unit supplies power to the interfaces. A corresponding device is configured to be inserted into an interface, for example, a PCIe device can be inserted into the PCIe interface.
Implementations of the present technology will now be described, by way of example only, with reference to the attached figures.
It will be appreciated that for simplicity and clarity of illustration, where appropriate, reference numerals have been repeated among the different figures to indicate corresponding or analogous elements. In addition, numerous specific details are set forth in order to provide a thorough understanding of the embodiments described herein. However, it will be understood by those of ordinary skill in the art that the embodiments described herein can be practiced without these specific details. In other instances, components have not been described in detail so as not to obscure the related relevant feature being described. Also, the description is not to be considered as limiting the scope of the embodiments described herein. The drawings are not necessarily to scale and the proportions of certain parts may be exaggerated to better illustrate details and features of the present disclosure.
Several definitions that apply throughout this disclosure will now be presented.
The term “coupled” is defined as connected, whether directly or indirectly through intervening components, and is not necessarily limited to physical connections. The connection can be such that the objects are permanently connected or releasably connected. The term “comprising,” when utilized, means “including, but not necessarily limited to”; it specifically indicates open-ended inclusion or membership in the so-described combination, group, series, and the like.
The present disclosure is described in relation to a power supply circuit which can be used to supply power to a PCIe interface.
The power supply unit 10 comprises a first power supply 11, a second power supply 13, and a third power supply 15. In one embodiment, the first power supply 11 is configured to provide a 3V voltage, the second power supply 13 is configured to provide a 3V voltage, and the third power supply 15 is configured to provide a 12V voltage.
The control unit 20 comprises a first control circuit 21, a second control circuit 23, and a third control circuit 25.
The detection unit 30 comprises a detection chip 31 and a fourth control circuit 33. In one embodiment, the detection chip 31 is a PCH chip and is configured to detect whether the interface 40 receives a PCIe device.
The fourth control circuit 33 comprises a fourth resistor R4 and a fourth power supply 35.
The interface 40 comprises a control pin 41, a first power supply pin 42, a second power supply pin 43, and a third power supply pin 44.
The detection chip 31 is coupled to a node 37. The node 37 is coupled to one end of the fourth resistor R4. The other end of the fourth resistor R4 is coupled to the fourth power supply 35. The node 37 is coupled to the control pin 41 of the interface 40. The node 37 is coupled to one end of the first resistor R1. The other end of the first resistor R1 is coupled to the control terminal G of the first FET Q1. The control terminal G of the first FET Q1 is coupled to the first connecting terminal S of the first FET Q1 via the first capacitor C1. The second connecting terminal D of the first FET Q1 is coupled to the first power supply 11. The first connecting terminal S of the first FET Q1 is coupled to the first power supply pin 42 of the interface 40.
The node 37 is coupled to one end of the second resistor R2. The other end of the second resistor R2 is coupled to the control terminal G of the second FET Q2. The control terminal G of the second FET Q is coupled to the first connecting terminal S of the second FET Q2 via the second capacitor C2. The second connecting terminal D of the second FET Q2 is coupled to the second power supply 13. The first connecting terminal S of the second FET Q2 is coupled to the second power supply pin 43 of the interface 40.
The node 37 is coupled to one end of the third resistor R3. The other end of the third resistor R3 is coupled to the control terminal G of the third FET Q3. The control terminal G of the third FET Q3 is coupled to the first connecting terminal S of the third FET Q3 via the third capacitor C3. The second connecting terminal D of the second FET Q2 is coupled to the third power supply 15. The first connecting terminal S of the third FET Q3 is coupled to the third power supply pin 44 of the interface 40.
In one embodiment, each of the first FET Q1, the second FET Q2, and the third FET Q3 is an n-channel FET, each control terminal G is a gate terminal, each first connecting terminal S is a source terminal, and each second connecting terminal D is a drain terminal.
A working principle of the interface supply circuit is as follows. When the detection chip 31 detects a PCIe device is inserted into the interface 40, the detection unit 30 outputs a first control signal. The first FET Q1, the second FET Q2, and the third FET Q3 are switched on after receiving the first control signal. The first power supply 11, the second power supply 13, and the third power supply 15 supply power to the interface 40. When the detection chip 31 detects no PCIe device is inserted into the interface 40, the detection unit 30 outputs a second control signal. The first FET Q1, the second FET Q2, and the third FET Q3 are switched off after receiving the second control signal. The first power supply 11, the second power supply 13, and the third power supply 15 do not supply power to the interface 40, thereby decreasing power and preventing short circuit when conductive materials drop into the interface 40. In one embodiment, the first control signal is a low level signal and the second control signal is a high level signal.
It is to be understood that even though numerous characteristics and advantages have been set forth in the foregoing description of embodiments, together with details of the structures and functions of the embodiments, the disclosure is illustrative only and changes may be made in detail, including in the matters of shape, size, and arrangement of parts within the principles of the disclosure to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.
| Number | Date | Country | Kind |
|---|---|---|---|
| 201510118461.3 | Mar 2015 | CN | national |
