Patent Application
20160139648
This application claims priority to Chinese Patent Application No. 201410639142.2 Nov. 13, 2014, the contents of which are incorporated by reference herein.
The subject matter herein generally relates to power conservation.
An interface supply circuit may be used to decrease power consumption.
Implementations of the present technology will now be described, by way of example only, with reference to the attached figures.
It will be appreciated that for simplicity and clarity of illustration, where appropriate, reference numerals have been repeated among the different figures to indicate corresponding or analogous elements. In addition, numerous specific details are set forth in order to provide a thorough understanding of the embodiments described herein. However, it will be understood by those of ordinary skill in the art that the embodiments described herein can be practiced without these specific details. In other instances, components have not been described in detail so as not to obscure the related relevant feature being described. Also, the description is not to be considered as limiting the scope of the embodiments described herein. The drawings are not necessarily to scale and the proportions of certain parts may be exaggerated to better illustrate details and features of the present disclosure.
Several definitions that apply throughout this disclosure will now be presented.
The term “coupled” is defined as connected, whether directly or indirectly through intervening components, and is not necessarily limited to physical connections. The connection can be such that the objects are permanently connected or releasably connected. The term “comprising,” when utilized, means “including, but not necessarily limited to”; it specifically indicates open-ended inclusion or membership in the so-described combination, group, series, and the like.
The present disclosure is described in relation to an interface supply circuit used to decrease power consumption.
The control chip 20 comprises a connecting pin 21 and a control pin 23.
The control circuit 30 comprises a first field effect transistor (FET) Q1 and a second FET Q2. In one embodiment, the first FET Q1 is a P-channel MOSFET and the second FET Q2 is a N-channel MOSFET.
The interface 50 comprises a power supply pin 51 and a detection pin 53.
The power supply 10 coupled to a source terminal S of the first FET Q1. The power supply 10 is coupled to a drain terminal D of the second FET Q2 via a first resistor R1. A gate terminal G of the first FET Q1 is coupled to a drain terminal D of the second FET Q2. A drain terminal D of the first FET Q1 is coupled to the power supply pin 51 of the interface 50. A source terminal S of the second FET Q2 is grounded. Agate terminal G of the second FET Q2 is coupled to the control pin 23 of the control chip 20. The connecting pin 21 of the control chip 20 is coupled to the connecting terminal 41 of the detection chip 40. The detection terminal 43 of the detection chip 40 is coupled to the detection pin 53 of the interface 50. The detection terminal 41 of the detection chip 40 is coupled to the power supply 10 via a second resistor R2.
At block 101, the detection chip 40 detects the computer is shutdown.
At block 102, the detection chip 40 determines whether the hardware device is inserted into the interface 50, if yes, the method goes to block 103; if no, the method goes to block 109.
At block 103, the detection chip 40 determines whether the hardware device is a wireless card, if yes, the method goes to block 105; if no, the method goes to block 107.
At block 104, the detection chip 40 sends a triggered signal to the control chip 20.
At block 105, the control chip 20 sends a connect signal to the control circuit 30.
At block 106, the power supply 10 supplies power to the interface 50.
At block 107, the detection chip 40 sends a stop signal to the control chip 20.
At block 108, the control chip 20 sends a disconnect signal to the control circuit 30.
At block 109, the power supply 10 does not supply power to the interface 50.
In the interface supply circuit, the detection chip 40 sends the stop signal to the control chip 20, when the computer is shutdown and the detection chip 40 detects no wireless card is inserted into the interface 50. The control chip 20 sends the disconnect signal to the control circuit 30 after receiving the stop signal, thereby the second FET Q2 is switched off after which the first FET Q1 is switched off. The power supply 10 does not supply power to the interface 50, thus decreasing the power consumption. In one embodiment, the connect signal is a high level signal, the disconnect signal is a low level signal.
It is to be understood that even though numerous characteristics and advantages have been set forth in the foregoing description of embodiments, together with details of the structures and functions of the embodiments, the disclosure is illustrative only and changes may be made in detail, including in the matters of shape, size, and arrangement of parts within the principles of the disclosure to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.
| Number | Date | Country | Kind |
|---|---|---|---|
| 201410639142.2 | Nov 2014 | CN | national |
